Total rewrite.
The PIC is now split up in 2 units, like the real thing. There are now less hacks in the code in order to deal with the irq 2 being active/inservice. IRQ 2 now needs to be acknowledged by the interrupt handler for IRQs that happen on the slave PIC. Fixes Pyl sound effects with low cycles and hopefully others. Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3792
This commit is contained in:
Peter Veenstra
parent
d95950242d
commit
0157fcf8fa
1 changed files with 218 additions and 216 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2002-2011 The DOSBox Team
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* Copyright (C) 2002-2012 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,9 +16,6 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <list>
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#include "dosbox.h"
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#include "inout.h"
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#include "cpu.h"
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@ -29,35 +26,144 @@
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#define PIC_QUEUESIZE 512
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struct IRQ_Block {
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bool masked;
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bool active;
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bool inservice;
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Bitu vector;
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};
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struct PIC_Controller {
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Bitu icw_words;
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Bitu icw_index;
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Bitu masked;
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bool special;
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bool auto_eoi;
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bool rotate_on_auto_eoi;
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bool single;
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bool request_issr;
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Bit8u vector_base;
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Bit8u irr; // request register
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Bit8u imr; // mask register
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Bit8u imrr; // mask register reversed (makes bit tests simpler)
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Bit8u isr; // in service register
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Bit8u isrr; // in service register reversed (makes bit tests simpler)
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Bit8u active_irq; //currently active irq
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void set_imr(Bit8u val);
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void check_after_EOI(){
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//Update the active_irq as an EOI is likely to change that.
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update_active_irq();
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if((irr&imrr)&isrr) check_for_irq();
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}
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void update_active_irq() {
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if(isr == 0) {active_irq = 8; return;}
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for(Bit8u i = 0, s = 1; i < 8;i++, s<<=1){
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if( isr & s){
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active_irq = i;
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return;
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}
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}
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}
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void check_for_irq(){
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const Bit8u possible_irq = (irr&imrr)&isrr;
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if (possible_irq) {
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const Bit8u a_irq = special?8:active_irq;
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for(Bit8u i = 0, s = 1; i < a_irq;i++, s<<=1){
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if ( possible_irq & s ) {
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//There is an irq ready to be served => signal master and/or cpu
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activate();
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return;
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}
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}
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}
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deactivate(); //No irq, remove signal to master and/or cpu
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}
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//Signals master/cpu that there is an irq ready.
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void activate();
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//Removes signal to master/cpu that there is an irq ready.
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void deactivate();
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void raise_irq(Bit8u val){
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Bit8u bit = 1 << (val);
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if((irr & bit)==0) { //value changed (as it is currently not active)
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irr|=bit;
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if((bit&imrr)&isrr) { //not masked and not in service
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if(special || val < active_irq) activate();
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}
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}
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}
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void lower_irq(Bit8u val){
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Bit8u bit = 1 << ( val);
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if(irr & bit) { //value will change (as it is currently active)
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irr&=~bit;
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if((bit&imrr)&isrr) { //not masked and not in service
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//This irq might have toggled PIC_IRQCheck/caused irq 2 on master, when it was raised.
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//If it is active, then recheck it, we can't just deactivate as there might be more IRQS raised.
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if(special || val < active_irq) check_for_irq();
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}
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}
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}
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//handles all bits and logic related to starting this IRQ, it does NOT start the interrupt on the CPU.
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void start_irq(Bit8u val);
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};
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Bitu PIC_Ticks=0;
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Bitu PIC_IRQCheck;
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Bitu PIC_IRQOnSecondPicActive;
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Bitu PIC_IRQActive;
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static IRQ_Block irqs[16];
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static PIC_Controller pics[2];
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static bool PIC_Special_Mode = false; //Saves one compare in the pic_run_irqloop
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static PIC_Controller& master = pics[0];
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static PIC_Controller& slave = pics[1];
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Bitu PIC_Ticks = 0;
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Bitu PIC_IRQCheck = 0; //Maybe make it a bool and/or ensure 32bit size (x86 dynamic core seems to assume 32 bit variable size)
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void PIC_Controller::set_imr(Bit8u val) {
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if (GCC_UNLIKELY(machine==MCH_PCJR)) {
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//irq 6 is a NMI on the PCJR
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if (this == &master) val &= ~(1 <<(6));
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}
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Bit8u change = (imr) ^ (val); //Bits that have changed become 1.
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imr = val;
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imrr = ~val;
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//Test if changed bits are set in irr and are not being served at the moment
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//Those bits have impact on whether the cpu emulation should be paused or not.
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if((irr & change)&isrr) check_for_irq();
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}
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void PIC_Controller::activate() {
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//Stops CPU if master, signals master if slave
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if(this == &master) {
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PIC_IRQCheck = 1;
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//cycles 0, take care of the port IO stuff added in raise_irq base caller.
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CPU_CycleLeft += CPU_Cycles;
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CPU_Cycles = 0;
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//maybe when coming from a EOI, give a tiny delay. (for the cpu to pick it up) (see PIC_Activate_IRQ)
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} else {
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master.raise_irq(2);
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}
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}
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void PIC_Controller::deactivate() {
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//removes irq check value if master, signals master if slave
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if(this == &master) {
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PIC_IRQCheck = 0;
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} else {
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master.lower_irq(2);
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}
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}
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void PIC_Controller::start_irq(Bit8u val){
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irr&=~(1<<(val));
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if (!auto_eoi) {
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active_irq = val;
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isr |= 1<<(val);
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isrr = ~isr;
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} else if (GCC_UNLIKELY(rotate_on_auto_eoi)) {
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E_Exit("rotate on auto EOI not handled");
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}
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}
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struct PICEntry {
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float index;
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Bitu value;
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static void write_command(Bitu port,Bitu val,Bitu iolen) {
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PIC_Controller * pic=&pics[port==0x20 ? 0 : 1];
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Bitu irq_base=port==0x20 ? 0 : 8;
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Bitu i;
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static Bit16u IRQ_priority_table[16] =
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{ 0,1,2,8,9,10,11,12,13,14,15,3,4,5,6,7 };
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if (GCC_UNLIKELY(val&0x10)) { // ICW1 issued
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if (val&0x04) E_Exit("PIC: 4 byte interval not handled");
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if (val&0x08) E_Exit("PIC: level triggered mode not handled");
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@ -93,40 +196,24 @@ static void write_command(Bitu port,Bitu val,Bitu iolen) {
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if (val&0x40) { // special mask select
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if (val&0x20) pic->special = true;
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else pic->special = false;
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if (pics[0].special || pics[1].special)
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PIC_Special_Mode = true; else
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PIC_Special_Mode = false;
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if (PIC_IRQCheck) { //Recheck irqs
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CPU_CycleLeft += CPU_Cycles;
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CPU_Cycles = 0;
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}
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//Check if there are irqs ready to run, as the priority system has possibly been changed.
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pic->check_for_irq();
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LOG(LOG_PIC,LOG_NORMAL)("port %X : special mask %s",port,(pic->special)?"ON":"OFF");
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}
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} else { // OCW2 issued
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if (val&0x20) { // EOI commands
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if (GCC_UNLIKELY(val&0x80)) E_Exit("rotate mode not supported");
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if (val&0x40) { // specific EOI
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if (PIC_IRQActive==(irq_base+val-0x60U)) {
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irqs[PIC_IRQActive].inservice=false;
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PIC_IRQActive=PIC_NOIRQ;
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for (i=0; i<=15; i++) {
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if (irqs[IRQ_priority_table[i]].inservice) {
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PIC_IRQActive=IRQ_priority_table[i];
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break;
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}
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}
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}
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pic->isr &= ~(1<< ((val-0x60)));
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pic->isrr = ~pic->isr;
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pic->check_after_EOI();
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// if (val&0x80); // perform rotation
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} else { // nonspecific EOI
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if (PIC_IRQActive<(irq_base+8)) {
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irqs[PIC_IRQActive].inservice=false;
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PIC_IRQActive=PIC_NOIRQ;
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for (i=0; i<=15; i++){
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if(GCC_UNLIKELY(irqs[IRQ_priority_table[i]].inservice)) {
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PIC_IRQActive=IRQ_priority_table[i];
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break;
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}
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}
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if (pic->active_irq != 8) {
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//If there is no irq in service, ignore the call, some games send an eoi to both pics when a sound irq happens (regardless of the irq).
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pic->isr &= ~(1 << (pic->active_irq));
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pic->isrr = ~pic->isr;
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pic->check_after_EOI();
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}
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// if (val&0x80); // perform rotation
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}
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@ -143,43 +230,13 @@ static void write_command(Bitu port,Bitu val,Bitu iolen) {
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static void write_data(Bitu port,Bitu val,Bitu iolen) {
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PIC_Controller * pic=&pics[port==0x21 ? 0 : 1];
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Bitu irq_base=(port==0x21) ? 0 : 8;
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Bitu i;
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bool old_irq2_mask = irqs[2].masked;
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switch(pic->icw_index) {
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case 0: /* mask register */
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LOG(LOG_PIC,LOG_NORMAL)("%d mask %X",port==0x21 ? 0 : 1,val);
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for (i=0;i<=7;i++) {
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irqs[i+irq_base].masked=(val&(1<<i))>0;
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if(port==0x21) {
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if (irqs[i+irq_base].active && !irqs[i+irq_base].masked) PIC_IRQCheck|=(1 << (i+irq_base));
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else PIC_IRQCheck&=~(1 << (i+irq_base));
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} else {
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if (irqs[i+irq_base].active && !irqs[i+irq_base].masked && !irqs[2].masked) PIC_IRQCheck|=(1 << (i+irq_base));
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else PIC_IRQCheck&=~(1 << (i+irq_base));
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}
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}
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if (machine==MCH_PCJR) {
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/* irq6 cannot be disabled as it serves as pseudo-NMI */
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irqs[6].masked=false;
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}
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if(irqs[2].masked != old_irq2_mask) {
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/* Irq 2 mask has changed recheck second pic */
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for(i=8;i<=15;i++) {
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if (irqs[i].active && !irqs[i].masked && !irqs[2].masked) PIC_IRQCheck|=(1 << (i));
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else PIC_IRQCheck&=~(1 << (i));
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}
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}
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if (PIC_IRQCheck) {
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CPU_CycleLeft+=CPU_Cycles;
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CPU_Cycles=0;
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}
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pic->set_imr(val);
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break;
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case 1: /* icw2 */
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LOG(LOG_PIC,LOG_NORMAL)("%d:Base vector %X",port==0x21 ? 0 : 1,val);
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for (i=0;i<=7;i++) {
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irqs[i+irq_base].vector=(val&0xf8)+i;
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};
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pic->vector_base = val&0xf8;
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if(pic->icw_index++ >= pic->icw_words) pic->icw_index=0;
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else if(pic->single) pic->icw_index=3; /* skip ICW3 in single mode */
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break;
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@ -214,82 +271,70 @@ static void write_data(Bitu port,Bitu val,Bitu iolen) {
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static Bitu read_command(Bitu port,Bitu iolen) {
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PIC_Controller * pic=&pics[port==0x20 ? 0 : 1];
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Bitu irq_base=(port==0x20) ? 0 : 8;
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Bitu i;Bit8u ret=0;Bit8u b=1;
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if (pic->request_issr) {
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for (i=irq_base;i<irq_base+8;i++) {
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if (irqs[i].inservice) ret|=b;
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b <<= 1;
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}
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} else {
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for (i=irq_base;i<irq_base+8;i++) {
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if (irqs[i].active) ret|=b;
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b <<= 1;
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}
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if (irq_base==0 && (PIC_IRQCheck&0xff00)) ret |=4;
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if (pic->request_issr){
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return pic->isr;
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} else {
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return pic->irr;
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}
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return ret;
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}
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static Bitu read_data(Bitu port,Bitu iolen) {
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Bitu irq_base=(port==0x21) ? 0 : 8;
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Bitu i;Bit8u ret=0;Bit8u b=1;
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for (i=irq_base;i<=irq_base+7;i++) {
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if (irqs[i].masked) ret|=b;
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b <<= 1;
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}
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return ret;
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PIC_Controller * pic=&pics[port==0x21 ? 0 : 1];
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return pic->imr;
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}
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void PIC_ActivateIRQ(Bitu irq) {
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if (GCC_UNLIKELY(CPU_Cycles)) {
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// CPU_Cycles nonzero means the interrupt was triggered by an I/O
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Bitu t = irq>7 ? (irq - 8): irq;
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PIC_Controller * pic=&pics[irq>7 ? 1 : 0];
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Bit32s OldCycles = CPU_Cycles;
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pic->raise_irq(t); //Will set the CPU_Cycles to zero if this IRQ will be handled directly
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if (GCC_UNLIKELY(OldCycles != CPU_Cycles)) {
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// if CPU_Cycles have changed, this means that the interrupt was triggered by an I/O
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// register write rather than an event.
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// Real hardware executes 0 to ~13 NOPs or comparable instructions
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// before the processor picks up the interrupt. Let's try with 2
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// cycles here.
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// Required by Panic demo (irq0), It came from the desert (MPU401)
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// Does it matter if CPU_CycleLeft becomes negative?
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CPU_CycleLeft += (CPU_Cycles-2);
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CPU_Cycles=2;
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}
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if( irq < 8 ) {
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irqs[irq].active = true;
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if (!irqs[irq].masked) {
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PIC_IRQCheck|=(1 << irq);
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}
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} else if (irq < 16) {
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irqs[irq].active = true;
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PIC_IRQOnSecondPicActive|=(1 << irq);
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if (!irqs[irq].masked && !irqs[2].masked) {
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PIC_IRQCheck|=(1 << irq);
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}
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// It might be an idea to do this always in order to simulate this
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// So on write mask and EOI as well. (so inside the activate function)
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// CPU_CycleLeft += (CPU_Cycles-2);
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CPU_CycleLeft -= 2;
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CPU_Cycles = 2;
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}
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}
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void PIC_DeActivateIRQ(Bitu irq) {
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if (irq<16) {
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irqs[irq].active=false;
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PIC_IRQCheck&=~(1 << irq);
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PIC_IRQOnSecondPicActive&=~(1 << irq);
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}
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Bitu t = irq>7 ? (irq - 8): irq;
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PIC_Controller * pic=&pics[irq>7 ? 1 : 0];
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pic->lower_irq(t);
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}
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static inline bool PIC_startIRQ(Bitu i) {
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/* irqs on second pic only if irq 2 isn't masked */
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if( i > 7 && irqs[2].masked) return false;
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irqs[i].active = false;
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PIC_IRQCheck&= ~(1 << i);
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PIC_IRQOnSecondPicActive&= ~(1 << i);
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CPU_HW_Interrupt(irqs[i].vector);
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Bitu pic=(i&8)>>3;
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if (!pics[pic].auto_eoi) { //irq 0-7 => pic 0 else pic 1
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PIC_IRQActive = i;
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irqs[i].inservice = true;
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} else if (GCC_UNLIKELY(pics[pic].rotate_on_auto_eoi)) {
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E_Exit("rotate on auto EOI not handled");
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static void slave_startIRQ(){
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Bit8u pic1_irq = 8;
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const Bit8u p = (slave.irr & slave.imrr)&slave.isrr;
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const Bit8u max = slave.special?8:slave.active_irq;
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for(Bit8u i = 0,s = 1;i < max;i++, s<<=1){
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if (p&s){
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pic1_irq = i;
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break;
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}
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}
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return true;
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// Maybe change the E_Exit to a return
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if (GCC_UNLIKELY(pic1_irq == 8)) E_Exit("irq 2 is active, but no irq active on the slave PIC.");
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slave.start_irq(pic1_irq);
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master.start_irq(2);
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CPU_HW_Interrupt(slave.vector_base + pic1_irq);
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}
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static void inline master_startIRQ(Bitu i){
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master.start_irq(i);
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CPU_HW_Interrupt(master.vector_base + i);
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}
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void PIC_runIRQs(void) {
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@ -297,70 +342,31 @@ void PIC_runIRQs(void) {
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if (GCC_UNLIKELY(!PIC_IRQCheck)) return;
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if (GCC_UNLIKELY(cpudecoder==CPU_Core_Normal_Trap_Run)) return;
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static Bitu IRQ_priority_order[16] =
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{ 0,1,2,8,9,10,11,12,13,14,15,3,4,5,6,7 };
|
||||
static Bit16u IRQ_priority_lookup[17] =
|
||||
{ 0,1,2,11,12,13,14,15,3,4,5,6,7,8,9,10,16 };
|
||||
Bit16u activeIRQ = PIC_IRQActive;
|
||||
if (activeIRQ == PIC_NOIRQ) activeIRQ = 16;
|
||||
/* Get the priority of the active irq */
|
||||
Bit16u Priority_Active_IRQ = IRQ_priority_lookup[activeIRQ];
|
||||
|
||||
Bitu i,j;
|
||||
/* j is the priority (walker)
|
||||
* i is the irq at the current priority */
|
||||
|
||||
/* If one of the pics is in special mode use a check that cares for that. */
|
||||
if(!PIC_Special_Mode) {
|
||||
for (j = 0; j < Priority_Active_IRQ; j++) {
|
||||
i = IRQ_priority_order[j];
|
||||
if (!irqs[i].masked && irqs[i].active) {
|
||||
if(GCC_LIKELY(PIC_startIRQ(i))) return;
|
||||
}
|
||||
}
|
||||
} else { /* Special mode variant */
|
||||
for (j = 0; j<= 15; j++) {
|
||||
i = IRQ_priority_order[j];
|
||||
if ( (j < Priority_Active_IRQ) || (pics[ ((i&8)>>3) ].special) ) {
|
||||
if (!irqs[i].masked && irqs[i].active) {
|
||||
/* the irq line is active. it's not masked and
|
||||
* the irq is allowed priority wise. So let's start it */
|
||||
/* If started successfully return, else go for the next */
|
||||
if(PIC_startIRQ(i)) return;
|
||||
}
|
||||
const Bit8u p = (master.irr & master.imrr)&master.isrr;
|
||||
const Bit8u max = master.special?8:master.active_irq;
|
||||
for(Bit8u i = 0,s = 1;i < max;i++, s<<=1){
|
||||
if (p&s){
|
||||
if (i==2) { //second pic
|
||||
slave_startIRQ();
|
||||
} else {
|
||||
master_startIRQ(i);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
//Disable check variable.
|
||||
PIC_IRQCheck = 0;
|
||||
}
|
||||
|
||||
void PIC_SetIRQMask(Bitu irq, bool masked) {
|
||||
if(irqs[irq].masked == masked) return; /* Do nothing if mask doesn't change */
|
||||
bool old_irq2_mask = irqs[2].masked;
|
||||
irqs[irq].masked=masked;
|
||||
if(irq < 8) {
|
||||
if (irqs[irq].active && !irqs[irq].masked) {
|
||||
PIC_IRQCheck|=(1 << (irq));
|
||||
} else {
|
||||
PIC_IRQCheck&=~(1 << (irq));
|
||||
}
|
||||
} else {
|
||||
if (irqs[irq].active && !irqs[irq].masked && !irqs[2].masked) {
|
||||
PIC_IRQCheck|=(1 << (irq));
|
||||
} else {
|
||||
PIC_IRQCheck&=~(1 << (irq));
|
||||
}
|
||||
}
|
||||
if(irqs[2].masked != old_irq2_mask) {
|
||||
/* Irq 2 mask has changed recheck second pic */
|
||||
for(Bitu i=8;i<=15;i++) {
|
||||
if (irqs[i].active && !irqs[i].masked && !irqs[2].masked) PIC_IRQCheck|=(1 << (i));
|
||||
else PIC_IRQCheck&=~(1 << (i));
|
||||
}
|
||||
}
|
||||
if (PIC_IRQCheck) {
|
||||
CPU_CycleLeft+=CPU_Cycles;
|
||||
CPU_Cycles=0;
|
||||
}
|
||||
Bitu t = irq>7 ? (irq - 8): irq;
|
||||
PIC_Controller * pic=&pics[irq>7 ? 1 : 0];
|
||||
//clear bit
|
||||
Bit8u bit = 1 <<(t);
|
||||
Bit8u newmask = pic->imr;
|
||||
newmask &= ~bit;
|
||||
if (masked) newmask |= bit;
|
||||
pic->set_imr(newmask);
|
||||
}
|
||||
|
||||
static void AddEntry(PICEntry * entry) {
|
||||
|
|
@ -463,7 +469,7 @@ void PIC_RemoveEvents(PIC_EventHandler handler) {
|
|||
|
||||
|
||||
bool PIC_RunQueue(void) {
|
||||
/* Check to see if a new milisecond needs to be started */
|
||||
/* Check to see if a new millisecond needs to be started */
|
||||
CPU_CycleLeft+=CPU_Cycles;
|
||||
CPU_Cycles=0;
|
||||
if (CPU_CycleLeft<=0) {
|
||||
|
|
@ -559,11 +565,9 @@ public:
|
|||
PIC_8259A(Section* configuration):Module_base(configuration){
|
||||
/* Setup pic0 and pic1 with initial values like DOS has normally */
|
||||
PIC_IRQCheck=0;
|
||||
PIC_IRQActive=PIC_NOIRQ;
|
||||
PIC_Ticks=0;
|
||||
Bitu i;
|
||||
for (i=0;i<2;i++) {
|
||||
pics[i].masked=0xff;
|
||||
pics[i].auto_eoi=false;
|
||||
pics[i].rotate_on_auto_eoi=false;
|
||||
pics[i].request_issr=false;
|
||||
|
|
@ -571,24 +575,21 @@ public:
|
|||
pics[i].single=false;
|
||||
pics[i].icw_index=0;
|
||||
pics[i].icw_words=0;
|
||||
pics[i].irr = pics[i].isr = pics[i].imrr = 0;
|
||||
pics[i].isrr = pics[i].imr = 0xff;
|
||||
pics[i].active_irq = 8;
|
||||
}
|
||||
for (i=0;i<=7;i++) {
|
||||
irqs[i].active=false;
|
||||
irqs[i].masked=true;
|
||||
irqs[i].inservice=false;
|
||||
irqs[i+8].active=false;
|
||||
irqs[i+8].masked=true;
|
||||
irqs[i+8].inservice=false;
|
||||
irqs[i].vector=0x8+i;
|
||||
irqs[i+8].vector=0x70+i;
|
||||
}
|
||||
irqs[0].masked=false; /* Enable system timer */
|
||||
irqs[1].masked=false; /* Enable Keyboard IRQ */
|
||||
irqs[2].masked=false; /* Enable second pic */
|
||||
irqs[8].masked=false; /* Enable RTC IRQ */
|
||||
master.vector_base = 0x08;
|
||||
slave.vector_base = 0x70;
|
||||
|
||||
PIC_SetIRQMask(0,false); /* Enable system timer */
|
||||
PIC_SetIRQMask(1,false); /* Enable system timer */
|
||||
PIC_SetIRQMask(2,false); /* Enable second pic */
|
||||
PIC_SetIRQMask(8,false); /* Enable RTC IRQ */
|
||||
|
||||
if (machine==MCH_PCJR) {
|
||||
/* Enable IRQ6 (replacement for the NMI for PCJr) */
|
||||
irqs[6].masked=false;
|
||||
PIC_SetIRQMask(6,false);
|
||||
}
|
||||
ReadHandler[0].Install(0x20,read_command,IO_MB);
|
||||
ReadHandler[1].Install(0x21,read_data,IO_MB);
|
||||
|
|
@ -606,6 +607,7 @@ public:
|
|||
pic_queue.free_entry=&pic_queue.entries[0];
|
||||
pic_queue.next_entry=0;
|
||||
}
|
||||
|
||||
~PIC_8259A(){
|
||||
}
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue