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Add correct 16bit BSWAP behavior in the interpreting cores

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3498
This commit is contained in:
Sjoerd van der Berg 2009-11-10 19:52:58 +00:00
parent db0aef34cf
commit 072ddbe083
6 changed files with 60 additions and 28 deletions
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8
src/cpu/core_full/op.h
View file

@ -584,9 +584,13 @@ switch (inst.code.op) {
SETFLAGBIT(CF,(inst_op1_d & (1 << (inst_op2_d & 31))));
inst_op1_d&=~(1 << (inst_op2_d & 31));
break;
case O_BSWAP:
case O_BSWAPw:
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegalopcode;
BSWAP(inst_op1_d);
BSWAPW(inst_op1_w);
break;
case O_BSWAPd:
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegalopcode;
BSWAPD(inst_op1_d);
break;
case O_CMPXCHG:
if (CPU_ArchitectureType<CPU_ARCHTYPE_486NEWSLOW) goto illegalopcode;

16
src/cpu/core_full/optable.h
View file

@ -321,10 +321,10 @@ static OpCode OpCodeTable[1024]={
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
/* 0x1c8 - 0x1cf */
{L_REGd ,O_BSWAP ,S_REGd ,REGI_AX},{L_REGd ,O_BSWAP ,S_REGd ,REGI_CX},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_DX},{L_REGd ,O_BSWAP ,S_REGd ,REGI_BX},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_SP},{L_REGd ,O_BSWAP ,S_REGd ,REGI_BP},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_SI},{L_REGd ,O_BSWAP ,S_REGd ,REGI_DI},
{L_REGw ,O_BSWAPw ,S_REGw ,REGI_AX},{L_REGw ,O_BSWAPw ,S_REGw ,REGI_CX},
{L_REGw ,O_BSWAPw ,S_REGw ,REGI_DX},{L_REGw ,O_BSWAPw ,S_REGw ,REGI_BX},
{L_REGw ,O_BSWAPw ,S_REGw ,REGI_SP},{L_REGw ,O_BSWAPw ,S_REGw ,REGI_BP},
{L_REGw ,O_BSWAPw ,S_REGw ,REGI_SI},{L_REGw ,O_BSWAPw ,S_REGw ,REGI_DI},
/* 0x1d0 - 0x1d7 */
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
@ -677,10 +677,10 @@ static OpCode OpCodeTable[1024]={
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
/* 0x3c8 - 0x3cf */
{L_REGd ,O_BSWAP ,S_REGd ,REGI_AX},{L_REGd ,O_BSWAP ,S_REGd ,REGI_CX},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_DX},{L_REGd ,O_BSWAP ,S_REGd ,REGI_BX},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_SP},{L_REGd ,O_BSWAP ,S_REGd ,REGI_BP},
{L_REGd ,O_BSWAP ,S_REGd ,REGI_SI},{L_REGd ,O_BSWAP ,S_REGd ,REGI_DI},
{L_REGd ,O_BSWAPd ,S_REGd ,REGI_AX},{L_REGd ,O_BSWAPd ,S_REGd ,REGI_CX},
{L_REGd ,O_BSWAPd ,S_REGd ,REGI_DX},{L_REGd ,O_BSWAPd ,S_REGd ,REGI_BX},
{L_REGd ,O_BSWAPd ,S_REGd ,REGI_SP},{L_REGd ,O_BSWAPd ,S_REGd ,REGI_BP},
{L_REGd ,O_BSWAPd ,S_REGd ,REGI_SI},{L_REGd ,O_BSWAPd ,S_REGd ,REGI_DI},
/* 0x3d0 - 0x3d7 */
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },

3
src/cpu/core_full/support.h
View file

@ -94,7 +94,8 @@ enum {
O_BTd,O_BTSd,O_BTRd,O_BTCd,
O_BSFw,O_BSRw,O_BSFd,O_BSRd,
O_BSWAP,O_CMPXCHG,
O_BSWAPw, O_BSWAPd,
O_CMPXCHG,
O_FPU

32
src/cpu/core_normal/prefix_0f.h
View file

@ -588,28 +588,28 @@
else {GetEAa;*rmrw=LoadMw(eaa);SaveMw(eaa,LoadMw(eaa)+oldrmrw);}
break;
}
CASE_0F_B(0xc8) /* BSWAP EAX */
CASE_0F_W(0xc8) /* BSWAP AX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_eax);break;
CASE_0F_B(0xc9) /* BSWAP ECX */
BSWAPW(reg_ax);break;
CASE_0F_W(0xc9) /* BSWAP CX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_ecx);break;
CASE_0F_B(0xca) /* BSWAP EDX */
BSWAPW(reg_cx);break;
CASE_0F_W(0xca) /* BSWAP DX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_edx);break;
CASE_0F_B(0xcb) /* BSWAP EBX */
BSWAPW(reg_dx);break;
CASE_0F_W(0xcb) /* BSWAP BX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_ebx);break;
CASE_0F_B(0xcc) /* BSWAP ESP */
BSWAPW(reg_bx);break;
CASE_0F_W(0xcc) /* BSWAP SP */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_esp);break;
CASE_0F_B(0xcd) /* BSWAP EBP */
BSWAPW(reg_sp);break;
CASE_0F_W(0xcd) /* BSWAP BP */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_ebp);break;
CASE_0F_B(0xce) /* BSWAP ESI */
BSWAPW(reg_bp);break;
CASE_0F_W(0xce) /* BSWAP SI */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_esi);break;
CASE_0F_B(0xcf) /* BSWAP EDI */
BSWAPW(reg_si);break;
CASE_0F_W(0xcf) /* BSWAP DI */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAP(reg_edi);break;
BSWAPW(reg_di);break;

24
src/cpu/core_normal/prefix_66_0f.h
View file

@ -439,3 +439,27 @@
else {GetEAa;*rmrd=LoadMd(eaa);SaveMd(eaa,LoadMd(eaa)+oldrmrd);}
break;
}
CASE_0F_D(0xc8) /* BSWAP EAX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_eax);break;
CASE_0F_D(0xc9) /* BSWAP ECX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_ecx);break;
CASE_0F_D(0xca) /* BSWAP EDX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_edx);break;
CASE_0F_D(0xcb) /* BSWAP EBX */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_ebx);break;
CASE_0F_D(0xcc) /* BSWAP ESP */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_esp);break;
CASE_0F_D(0xcd) /* BSWAP EBP */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_ebp);break;
CASE_0F_D(0xce) /* BSWAP ESI */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_esi);break;
CASE_0F_D(0xcf) /* BSWAP EDI */
if (CPU_ArchitectureType<CPU_ARCHTYPE_486OLDSLOW) goto illegal_opcode;
BSWAPD(reg_edi);break;

5
src/cpu/instructions.h
View file

@ -956,5 +956,8 @@
save(op1,lf_resd); \
lflags.type=t_DSHRd;
#define BSWAP(op1) \
#define BSWAPW(op1) \
op1 = 0;
#define BSWAPD(op1) \
op1 = (op1>>24)|((op1>>8)&0xFF00)|((op1<<8)&0xFF0000)|((op1<<24)&0xFF000000);