FPU Support
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@86
This commit is contained in:
Sjoerd van der Berg
parent
79182b385d
commit
153d381f5d
3 changed files with 205 additions and 5 deletions
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@ -16,10 +16,12 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "dosbox.h"
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#ifdef C_FPU
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#include <math.h>
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#include <float.h>
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#include "mem.h"
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#include "dosbox.h"
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#include "fpu.h"
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typedef PhysPt EAPoint;
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@ -36,13 +38,16 @@ typedef PhysPt EAPoint;
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#define SaveMw(off,val) mem_writew(off,val)
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#define SaveMd(off,val) mem_writed(off,val)
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typedef double Real;
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#include "fpu_types.h"
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#include "fpu_instructions.h"
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FPU_Flag_Info fpu_flags;
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FPU_Regs fpu_regs;
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FPU_Reg fpu_regs[8];
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#define FPU_GetZF fpu_flags.sw.zf = FPU_get_ZF();
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#include "fpu_core_16/instructions.h"
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#define FPU_ParseCW(newcw) { \
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fpu_flags.cw.ic = ((bool)((newcw&0x1000)>>12)?true:false); \
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fpu_flags.cw.rc = (Bit8u)((newcw&0x0C00)>>10); \
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@ -264,8 +269,9 @@ void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
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void FPU_ESC7_Normal(Bitu rm) {
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}
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void FPU_Init(void) {
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fpu_flags.type = t_FUNKNOWN;
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}
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#endif
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162
src/fpu/fpu_instructions.h
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162
src/fpu/fpu_instructions.h
Normal file
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@ -0,0 +1,162 @@
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/*
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* Copyright (C) 2002 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Library General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#define FLD(op1) { \
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FPU_GetZF; \
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fpu_flags.type=t_FLD; \
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if(--fpu_flags.sw.tos < 0) \
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fpu_flags.sw.tos = 7; \
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if( fpu_regs.st[fpu_flags.sw.tos].tag != FPUREG_EMPTY ) { \
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fpu_flags.result.tag = fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_NNAN; \
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break; \
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} \
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if(op1) \
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fpu_flags.result.tag = fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_VALID; \
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else \
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fpu_flags.result.tag = fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_ZERO; \
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fpu_flags.result.r = fpu_regs.st[fpu_flags.sw.tos].r = op1; \
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}
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#define FLDST(op1) { \
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FPU_GetZF; \
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fpu_flags.type=t_FLDST; \
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Bit8u reg = fpu_flags.sw.tos+op1; \
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if(reg>7) reg-=8; \
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if(--fpu_flags.sw.tos < 0) \
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fpu_flags.sw.tos = 7; \
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if(fpu_regs.st[fpu_flags.sw.tos].tag!=FPUREG_EMPTY) { \
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fpu_flags.result.tag = fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_NNAN; \
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break; \
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} \
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fpu_flags.result.tag = fpu_regs.st[fpu_flags.sw.tos].tag = fpu_regs.st[reg].tag; \
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fpu_flags.result.r = fpu_regs.st[fpu_flags.sw.tos].r = fpu_regs.st[reg].r; \
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}
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#define FPOP { \
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fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_EMPTY; \
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if(++fpu_flags.sw.tos > 7 ) \
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fpu_flags.sw.tos = 0; \
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}
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/* FPOP: fpu_flags.result.r = fpu_regs.st[fpu_flags.sw.tos].r = 0; is not really neccessary */
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#define FDIVP(op1,op2) { \
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Bit8u reg1 = fpu_flags.sw.tos+op1; \
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Bit8u reg2 = fpu_flags.sw.tos+op2; \
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fpu_flags.type=t_FDIVP; \
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if(reg1>7) reg1-=8; \
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if(reg2>7) reg2-=8; \
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if((fpu_regs.st[reg1].tag!=FPUREG_VALID && fpu_regs.st[reg1].tag!=FPUREG_ZERO)||(fpu_regs.st[reg2].tag!=FPUREG_VALID && fpu_regs.st[reg2].tag!=FPUREG_ZERO)) { \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_NNAN; \
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FPOP; \
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break; \
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} \
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if(fpu_regs.st[reg2].tag == FPUREG_ZERO) { \
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if(fpu_regs.st[reg1].r > 0) \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_PNAN; \
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else \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_NNAN; \
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FPOP; \
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break; \
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} \
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if(fpu_regs.st[reg1].tag == FPUREG_ZERO) { \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_ZERO; \
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FPOP; \
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break; \
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} \
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fpu_flags.result.tag = FPUREG_VALID; \
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fpu_flags.result.r = fpu_regs.st[reg1].r = fpu_regs.st[reg1].r / fpu_regs.st[reg2].r; \
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FPOP; \
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}
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#define FDIV(op1,op2) { \
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Bit8u reg1 = fpu_flags.sw.tos+op1; \
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Bit8u reg2 = fpu_flags.sw.tos+op2; \
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fpu_flags.type=t_FDIV; \
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if(reg1>7) reg1-=7; \
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if(reg2>7) reg2-=7; \
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if((fpu_regs.st[reg1].tag!=FPUREG_VALID && fpu_regs.st[reg1].tag!=FPUREG_ZERO)||(fpu_regs.st[reg2].tag!=FPUREG_VALID && fpu_regs.st[reg2].tag!=FPUREG_ZERO)) { \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_NNAN; \
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break; \
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} \
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if(fpu_regs.st[reg2].tag == FPUREG_ZERO) { \
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if(fpu_regs.st[reg1].r > 0) \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_PNAN; \
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else \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_NNAN; \
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break; \
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} \
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if(fpu_regs.st[reg1].tag == FPUREG_ZERO) { \
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fpu_flags.result.tag = fpu_regs.st[reg1].tag = FPUREG_ZERO; \
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break; \
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} \
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fpu_flags.result.tag = FPUREG_VALID; \
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fpu_flags.result.r = fpu_regs.st[reg1].r = fpu_regs.st[reg1].r / fpu_regs.st[reg2].r; \
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}
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#define FCHS { \
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FPU_GetZF; \
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fpu_flags.type=t_FCHS; \
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if(fpu_regs.st[fpu_flags.sw.tos].tag == FPUREG_PNAN) { \
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fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_NNAN; \
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} else if(fpu_regs.st[fpu_flags.sw.tos].tag == FPUREG_NNAN) { \
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fpu_regs.st[fpu_flags.sw.tos].tag = FPUREG_PNAN; \
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} else \
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fpu_regs.st[fpu_flags.sw.tos].r = -fpu_regs.st[fpu_flags.sw.tos].r; \
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}
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#define FCOMPP { \
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Bit8u reg = fpu_flags.sw.tos+1; \
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FPU_GetZF; \
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fpu_flags.type=t_FCOMP; \
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if(reg>7) \
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reg=0; \
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if((fpu_regs.st[reg].tag==FPUREG_VALID||fpu_regs.st[reg].tag==FPUREG_ZERO)&&(fpu_regs.st[fpu_flags.sw.tos].tag==FPUREG_VALID||fpu_regs.st[fpu_flags.sw.tos].tag==FPUREG_ZERO)) { \
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fpu_flags.result.r = fpu_regs.st[reg].r - fpu_regs.st[fpu_flags.sw.tos].r; \
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if(fpu_flags.result.r==0) \
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fpu_flags.result.tag = FPUREG_ZERO; \
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else \
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fpu_flags.result.tag = FPUREG_VALID; \
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FPOP; \
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FPOP; \
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return; \
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} else if(((fpu_regs.st[reg].tag==FPUREG_EMPTY)||(fpu_regs.st[fpu_flags.sw.tos].tag==FPUREG_EMPTY))||((fpu_regs.st[reg].tag==FPUREG_VALID||fpu_regs.st[reg].tag==FPUREG_ZERO)||(fpu_regs.st[fpu_flags.sw.tos].tag==FPUREG_VALID||fpu_regs.st[fpu_flags.sw.tos].tag==FPUREG_ZERO))) { \
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fpu_flags.result.tag = FPUREG_EMPTY; \
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FPOP; \
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FPOP; \
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return; \
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} \
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Bit8s res = (fpu_regs.st[reg].tag-fpu_regs.st[fpu_flags.sw.tos].tag); \
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if(res==0||fpu_flags.cw.ic==0) { \
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fpu_flags.result.tag = FPUREG_ZERO; \
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FPOP; \
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FPOP; \
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return; \
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} else if(res>0) { \
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fpu_flags.result.tag = FPUREG_NNAN; \
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FPOP; \
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FPOP; \
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return; \
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} \
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fpu_flags.result.tag = FPUREG_PNAN; \
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FPOP; \
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FPOP; \
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}
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32
src/fpu/fpu_types.h
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32
src/fpu/fpu_types.h
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@ -0,0 +1,32 @@
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enum { FPUREG_VALID=0, FPUREG_ZERO, FPUREG_PNAN, FPUREG_NNAN, FPUREG_EMPTY };
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enum {
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t_FLD=0, t_FLDST, t_FDIV,
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t_FDIVP, t_FCHS, t_FCOMP,
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t_FUNKNOWN,
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t_FNOTDONE,
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};
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struct FPU_Flag_Info {
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struct {
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Real r;
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Bit8u tag;
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} var1,var2, result;
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struct {
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bool bf,c3,c2,c1,c0,ir,sf,pf,uf,of,zf,df,in;
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Bit8s tos;
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} sw;
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struct {
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bool ic,ie,sf,pf,uf,of,zf,df,in;
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Bit8u rc,pc;
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} cw;
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Bitu type;
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Bitu prev_type;
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};
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struct FPU_Reg {
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Real r;
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Bit8u tag;
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};
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