From 1f5dac8c97d3e7e7ed9407d13dc2db3342a99495 Mon Sep 17 00:00:00 2001
From: Sjoerd van der Berg <harekiet@users.sourceforge.net>
Date: Fri, 25 Apr 2003 08:42:42 +0000
Subject: [PATCH] Added 32-bit ENTER and fixed 16-bit one Added 32-bit XLAT

Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@962
---
 src/cpu/core_full/load.h    | 71 +++++++++++++++++++++++++++++++++----
 src/cpu/core_full/optable.h |  7 ++--
 src/cpu/core_full/support.h |  2 +-
 3 files changed, 70 insertions(+), 10 deletions(-)

diff --git a/src/cpu/core_full/load.h b/src/cpu/core_full/load.h
index 8c9764f1..b6ba9938 100644
--- a/src/cpu/core_full/load.h
+++ b/src/cpu/core_full/load.h
@@ -317,10 +317,14 @@ l_M_Ed:
 	case D_SETALC:
 		reg_al = get_CF() ? 0xFF : 0;
 		goto nextopcode;
-	case D_XLAT:
+	case D_XLATw:
 		if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_bx+reg_al);
 		else reg_al=LoadMb(SegBase(ds)+reg_bx+reg_al);
 		goto nextopcode;
+	case D_XLATd:
+		if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_ebx+reg_al);
+		else reg_al=LoadMb(SegBase(ds)+reg_ebx+reg_al);
+		goto nextopcode;
 	case D_CBW:
 		reg_ax=(Bit8s)reg_al;
 		goto nextopcode;
@@ -371,11 +375,66 @@ l_M_Ed:
 		goto nextopcode;
 	case D_ENTERw:
 		{
-			Bit16u bytes=Fetchw();Bit8u level=Fetchb();
-			Push_16(reg_bp);reg_bp=reg_sp;reg_sp-=bytes;
-			EAPoint reader=SegBase(ss)+reg_bp;
-			for (Bit8u i=1;i<level;i++) {Push_16(LoadMw(reader));reader-=2;}
-			if (level) Push_16(reg_bp);
+			Bitu bytes=Fetchw();Bitu level=Fetchb() & 0x1f;
+			Bitu frame_ptr=reg_esp-2;
+			if (cpu.state & STATE_STACK32) {
+				reg_esp-=2;
+				mem_writew(SegBase(ss)+reg_esp,reg_bp);
+				for (Bitu i=1;i<level;i++) {	
+					reg_ebp-=2;reg_esp-=2;
+					mem_writew(SegBase(ss)+reg_esp,mem_readw(SegBase(ss)+reg_ebp));
+				}
+				if (level) {
+					reg_esp-=2;
+					mem_writew(SegBase(ss)+reg_esp,(Bit16u)frame_ptr);
+				}
+				reg_esp-=bytes;
+			} else {
+				reg_sp-=2;
+				mem_writew(SegBase(ss)+reg_sp,reg_bp);
+				for (Bitu i=1;i<level;i++) {	
+					reg_bp-=2;reg_sp-=2;
+					mem_writew(SegBase(ss)+reg_sp,mem_readw(SegBase(ss)+reg_bp));
+				}
+				if (level) {
+					reg_sp-=2;
+					mem_writew(SegBase(ss)+reg_sp,(Bit16u)frame_ptr);
+				}
+				reg_sp-=bytes;
+			}
+			reg_bp=frame_ptr;
+			goto nextopcode;
+		}
+	case D_ENTERd:
+		{
+			Bitu bytes=Fetchw();Bitu level=Fetchb() & 0x1f;
+			Bitu frame_ptr=reg_esp-4;
+			if (cpu.state & STATE_STACK32) {
+				reg_esp-=4;
+				mem_writed(SegBase(ss)+reg_esp,reg_ebp);
+				for (Bitu i=1;i<level;i++) {	
+					reg_ebp-=4;reg_esp-=4;
+					mem_writed(SegBase(ss)+reg_esp,mem_readd(SegBase(ss)+reg_ebp));
+				}
+				if (level) {
+					reg_esp-=4;
+					mem_writed(SegBase(ss)+reg_esp,(Bit32u)frame_ptr);
+				}
+				reg_esp-=bytes;
+			} else {
+				reg_sp-=4;
+				mem_writed(SegBase(ss)+reg_sp,reg_ebp);
+				for (Bitu i=1;i<level;i++) {	
+					reg_bp-=4;reg_sp-=4;
+					mem_writed(SegBase(ss)+reg_sp,mem_readd(SegBase(ss)+reg_bp));
+				}
+				if (level) {
+					reg_sp-=4;
+					mem_writed(SegBase(ss)+reg_sp,(Bit32u)frame_ptr);
+				}
+				reg_sp-=bytes;
+			}
+			reg_ebp=frame_ptr;
 			goto nextopcode;
 		}
 	case D_LEAVEw:
diff --git a/src/cpu/core_full/optable.h b/src/cpu/core_full/optable.h
index 72069f76..83bf1dcb 100644
--- a/src/cpu/core_full/optable.h
+++ b/src/cpu/core_full/optable.h
@@ -150,7 +150,7 @@ static OpCode OpCodeTable[1024]={
 {L_MODRM	,5			,0	,M_GRP_1	},{L_MODRM	,6			,0	,M_GRP_1	},
 {L_MODRM	,5			,0	,M_GRP_CL	},{L_MODRM	,6			,0	,M_GRP_CL	},
 {L_Ib		,O_AAM		,0		,0		},{L_Ib		,O_AAD		,0		,0		},
-{D_SETALC	,0			,0		,0		},{D_XLAT	,0			,0		,0		},
+{D_SETALC	,0			,0		,0		},{D_XLATw	,0			,0		,0		},
 //TODO FPU
 /* 0xd8 - 0xdf */
 {L_MODRM	,0			,0		,0		},{L_MODRM	,0			,0		,0		},
@@ -466,7 +466,8 @@ static OpCode OpCodeTable[1024]={
 {L_REGd		,O_XCHG_EAX	,S_REGd	,REGI_SI},{L_REGd	,O_XCHG_EAX	,S_REGd	,REGI_DI},
 /* 0x298 - 0x29f */
 {D_CWDE		,0			,0		,0		},{D_CDQ	,0			,0		,0		},
-{L_Ifd		,O_CALLFd	,0		,0		},{L_ERROR	,0			,0		,0		},
+//TODO Wait shoudn't be  nop
+{L_Ifd		,O_CALLFd	,0		,0		},{D_NOP	,0			,0		,0		},
 {L_FLG		,0			,S_PUSHd,0		},{L_POPd	,0			,S_FLGd	,0		},
 {L_REGb		,0			,S_FLGb	,REGI_AH},{L_FLG	,0			,S_REGb	,REGI_AH},
 
@@ -507,7 +508,7 @@ static OpCode OpCodeTable[1024]={
 {L_MODRM	,5			,0	,M_GRP_1	},{L_MODRM	,7			,0	,M_GRP_1	},
 {L_MODRM	,5			,0	,M_GRP_CL	},{L_MODRM	,7			,0	,M_GRP_CL	},
 {L_Ib		,O_AAM		,0		,0		},{L_Ib		,O_AAD		,0		,0		},
-{D_SETALC	,0			,0		,0		},{0		,0			,0		,0		},
+{D_SETALC	,0			,0		,0		},{D_XLATd	,0			,0		,0		},
 /* 0x2d8 - 0x2df */
 {L_MODRM	,0			,0		,0		},{L_MODRM	,0			,0		,0		},
 {L_MODRM	,0			,0		,0		},{L_MODRM	,0			,0		,0		},
diff --git a/src/cpu/core_full/support.h b/src/cpu/core_full/support.h
index 9460c6df..895cb90c 100644
--- a/src/cpu/core_full/support.h
+++ b/src/cpu/core_full/support.h
@@ -34,7 +34,7 @@ enum {
 	D_CBW,D_CWDE,
 	D_CWD,D_CDQ,
 	D_SETALC,
-	D_XLAT,
+	D_XLATw,D_XLATd,
 	D_CLI,D_STI,D_STC,D_CLC,D_CMC,D_CLD,D_STD,
 	D_NOP,
 	D_ENTERw,D_ENTERd,