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vga attrib register/blanking updates (hal); cleanup

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3436
This commit is contained in:
Sebastian Strohhäcker 2009-06-28 14:56:14 +00:00
parent eb9633a6e4
commit 26e4b50da0
4 changed files with 123 additions and 117 deletions
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32
src/hardware/vga_attr.cpp
View file

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* $Id: vga_attr.cpp,v 1.30 2009-05-27 09:15:41 qbix79 Exp $ */
/* $Id: vga_attr.cpp,v 1.31 2009-06-28 14:56:13 c2woody Exp $ */
#include "dosbox.h"
#include "inout.h"
@ -43,12 +43,14 @@ void VGA_ATTR_SetPalette(Bit8u index,Bit8u val) {
VGA_DAC_CombineColor(index,val);
}
Bitu read_p3c0(Bitu port,Bitu iolen) {
//Wcharts
return 0x0;
Bitu read_p3c0(Bitu /*port*/,Bitu /*iolen*/) {
// Wcharts, Win 3.11 & 95 SVGA
Bitu retval = attr(index) & 0x1f;
if (attr(enabled)) retval |= 0x20;
return retval;
}
void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
void write_p3c0(Bitu /*port*/,Bitu val,Bitu iolen) {
if (!vga.internal.attrindex) {
attr(index)=val & 0x1F;
vga.internal.attrindex=true;
@ -67,7 +69,7 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
if (!attr(enabled)) VGA_ATTR_SetPalette(attr(index),val);
if (!attr(enabled)) VGA_ATTR_SetPalette(attr(index),(Bit8u)val);
/*
0-5 Index into the 256 color DAC table. May be modified by 3C0h index
10h and 14h.
@ -77,7 +79,7 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
if (!IS_VGA_ARCH) val&=0x1f; // not really correct, but should do it
if ((attr(mode_control) ^ val) & 0x80) {
attr(mode_control)^=0x80;
for (Bitu i=0;i<0x10;i++) {
for (Bit8u i=0;i<0x10;i++) {
VGA_ATTR_SetPalette(i,vga.attr.palette[i]);
}
}
@ -85,11 +87,11 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
VGA_SetBlinking(val & 0x8);
}
if ((attr(mode_control) ^ val) & 0x04) {
attr(mode_control)=val;
attr(mode_control)=(Bit8u)val;
VGA_DetermineMode();
if ((IS_VGA_ARCH) && (svgaCard==SVGA_None)) VGA_StartResize();
} else {
attr(mode_control)=val;
attr(mode_control)=(Bit8u)val;
VGA_DetermineMode();
}
@ -111,12 +113,12 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
*/
break;
case 0x11: /* Overscan Color Register */
attr(overscan_color)=val;
attr(overscan_color)=(Bit8u)val;
/* 0-5 Color of screen border. Color is defined as in the palette registers. */
break;
case 0x12: /* Color Plane Enable Register */
/* Why disable colour planes? */
attr(color_plane_enable)=val;
attr(color_plane_enable)=(Bit8u)val;
/*
0 Bit plane 0 is enabled if set.
1 Bit plane 1 is enabled if set.
@ -133,7 +135,7 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
case M_TEXT:
if ((val==0x7) && (svgaCard==SVGA_None)) vga.config.pel_panning=7;
if (val>0x7) vga.config.pel_panning=0;
else vga.config.pel_panning=val+1;
else vga.config.pel_panning=(Bit8u)(val+1);
break;
case M_VGA:
case M_LIN8:
@ -163,8 +165,8 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
break;
}
if (attr(color_select) ^ val) {
attr(color_select)=val;
for (Bitu i=0;i<0x10;i++) {
attr(color_select)=(Bit8u)val;
for (Bit8u i=0;i<0x10;i++) {
VGA_ATTR_SetPalette(i,vga.attr.palette[i]);
}
}
@ -187,7 +189,7 @@ void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
}
}
Bitu read_p3c1(Bitu port,Bitu iolen) {
Bitu read_p3c1(Bitu /*port*/,Bitu iolen) {
// vga.internal.attrindex=false;
switch (attr(index)) {
/* Palette */

4
src/hardware/vga_draw.cpp
View file

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* $Id: vga_draw.cpp,v 1.107 2009-04-11 08:02:23 qbix79 Exp $ */
/* $Id: vga_draw.cpp,v 1.108 2009-06-28 14:56:14 c2woody Exp $ */
#include <string.h>
#include <math.h>
@ -616,7 +616,7 @@ static void VGA_ProcessSplit() {
}
static void VGA_DrawSingleLine(Bitu /*blah*/) {
if(vga.attr.enabled || (!(vga.mode==M_VGA || vga.mode==M_EGA))) {
if (vga.attr.enabled) {
Bit8u * data=VGA_DrawLine( vga.draw.address, vga.draw.address_line );
RENDER_DrawLine(data);
} else {

89
src/hardware/vga_other.cpp
View file

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* $Id: vga_other.cpp,v 1.25 2009-01-25 12:00:51 c2woody Exp $ */
/* $Id: vga_other.cpp,v 1.26 2009-06-28 14:56:14 c2woody Exp $ */
#include <string.h>
#include <math.h>
@ -28,57 +28,57 @@
#include "render.h"
#include "mapper.h"
static void write_crtc_index_other(Bitu port,Bitu val,Bitu iolen) {
vga.other.index=val;
static void write_crtc_index_other(Bitu /*port*/,Bitu val,Bitu /*iolen*/) {
vga.other.index=(Bit8u)val;
}
static Bitu read_crtc_index_other(Bitu port,Bitu iolen) {
static Bitu read_crtc_index_other(Bitu /*port*/,Bitu /*iolen*/) {
return vga.other.index;
}
static void write_crtc_data_other(Bitu port,Bitu val,Bitu iolen) {
static void write_crtc_data_other(Bitu /*port*/,Bitu val,Bitu /*iolen*/) {
switch (vga.other.index) {
case 0x00: //Horizontal total
if (vga.other.htotal ^ val) VGA_StartResize();
vga.other.htotal=val;
vga.other.htotal=(Bit8u)val;
break;
case 0x01: //Horizontal displayed chars
if (vga.other.hdend ^ val) VGA_StartResize();
vga.other.hdend=val;
vga.other.hdend=(Bit8u)val;
break;
case 0x02: //Horizontal sync position
vga.other.hsyncp=val;
vga.other.hsyncp=(Bit8u)val;
break;
case 0x03: //Horizontal and vertical sync width
vga.other.syncw=val;
vga.other.syncw=(Bit8u)val;
break;
case 0x04: //Vertical total
if (vga.other.vtotal ^ val) VGA_StartResize();
vga.other.vtotal=val;
vga.other.vtotal=(Bit8u)val;
break;
case 0x05: //Vertical display adjust
if (vga.other.vadjust ^ val) VGA_StartResize();
vga.other.vadjust=val;
vga.other.vadjust=(Bit8u)val;
break;
case 0x06: //Vertical rows
if (vga.other.vdend ^ val) VGA_StartResize();
vga.other.vdend=val;
vga.other.vdend=(Bit8u)val;
break;
case 0x07: //Vertical sync position
vga.other.vsyncp=val;
vga.other.vsyncp=(Bit8u)val;
break;
case 0x09: //Max scanline
if (vga.other.max_scanline ^ val) VGA_StartResize();
vga.other.max_scanline=val;
vga.other.max_scanline=(Bit8u)val;
break;
case 0x0A: /* Cursor Start Register */
vga.other.cursor_start = val & 0x3f;
vga.draw.cursor.sline = val&0x1f;
vga.other.cursor_start = (Bit8u)(val & 0x3f);
vga.draw.cursor.sline = (Bit8u)(val&0x1f);
vga.draw.cursor.enabled = ((val & 0x60) != 0x20);
break;
case 0x0B: /* Cursor End Register */
vga.other.cursor_end = val&0x1f;
vga.draw.cursor.eline = val&0x1f;
vga.other.cursor_end = (Bit8u)(val&0x1f);
vga.draw.cursor.eline = (Bit8u)(val&0x1f);
break;
case 0x0C: /* Start Address High Register */
vga.config.display_start=(vga.config.display_start & 0x00FF) | (val << 8);
@ -88,23 +88,23 @@ static void write_crtc_data_other(Bitu port,Bitu val,Bitu iolen) {
break;
case 0x0E: /*Cursor Location High Register */
vga.config.cursor_start&=0x00ff;
vga.config.cursor_start|=val << 8;
vga.config.cursor_start|=(Bit8u)(val << 8);
break;
case 0x0F: /* Cursor Location Low Register */
vga.config.cursor_start&=0xff00;
vga.config.cursor_start|=val;
vga.config.cursor_start|=(Bit8u)val;
break;
case 0x10: /* Light Pen High */
vga.other.lpen_high = val & 0x1f; //only 6 bits
vga.other.lpen_high = (Bit8u)(val & 0x1f); //only 6 bits
break;
case 0x11: /* Light Pen Low */
vga.other.lpen_low = val;
vga.other.lpen_low = (Bit8u)val;
break;
default:
LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:Write %X to illegal index %x",val,vga.other.index);
}
}
static Bitu read_crtc_data_other(Bitu port,Bitu iolen) {
static Bitu read_crtc_data_other(Bitu /*port*/,Bitu /*iolen*/) {
switch (vga.other.index) {
case 0x00: //Horizontal total
return vga.other.htotal;
@ -143,7 +143,7 @@ static Bitu read_crtc_data_other(Bitu port,Bitu iolen) {
default:
LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:Read from illegal index %x",vga.other.index);
}
return ~0;
return (Bitu)(~0);
}
static double hue_offset = 0.0;
@ -206,7 +206,7 @@ static void update_cga16_color(void) {
G = Y - 0.272*I - 0.647*Q; if (G < 0.0) G = 0.0; if (G > 1.0) G = 1.0;
B = Y - 1.105*I + 1.702*Q; if (B < 0.0) B = 0.0; if (B > 1.0) B = 1.0;
RENDER_SetPal(index,static_cast<Bit8u>(R*baseR),static_cast<Bit8u>(G*baseG),static_cast<Bit8u>(B*baseB));
RENDER_SetPal((Bit8u)index,static_cast<Bit8u>(R*baseR),static_cast<Bit8u>(G*baseG),static_cast<Bit8u>(B*baseB));
}
}
}
@ -303,7 +303,7 @@ static void TandyCheckLineMask(void ) {
vga.tandy.line_shift = 13;
vga.tandy.addr_mask = (1 << 13) - 1;
} else {
vga.tandy.addr_mask = ~0;
vga.tandy.addr_mask = (Bitu)(~0);
vga.tandy.line_shift = 0;
}
}
@ -352,10 +352,10 @@ static void write_tandy_reg(Bit8u val) {
}
}
static void write_cga(Bitu port,Bitu val,Bitu iolen) {
static void write_cga(Bitu port,Bitu val,Bitu /*iolen*/) {
switch (port) {
case 0x3d8:
vga.tandy.mode_control=val;
vga.tandy.mode_control=(Bit8u)val;
if (vga.tandy.mode_control & 0x2) {
if (vga.tandy.mode_control & 0x10) {
if (!(val & 0x4) && machine==MCH_CGA) {
@ -371,24 +371,24 @@ static void write_cga(Bitu port,Bitu val,Bitu iolen) {
VGA_SetBlinking(val & 0x20);
break;
case 0x3d9:
write_color_select(val);
write_color_select((Bit8u)val);
break;
}
}
static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
static void write_tandy(Bitu port,Bitu val,Bitu /*iolen*/) {
switch (port) {
case 0x3d8:
vga.tandy.mode_control=val;
vga.tandy.mode_control=(Bit8u)val;
TandyCheckLineMask();
VGA_SetBlinking(val & 0x20);
TANDY_FindMode();
break;
case 0x3d9:
write_color_select(val);
write_color_select((Bit8u)val);
break;
case 0x3da:
vga.tandy.reg_index=val;
vga.tandy.reg_index=(Bit8u)val;
break;
// case 0x3db: //Clear lightpen latch
break;
@ -397,10 +397,10 @@ static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
// case 0x3dd: //Extended ram page address register:
break;
case 0x3de:
write_tandy_reg(val);
write_tandy_reg((Bit8u)val);
break;
case 0x3df:
vga.tandy.line_mask = val >> 6;
vga.tandy.line_mask = (Bit8u)(val >> 6);
vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
vga.tandy.mem_bank = (val >> 3) & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
TandyCheckLineMask();
@ -409,18 +409,18 @@ static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
}
}
static void write_pcjr(Bitu port,Bitu val,Bitu iolen) {
static void write_pcjr(Bitu port,Bitu val,Bitu /*iolen*/) {
switch (port) {
case 0x3d9:
write_color_select(val);
write_color_select((Bit8u)val);
break;
case 0x3da:
if (vga.tandy.pcjr_flipflop) write_tandy_reg(val);
else vga.tandy.reg_index=val;
if (vga.tandy.pcjr_flipflop) write_tandy_reg((Bit8u)val);
else vga.tandy.reg_index=(Bit8u)val;
vga.tandy.pcjr_flipflop=!vga.tandy.pcjr_flipflop;
break;
case 0x3df:
vga.tandy.line_mask = val >> 6;
vga.tandy.line_mask = (Bit8u)(val >> 6);
vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
vga.tandy.mem_bank = (val >> 3) & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
vga.tandy.draw_base = &MemBase[vga.tandy.draw_bank * 16 * 1024];
@ -431,7 +431,7 @@ static void write_pcjr(Bitu port,Bitu val,Bitu iolen) {
}
}
static void write_hercules(Bitu port,Bitu val,Bitu iolen) {
static void write_hercules(Bitu port,Bitu val,Bitu /*iolen*/) {
switch (port) {
case 0x3b8: {
// the protected bits can always be cleared but only be set if the
@ -466,7 +466,7 @@ static void write_hercules(Bitu port,Bitu val,Bitu iolen) {
break;
}
case 0x3bf:
vga.herc.enable_bits=val;
vga.herc.enable_bits=(Bit8u)val;
break;
}
}
@ -476,7 +476,7 @@ static void write_hercules(Bitu port,Bitu val,Bitu iolen) {
return 0;
} */
Bitu read_herc_status(Bitu port,Bitu iolen) {
Bitu read_herc_status(Bitu /*port*/,Bitu /*iolen*/) {
// 3BAh (R): Status Register
// bit 0 Horizontal sync
// 1 Light pen status (only some cards)
@ -507,6 +507,8 @@ Bitu read_herc_status(Bitu port,Bitu iolen) {
void VGA_SetupOther(void) {
Bitu i;
memset( &vga.tandy, 0, sizeof( vga.tandy ));
vga.attr.enabled = true;
//Initialize values common for most machines, can be overwritten
vga.tandy.draw_base = vga.mem.linear;
vga.tandy.mem_base = vga.mem.linear;
@ -580,4 +582,3 @@ void VGA_SetupOther(void) {
}
}

115
src/ints/int10_modes.cpp
View file

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* $Id: int10_modes.cpp,v 1.85 2009-01-25 12:00:52 c2woody Exp $ */
/* $Id: int10_modes.cpp,v 1.86 2009-06-28 14:56:14 c2woody Exp $ */
#include <string.h>
@ -357,20 +357,19 @@ static bool SetCurMode(VideoModeBlock modeblock[],Bitu mode) {
static void FinishSetMode(bool clearmem) {
Bitu i;
/* Clear video memory if needs be */
if (clearmem) {
switch (CurMode->type) {
case M_CGA4:
case M_CGA2:
case M_TANDY16:
for (i=0;i<16*1024;i++) {
real_writew( 0xb800,i*2,0x0000);
for (Bit16u ct=0;ct<16*1024;ct++) {
real_writew( 0xb800,ct*2,0x0000);
}
break;
case M_TEXT: {
Bit16u seg = (CurMode->mode==7)?0xb000:0xb800;
for (i=0;i<16*1024;i++) real_writew(seg,i*2,0x0720);
for (Bit16u ct=0;ct<16*1024;ct++) real_writew(seg,ct*2,0x0720);
break;
}
case M_EGA:
@ -386,13 +385,13 @@ static void FinishSetMode(bool clearmem) {
}
}
/* Setup the BIOS */
if (CurMode->mode<128) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,CurMode->mode);
else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,CurMode->mode-0x98); //Looks like the s3 bios
real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,CurMode->twidth);
real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,CurMode->plength);
if (CurMode->mode<128) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)CurMode->mode);
else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)(CurMode->mode-0x98)); //Looks like the s3 bios
real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,(Bit16u)CurMode->twidth);
real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,(Bit16u)CurMode->plength);
real_writew(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,((CurMode->mode==7 )|| (CurMode->mode==0x0f)) ? 0x3b4 : 0x3d4);
real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,CurMode->theight-1);
real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,CurMode->cheight);
real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,(Bit8u)(CurMode->theight-1));
real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,(Bit16u)CurMode->cheight);
real_writeb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|(clearmem?0:0x80)));
real_writeb(BIOSMEM_SEG,BIOSMEM_SWITCHES,0x09);
real_writeb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL,real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x7f);
@ -402,11 +401,11 @@ static void FinishSetMode(bool clearmem) {
real_writed(BIOSMEM_SEG,BIOSMEM_VS_POINTER,int10.rom.video_save_pointers);
// Set cursor shape
if(CurMode->type==M_TEXT) {
if (CurMode->type==M_TEXT) {
INT10_SetCursorShape(0x06,07);
}
// Set cursor pos for page 0..7
for(i=0;i<8;i++) INT10_SetCursorPos(0,0,(Bit8u)i);
for (Bit8u ct=0;ct<8;ct++) INT10_SetCursorPos(0,0,ct);
// Set active page 0
INT10_SetActivePage(0);
/* Set some interrupt vectors */
@ -420,7 +419,6 @@ static void FinishSetMode(bool clearmem) {
}
bool INT10_SetVideoMode_OTHER(Bitu mode,bool clearmem) {
Bitu i;
switch (machine) {
case MCH_CGA:
if (mode>6) return false;
@ -479,9 +477,9 @@ bool INT10_SetVideoMode_OTHER(Bitu mode,bool clearmem) {
}
IO_WriteW(crtc_base,0x09 | (scanline-1) << 8);
//Setup the CGA palette using VGA DAC palette
for (i=0;i<16;i++) VGA_DAC_SetEntry(i,cga_palette[i][0],cga_palette[i][1],cga_palette[i][2]);
for (Bit8u ct=0;ct<16;ct++) VGA_DAC_SetEntry(ct,cga_palette[ct][0],cga_palette[ct][1],cga_palette[ct][2]);
//Setup the tandy palette
for (i=0;i<16;i++) VGA_DAC_CombineColor(i,i);
for (Bit8u ct=0;ct<16;ct++) VGA_DAC_CombineColor(ct,ct);
//Setup the special registers for each machine type
Bit8u mode_control_list[0xa+1]={
0x2c,0x28,0x2d,0x29, //0-3
@ -696,9 +694,9 @@ bool INT10_SetVideoMode(Bitu mode) {
seq_data[4]|=0xc; //Graphics - odd/even - Chained
break;
}
for (i=0;i<SEQ_REGS;i++) {
IO_Write(0x3c4,i);
IO_Write(0x3c5,seq_data[i]);
for (Bit8u ct=0;ct<SEQ_REGS;ct++) {
IO_Write(0x3c4,ct);
IO_Write(0x3c5,seq_data[ct]);
}
vga.config.compatible_chain4 = true; // this may be changed by SVGA chipset emulation
@ -707,19 +705,19 @@ bool INT10_SetVideoMode(Bitu mode) {
IO_Write(crtc_base,0x11);
IO_Write(crtc_base+1,IO_Read(crtc_base+1)&0x7f);
/* Clear all the regs */
for (i=0x0;i<=0x18;i++) {
IO_Write(crtc_base,i);IO_Write(crtc_base+1,0);
for (Bit8u ct=0x0;ct<=0x18;ct++) {
IO_Write(crtc_base,ct);IO_Write(crtc_base+1,0);
}
Bit8u overflow=0;Bit8u max_scanline=0;
Bit8u ver_overflow=0;Bit8u hor_overflow=0;
/* Horizontal Total */
IO_Write(crtc_base,0x00);IO_Write(crtc_base+1,CurMode->htotal-5);
IO_Write(crtc_base,0x00);IO_Write(crtc_base+1,(Bit8u)(CurMode->htotal-5));
hor_overflow|=((CurMode->htotal-5) & 0x100) >> 8;
/* Horizontal Display End */
IO_Write(crtc_base,0x01);IO_Write(crtc_base+1,CurMode->hdispend-1);
IO_Write(crtc_base,0x01);IO_Write(crtc_base+1,(Bit8u)(CurMode->hdispend-1));
hor_overflow|=((CurMode->hdispend-1) & 0x100) >> 7;
/* Start horizontal Blanking */
IO_Write(crtc_base,0x02);IO_Write(crtc_base+1,CurMode->hdispend);
IO_Write(crtc_base,0x02);IO_Write(crtc_base+1,(Bit8u)CurMode->hdispend);
hor_overflow|=((CurMode->hdispend) & 0x100) >> 6;
/* End horizontal Blanking */
Bitu blank_end=(CurMode->htotal-2) & 0x7f;
@ -730,7 +728,7 @@ bool INT10_SetVideoMode(Bitu mode) {
if ((CurMode->special & _EGA_HALF_CLOCK) && (CurMode->type!=M_CGA2)) ret_start = (CurMode->hdispend+3);
else if (CurMode->type==M_TEXT) ret_start = (CurMode->hdispend+5);
else ret_start = (CurMode->hdispend+4);
IO_Write(crtc_base,0x04);IO_Write(crtc_base+1,ret_start);
IO_Write(crtc_base,0x04);IO_Write(crtc_base+1,(Bit8u)ret_start);
hor_overflow|=(ret_start & 0x100) >> 4;
/* End Horizontal Retrace */
@ -742,10 +740,10 @@ bool INT10_SetVideoMode(Bitu mode) {
} else if (CurMode->type==M_TEXT) ret_end = (CurMode->htotal-3) & 0x1f;
else ret_end = (CurMode->htotal-4) & 0x1f;
IO_Write(crtc_base,0x05);IO_Write(crtc_base+1,ret_end | (blank_end & 0x20) << 2);
IO_Write(crtc_base,0x05);IO_Write(crtc_base+1,(Bit8u)(ret_end | (blank_end & 0x20) << 2));
/* Vertical Total */
IO_Write(crtc_base,0x06);IO_Write(crtc_base+1,(CurMode->vtotal-2));
IO_Write(crtc_base,0x06);IO_Write(crtc_base+1,(Bit8u)(CurMode->vtotal-2));
overflow|=((CurMode->vtotal-2) & 0x100) >> 8;
overflow|=((CurMode->vtotal-2) & 0x200) >> 4;
ver_overflow|=((CurMode->vtotal-2) & 0x400) >> 10;
@ -770,7 +768,7 @@ bool INT10_SetVideoMode(Bitu mode) {
}
/* Vertical Retrace Start */
IO_Write(crtc_base,0x10);IO_Write(crtc_base+1,vretrace);
IO_Write(crtc_base,0x10);IO_Write(crtc_base+1,(Bit8u)vretrace);
overflow|=(vretrace & 0x100) >> 6;
overflow|=(vretrace & 0x200) >> 2;
ver_overflow|=(vretrace & 0x400) >> 6;
@ -779,7 +777,7 @@ bool INT10_SetVideoMode(Bitu mode) {
IO_Write(crtc_base,0x11);IO_Write(crtc_base+1,(vretrace+2) & 0xF);
/* Vertical Display End */
IO_Write(crtc_base,0x12);IO_Write(crtc_base+1,(CurMode->vdispend-1));
IO_Write(crtc_base,0x12);IO_Write(crtc_base+1,(Bit8u)(CurMode->vdispend-1));
overflow|=((CurMode->vdispend-1) & 0x100) >> 7;
overflow|=((CurMode->vdispend-1) & 0x200) >> 3;
ver_overflow|=((CurMode->vdispend-1) & 0x400) >> 9;
@ -804,13 +802,13 @@ bool INT10_SetVideoMode(Bitu mode) {
}
/* Vertical Blank Start */
IO_Write(crtc_base,0x15);IO_Write(crtc_base+1,(CurMode->vdispend+vblank_trim));
IO_Write(crtc_base,0x15);IO_Write(crtc_base+1,(Bit8u)(CurMode->vdispend+vblank_trim));
overflow|=((CurMode->vdispend+vblank_trim) & 0x100) >> 5;
max_scanline|=((CurMode->vdispend+vblank_trim) & 0x200) >> 4;
ver_overflow|=((CurMode->vdispend+vblank_trim) & 0x400) >> 8;
/* Vertical Blank End */
IO_Write(crtc_base,0x16);IO_Write(crtc_base+1,(CurMode->vtotal-vblank_trim-2));
IO_Write(crtc_base,0x16);IO_Write(crtc_base+1,(Bit8u)(CurMode->vtotal-vblank_trim-2));
/* Line Compare */
Bitu line_compare=(CurMode->vtotal < 1024) ? 1023 : 2047;
@ -881,7 +879,7 @@ bool INT10_SetVideoMode(Bitu mode) {
/* Extended System Control 2 Register */
/* This register actually has more bits but only use the extended offset ones */
IO_Write(crtc_base,0x51);
IO_Write(crtc_base + 1,(offset & 0x300) >> 4);
IO_Write(crtc_base + 1,(Bit8u)((offset & 0x300) >> 4));
/* Clear remaining bits of the display start */
IO_Write(crtc_base,0x69);
IO_Write(crtc_base + 1,0);
@ -995,9 +993,9 @@ bool INT10_SetVideoMode(Bitu mode) {
}
break;
}
for (i=0;i<GFX_REGS;i++) {
IO_Write(0x3ce,i);
IO_Write(0x3cf,gfx_data[i]);
for (Bit8u ct=0;ct<GFX_REGS;ct++) {
IO_Write(0x3ce,ct);
IO_Write(0x3cf,gfx_data[ct]);
}
Bit8u att_data[ATT_REGS];
memset(att_data,0,ATT_REGS);
@ -1025,16 +1023,16 @@ bool INT10_SetVideoMode(Bitu mode) {
default:
if ( CurMode->type == M_LIN4 )
goto att_text16;
for (i=0;i<8;i++) {
att_data[i]=i;
att_data[i+8]=i+0x10;
for (Bit8u ct=0;ct<8;ct++) {
att_data[ct]=ct;
att_data[ct+8]=ct+0x10;
}
break;
}
break;
case M_TANDY16:
att_data[0x10]=0x01; //Color Graphics
for (i=0;i<16;i++) att_data[i]=i;
for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
break;
case M_TEXT:
if (machine==MCH_EGA) {
@ -1054,9 +1052,9 @@ att_text16:
att_data[i+8]=0x18;
}
} else {
for (i=0;i<8;i++) {
att_data[i]=i;
att_data[i+8]=i+0x38;
for (Bit8u ct=0;ct<8;ct++) {
att_data[ct]=ct;
att_data[ct+8]=ct+0x38;
}
if (IS_VGA_ARCH) att_data[0x06]=0x14; //Odd Color 6 yellow/brown.
}
@ -1078,8 +1076,8 @@ att_text16:
att_data[5]=0x04;
att_data[6]=0x06;
att_data[7]=0x07;
for (i=0x8;i<0x10;i++)
att_data[i] = i + 0x8;
for (Bit8u ct=0x8;ct<0x10;ct++)
att_data[ct] = ct + 0x8;
real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
break;
case M_VGA:
@ -1087,15 +1085,15 @@ att_text16:
case M_LIN15:
case M_LIN16:
case M_LIN32:
for (i=0;i<16;i++) att_data[i]=i;
for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
att_data[0x10]=0x41; //Color Graphics 8-bit
break;
}
IO_Read(mono_mode ? 0x3ba : 0x3da);
if ((modeset_ctl & 8)==0) {
for (i=0;i<ATT_REGS;i++) {
IO_Write(0x3c0,i);
IO_Write(0x3c0,att_data[i]);
for (Bit8u ct=0;ct<ATT_REGS;ct++) {
IO_Write(0x3c0,ct);
IO_Write(0x3c0,att_data[ct]);
}
vga.config.pel_panning = 0;
IO_Write(0x3c0,0x20); IO_Write(0x3c0,0x00); //Disable palette access
@ -1173,10 +1171,10 @@ dac_text16:
}
}
} else {
for (i=0x10;i<ATT_REGS;i++) {
if (i==0x11) continue; // skip overscan register
IO_Write(0x3c0,i);
IO_Write(0x3c0,att_data[i]);
for (Bit8u ct=0x10;ct<ATT_REGS;ct++) {
if (ct==0x11) continue; // skip overscan register
IO_Write(0x3c0,ct);
IO_Write(0x3c0,att_data[ct]);
}
vga.config.pel_panning = 0;
IO_Write(0x3c0,0x20); //Disable palette access
@ -1222,11 +1220,11 @@ dac_text16:
IO_Write(crtc_base+1,0);
/* Setup the linear frame buffer */
IO_Write(crtc_base,0x59);
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
IO_Write(crtc_base+1,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
IO_Write(crtc_base,0x5a);
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 16));
IO_Write(crtc_base+1,(Bit8u)((S3_LFB_BASE >> 16)&0xff));
IO_Write(crtc_base,0x6b); // BIOS scratchpad
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
IO_Write(crtc_base+1,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
/* Setup some remaining S3 registers */
IO_Write(crtc_base,0x41); // BIOS scratchpad
@ -1255,7 +1253,7 @@ dac_text16:
}
IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1,reg_50);
Bitu reg_31, reg_3a;
Bit8u reg_31, reg_3a;
switch (CurMode->type) {
case M_LIN15:
case M_LIN16:
@ -1303,6 +1301,11 @@ dac_text16:
}
FinishSetMode(clearmem);
/* Set vga attrib register into defined state */
IO_Read(mono_mode ? 0x3ba : 0x3da);
IO_Write(0x3c0,0x20);
/* Load text mode font */
if (CurMode->type==M_TEXT) {
if (IS_VGA_ARCH) INT10_LoadFont(Real2Phys(int10.rom.font_16),true,256,0,0,16);