diff --git a/src/cpu/core_normal/prefix_0f.h b/src/cpu/core_normal/prefix_0f.h
index 44bb1b24..09122714 100644
--- a/src/cpu/core_normal/prefix_0f.h
+++ b/src/cpu/core_normal/prefix_0f.h
@@ -121,10 +121,8 @@
 			*rmrw=(Bit16u)limit;
 		}
 		break;
-#if !(C_DEBUG)
 	CASE_0F_B(0x06)												/* CLTS */
 		break;
-#endif
 	CASE_0F_B(0x20)												/* MOV Rd.CRx */
 		{
 			GetRM;
@@ -298,7 +296,6 @@
 		break;
 	CASE_0F_W(0xb2)												/* LSS Ew */
 		{	
-			CPU_Cycles++;
 			GetRMrw;GetEAa;
 			LOADSEG(ss,LoadMw(eaa+2));
 			*rmrw=LoadMw(eaa);
diff --git a/src/cpu/core_normal/prefix_66_0f.h b/src/cpu/core_normal/prefix_66_0f.h
index 65a10402..d23ab4cc 100644
--- a/src/cpu/core_normal/prefix_66_0f.h
+++ b/src/cpu/core_normal/prefix_66_0f.h
@@ -216,7 +216,6 @@
 		{	
 			GetRMrd;GetEAa;
 			LOADSEG(ss,LoadMw(eaa+4));
-			CPU_Cycles++;
 			*rmrd=LoadMd(eaa);
 			break;
 		}
diff --git a/src/cpu/core_normal/prefix_none.h b/src/cpu/core_normal/prefix_none.h
index 99df7d44..a819fbda 100644
--- a/src/cpu/core_normal/prefix_none.h
+++ b/src/cpu/core_normal/prefix_none.h
@@ -190,7 +190,6 @@
 	CASE_W(0x53)												/* PUSH BX */
 		Push_16(reg_bx);break;
 	CASE_W(0x54)												/* PUSH SP */
-//TODO Check if this is correct i think it's SP+2 or something
 		Push_16(reg_sp);break;
 	CASE_W(0x55)												/* PUSH BP */
 		Push_16(reg_bp);break;