fpu updated
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1028
This commit is contained in:
Peter Veenstra
parent
57e3c31efb
commit
3a059c870b
3 changed files with 351 additions and 9 deletions
274
src/fpu/fpu.cpp
274
src/fpu/fpu.cpp
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@ -23,6 +23,7 @@
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#include <float.h>
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#include "mem.h"
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#include "fpu.h"
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#include "cpu.h"
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typedef PhysPt EAPoint;
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@ -37,8 +38,8 @@ typedef PhysPt EAPoint;
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#include "fpu_types.h"
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struct {
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FPU_Reg regs[8];
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FPU_Tag tags[8];
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FPU_Reg regs[9];
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FPU_Tag tags[9];
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Bitu cw;
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FPU_Round round;
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Bitu ex_mask;
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@ -52,33 +53,189 @@ INLINE void FPU_SetCW(Bitu word) {
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fpu.round = (FPU_Round)((word >> 8) & 3);
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fpu.ex_mask = word & 0x3f;
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}
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INLINE Bitu FPU_GET_TOP(void){
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return (fpu.sw & 0x3800)>>11;
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}
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INLINE void FPU_SET_TOP(Bitu val){
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fpu.sw &= ~0x3800;
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fpu.sw |= (val&7)<<11;
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return;
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}
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#include "fpu_instructions.h"
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/* TODO : MAKE REGULAR TREE A DEFINE or a function
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: ESC6normal => esc4normal+pop or a define as well
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: Make a smarter top system. won't matter that much in speed though.
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: #define ST fpu.top #define ST(i) (fpu.top+(i))&7 maybe*/
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static void EATREE(Bitu _rm){
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Bitu group=(_rm >> 3) & 7;
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Bitu top = FPU_GET_TOP();
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/* data will allready be put in register 8 by caller */
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switch(group){
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case 0x00: /* FIADD */
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FPU_FADD(top, 8);
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break;
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case 0x01: /* FIMUL */
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FPU_FMUL(top, 8);
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break;
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case 0x02: /* FICOM */
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case 0x03: /* FICOMP */
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LOG(LOG_FPU,LOG_WARN)("ESC EATREE:Unhandled group %d",group);
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break;
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case 0x04: /* FISUB */
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FPU_FSUB(top,8);
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break;
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case 0x05: /* FISUBR */
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FPU_FSUBR(top,8);
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case 0x06: /* FIDIV */
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FPU_FDIV(top, 8);
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break;
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case 0x07: /* FIDIVR */
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FPU_FDIVR(top,8);
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break;
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default:
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break;
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}
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}
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void FPU_ESC0_EA(Bitu rm,PhysPt addr) {
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/* REGULAR TREE WITH 32 BITS REALS ? float ? */
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//THIS SHOULD GO ALLRIGHT !?!
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LOG(LOG_FPU, LOG_WARN)("ESC 0 EA used (check the result!)");
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union {
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float f;
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Bit32s l;
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} blah;
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blah.l = mem_readd(addr);
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fpu.regs[8].d = static_cast<double>(blah.f);
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EATREE(rm);
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}
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void FPU_ESC0_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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LOG(LOG_FPU,LOG_WARN)("ESC 0:Unhandled group %d subfunction %d",group,sub);
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Bitu top = FPU_GET_TOP();
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switch (group){
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case 0x00: /* FADD ST,STi */
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FPU_FADD(top,(top+sub)&7);
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break;
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case 0x01: /* FMUL ST,STi */
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FPU_FMUL(top,(top+sub)&7);
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break;
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case 0x02: /* FCOM STi */
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case 0x03: /* FCOMP STi */
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LOG(LOG_FPU,LOG_WARN)("ESC 0:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x04: /* FSUB ST,STi */
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FPU_FSUB(top,(top+sub)&7);
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break;
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case 0x05: /* FSUBR ST,STi */
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FPU_FSUBR(top,(top+sub)&7);
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break;
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case 0x06: /* FDIV ST,STi */
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FPU_FDIV(top,(top+sub)&7);
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break;
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case 0x07: /* FDIVR ST,STi */
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FPU_FDIVR(top,(top+sub)&7);
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break;
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default:
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break;
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}
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}
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void FPU_ESC1_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
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}
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void FPU_ESC1_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %d subfunction %d",group,sub);
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switch (group){
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case 0x00: /* FLD STi */
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{
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Bitu top = FPU_GET_TOP();
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FPU_PUSH(fpu.regs[(top+sub)&7].d);
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}
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break;
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case 0x04:
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switch(sub){
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case 0x00: /* FCHS */
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case 0x01: /* FABS */
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case 0x02: /* UNKNOWN */
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case 0x03: /* ILLEGAL */
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case 0x04: /* FTST */
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case 0x05: /* FXAM */
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case 0x06: /* FTSTP (cyrix)*/
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case 0x07: /* UNKNOWN */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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case 0x05:
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switch(sub){
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case 0x00: /* FLD1 */
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FPU_PUSH(1.0);
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break;
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case 0x01: /* FLDL2T */
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case 0x02: /* FLDL2E */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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case 0x03: /* FLDPI */
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FPU_PUSH(PI);
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break;
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case 0x04: /* FLDLG2 */
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case 0x05: /* FLDLN2 */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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case 0x06: /* FLDZ*/
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FPU_PUSH_ZERO();
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break;
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case 0x07: /* ILLEGAL */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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case 0x06:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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case 0x07:
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switch(sub){
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case 0x03: /* FSINCOS */
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FPU_FSINCOS();
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break;
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case 0x06: /* FSIN */
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FPU_FSIN();
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break;
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case 0x07: /* FCOS */
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FPU_FCOS();
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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}
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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}
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// LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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}
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void FPU_ESC2_EA(Bitu rm,PhysPt addr) {
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/* 32 bits integer operants */
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Bit32s blah = mem_readd(addr);
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fpu.regs[8].d = static_cast<double>(blah);
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EATREE(rm);
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}
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void FPU_ESC2_Normal(Bitu rm) {
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@ -125,16 +282,52 @@ void FPU_ESC3_Normal(Bitu rm) {
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void FPU_ESC4_EA(Bitu rm,PhysPt addr) {
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/* REGULAR TREE WITH 64 BITS REALS ? double ? */
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E_Exit("how to load a double in esc 4 ea");
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//SEE ESC 0 EA
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// double blah = mem_readd(addr); //wrong wrong wrong
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// fpu.regs[8].d = static_cast<double>(blah);
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EATREE(rm);
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}
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void FPU_ESC4_Normal(Bitu rm) {
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//LOOKS LIKE number 6 without popping*/
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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LOG(LOG_FPU,LOG_WARN)("ESC 4:Unhandled group %d subfunction %d",group,sub);
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Bitu top = FPU_GET_TOP();
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switch(group){
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case 0x00: /*FADDP STi,ST*/
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FPU_FADD((top+sub)&7,top);
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break;
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case 0x01: /* FMULP STi,ST*/
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FPU_FMUL((top+sub)&7,top);
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break;
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case 0x02: /* FCOMP5*/
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case 0x03: /* weird*/
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LOG(LOG_FPU,LOG_WARN)("ESC 6:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x04: /* FSUBRP STi,ST*/
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FPU_FSUBR((top+sub)&7,top);
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break;
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case 0x05: /* FSUBP STi,ST*/
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FPU_FSUB((top+sub)&7,top);
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break;
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case 0x06: /* FDIVRP STi,ST*/
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FPU_FDIVR((top+sub)&7,top);
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break;
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case 0x07: /* FDIVP STi,ST*/
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FPU_FDIV((top+sub)&7,top);
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break;
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default:
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break;
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}
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}
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void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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LOG(LOG_FPU,LOG_WARN)("ESC EA 5:Unhandled group %d subfunction %d",group,sub);
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}
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void FPU_ESC5_Normal(Bitu rm) {
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@ -145,20 +338,85 @@ void FPU_ESC5_Normal(Bitu rm) {
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void FPU_ESC6_EA(Bitu rm,PhysPt addr) {
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/* 16 bit (word integer) operants */
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Bit16s blah = mem_readw(addr);
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fpu.regs[8].d = static_cast<double>(blah);
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EATREE(rm);
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}
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void FPU_ESC6_Normal(Bitu rm) {
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/* all P variants working only on registers */
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/* get top before switch and pop afterwards */
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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Bitu top = FPU_GET_TOP();
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switch(group){
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case 0x00: /*FADDP STi,ST*/
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FPU_FADD((top+sub)&7,top);
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break;
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case 0x01: /* FMULP STi,ST*/
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FPU_FMUL((top+sub)&7,top);
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break;
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case 0x02: /* FCOMP5*/
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case 0x03: /* weird*/
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LOG(LOG_FPU,LOG_WARN)("ESC 6:Unhandled group %d subfunction %d",group,sub);
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// maybe return and don't pop
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break;
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case 0x04: /* FSUBRP STi,ST*/
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FPU_FSUBR((top+sub)&7,top);
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break;
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case 0x05: /* FSUBP STi,ST*/
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FPU_FSUB((top+sub)&7,top);
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break;
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case 0x06: /* FDIVRP STi,ST*/
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FPU_FDIVR((top+sub)&7,top);
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break;
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case 0x07: /* FDIVP STi,ST*/
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FPU_FDIV((top+sub)&7,top);
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break;
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default:
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break;
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}
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FPU_FPOP();
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}
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void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x03: /*FISTP */
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{ Bitu top = FPU_GET_TOP();
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mem_writew(addr,static_cast<Bit16s>(fpu.regs[top].d));
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FPU_FPOP();
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}
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
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}
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}
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void FPU_ESC7_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch (group){
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case 0x04:
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switch(sub){
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case 0x00: /* FNSTSW AX*/
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reg_ax = fpu.sw;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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LOG(LOG_FPU,LOG_WARN)("ESC 7:Unhandled group %d subfunction %d",group,sub);
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}
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void FPU_Init(void) {
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void FPU_Init(Section*) {
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FPU_FINIT();
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}
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@ -35,4 +35,86 @@ static void FPU_FCLEX(void){
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static void FPU_FNOP(void){
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return;
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}
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static void FPU_PUSH(double in){
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Bitu newtop = (FPU_GET_TOP() - 1) &7;
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FPU_SET_TOP(newtop);
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//actually check if empty
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fpu.tags[newtop]=TAG_Valid;
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fpu.regs[newtop].d=in;
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return;
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}
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static void FPU_PUSH_ZERO(void){
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Bitu newtop = (FPU_GET_TOP() - 1) &7;
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FPU_SET_TOP(newtop);
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//actually check if empty
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fpu.tags[newtop]=TAG_Zero;
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fpu.regs[newtop].d=0.0;
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return;
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}
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static void FPU_FPOP(void){
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Bitu top = FPU_GET_TOP();
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fpu.tags[top]=TAG_Empty;
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//maybe set zero in it as well
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FPU_SET_TOP((top+1)&7);
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return;
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}
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static void FPU_FADD(Bitu op1, Bitu op2){
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fpu.regs[op1].d+=fpu.regs[op2].d;
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//flags and such :)
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return;
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}
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static void FPU_FSIN(void){
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Bitu top = FPU_GET_TOP();
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fpu.regs[top].d = sin(fpu.regs[top].d);
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//flags and such :)
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return;
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}
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static void FPU_FSINCOS(void){
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Bitu top = FPU_GET_TOP();
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fpu.regs[top].d = sin(fpu.regs[top].d);
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FPU_PUSH(cos(fpu.regs[top].d));
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//flags and such :)
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return;
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}
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static void FPU_FCOS(void){
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Bitu top = FPU_GET_TOP();
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fpu.regs[top].d = cos(fpu.regs[top].d);
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//flags and such :)
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return;
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}
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static void FPU_FDIV(Bitu st, Bitu other){
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fpu.regs[st].d= fpu.regs[st].d/fpu.regs[other].d;
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//flags and such :)
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return;
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}
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static void FPU_FDIVR(Bitu st, Bitu other){
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fpu.regs[st].d= fpu.regs[other].d/fpu.regs[st].d;
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// flags and such :)
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return;
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};
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static void FPU_FMUL(Bitu st, Bitu other){
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fpu.regs[st].d*=fpu.regs[other].d;
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//flags and such :)
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return;
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}
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static void FPU_FSUB(Bitu st, Bitu other){
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fpu.regs[st].d = fpu.regs[st].d - fpu.regs[other].d;
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//flags and such :)
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return;
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}
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static void FPU_FSUBR(Bitu st, Bitu other){
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fpu.regs[st].d= fpu.regs[other].d - fpu.regs[st].d;
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//flags and such :)
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return;
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}
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@ -36,4 +36,6 @@ enum FPU_Round {
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ROUND_Down = 1,
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ROUND_Up = 2,
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ROUND_Chop = 3
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};
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};
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//get pi from a real library
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#define PI 3.1415926535
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