First CVS upload.
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@80
This commit is contained in:
Sjoerd van der Berg
parent
7d1ca9bdd4
commit
42e5d0b779
158 changed files with 42940 additions and 0 deletions
369
src/hardware/pic.cpp
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369
src/hardware/pic.cpp
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/*
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* Copyright (C) 2002 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Library General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "dosbox.h"
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#include "inout.h"
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#include "cpu.h"
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#include "pic.h"
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struct IRQ_Block {
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bool masked;
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bool active;
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bool inservice;
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Bit8u vector;
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char * name;
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PIC_EOIHandler * handler;
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};
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Bit32u PIC_IRQCheck;
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static IRQ_Block irqs[16];
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static Bit8u pic0_icws=0;
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static Bit8u pic1_icws=0;
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static Bit8u pic0_icw_state=0;
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static Bit8u pic1_icw_state=0;
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static bool pic0_request_iisr=0;
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static bool pic1_request_iisr=0;
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//TODO Special mask mode in ocw3
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//TODO maybe check for illegal modes that don't work on pc too and exit the emu
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//Pic 0 command port
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static void write_p20(Bit32u port,Bit8u val) {
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Bit32u i;
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switch (val) {
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case 0x0A: /* select read interrupt request register */
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pic0_request_iisr=false;
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break;
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case 0x0B: /* select read interrupt in-service register */
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pic0_request_iisr=true;
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break;
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case 0x10: /* ICW1 */
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pic0_icws=2;
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pic0_icw_state=1;
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break;
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case 0x11: /* ICW1 + need for ICW4 */
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pic0_icws=3;
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pic0_icw_state=1;
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break;
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case 0x20: /* end of interrupt command */
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/* clear highest current in service bit */
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for (i=0;i<=7;i++) {
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if (irqs[i].inservice) {
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irqs[i].inservice=false;
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if (irqs[i].handler!=0) irqs[i].handler();
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break;
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};
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};
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break;
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case 0x60: /* specific EOI 0 */
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case 0x61: /* specific EOI 1 */
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case 0x62: /* specific EOI 2 */
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case 0x63: /* specific EOI 3 */
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case 0x64: /* specific EOI 4 */
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case 0x65: /* specific EOI 5 */
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case 0x66: /* specific EOI 6 */
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case 0x67: /* specific EOI 7 */
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if (irqs[val-0x60].inservice) {
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irqs[val-0x60].inservice=false;
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if (irqs[val-0x60].handler!=0) irqs[val-0x60].handler();
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};
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break;
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// IRQ lowest priority commands
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case 0xC0: // 0 7 6 5 4 3 2 1
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case 0xC1: // 1 0 7 6 5 4 3 2
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case 0xC2: // 2 1 0 7 6 5 4 3
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case 0xC3: // 3 2 1 0 7 6 5 4
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case 0xC4: // 4 3 2 1 0 7 6 5
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case 0xC5: // 5 4 3 2 1 0 7 6
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case 0xC6: // 6 5 4 3 2 1 0 7
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case 0xC7: // 7 6 5 4 3 2 1 0
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// ignore for now TODO
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break;
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default:
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E_Exit("PIC0:Unhandled command %02X",val);
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}
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}
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//Pic 0 Interrupt mask
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static void write_p21(Bit32u port,Bit8u val) {
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Bit8u i;
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switch(pic0_icw_state) {
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case 0: /* mask register */
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for (i=0;i<=7;i++) {
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irqs[i].masked=(val&(1<<i))>0;
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if (irqs[i].active && !irqs[i].masked) PIC_IRQCheck|=(1 << 1);
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else PIC_IRQCheck&=~(1 << i);
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};
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break;
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case 1: /* icw2 */
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for (i=0;i<=7;i++) {
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irqs[i].vector=(val&0xf8)+i;
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};
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default: /* icw2, 3, and 4*/
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if(pic0_icw_state++ >= pic0_icws) pic0_icw_state=0;
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}
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}
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static Bit8u read_p20(Bit32u port) {
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Bit8u ret=0;
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Bit32u i;
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Bit8u b=1;
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if (pic0_request_iisr) {
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for (i=0;i<=7;i++) {
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if (irqs[i].inservice) ret|=b;
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b <<= 1;
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}
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} else {
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for (i=0;i<=7;i++) {
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if (irqs[i].active) ret|=b;
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b <<= 1;
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}
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};
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return ret;
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}
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static Bit8u read_p21(Bit32u port) {
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Bit8u ret=0;
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Bit32u i;
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Bit8u b=1;
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for (i=0;i<=7;i++) {
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if (irqs[i].masked) ret|=b;
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b <<= 1;
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}
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return ret;
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}
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static void write_pa0(Bit32u port,Bit8u val) {
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Bit32u i;
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switch (val) {
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case 0x0A: /* select read interrupt request register */
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pic1_request_iisr=false;
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break;
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case 0x0B: /* select read interrupt in-service register */
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pic1_request_iisr=true;
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break;
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case 0x10: /* ICW1 */
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/* Clear everything set full mask and clear all inservice */
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for (i=0;i<=7;i++) {
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irqs[i].masked=true;
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irqs[i].active=false;
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irqs[i].inservice=false;
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}
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pic1_icws=2;
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pic1_icw_state=1;
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break;
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case 0x11: /* ICW1 + need for ICW4 */
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pic1_icws=3;
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pic1_icw_state=1;
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break;
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case 0x20: /* end of interrupt command */
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/* clear highest current in service bit */
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for (i=8;i<=15;i++) {
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if (irqs[i].inservice) {
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irqs[i].inservice=false;
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if (irqs[i].handler!=0) irqs[i].handler();
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break;
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};
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};
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break;
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case 0x60: /* specific EOI 0 */
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case 0x61: /* specific EOI 1 */
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case 0x62: /* specific EOI 2 */
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case 0x63: /* specific EOI 3 */
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case 0x64: /* specific EOI 4 */
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case 0x65: /* specific EOI 5 */
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case 0x66: /* specific EOI 6 */
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case 0x67: /* specific EOI 7 */
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if (irqs[val-0x60+8].inservice) {
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irqs[val-0x60+8].inservice=false;
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if (irqs[val-0x60+8].handler!=0) irqs[val-0x60+8].handler();
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};
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break;
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// IRQ lowest priority commands
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case 0xC0: // 0 7 6 5 4 3 2 1
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case 0xC1: // 1 0 7 6 5 4 3 2
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case 0xC2: // 2 1 0 7 6 5 4 3
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case 0xC3: // 3 2 1 0 7 6 5 4
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case 0xC4: // 4 3 2 1 0 7 6 5
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case 0xC5: // 5 4 3 2 1 0 7 6
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case 0xC6: // 6 5 4 3 2 1 0 7
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case 0xC7: // 7 6 5 4 3 2 1 0
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//TODO Maybe does it even matter?
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break;
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default:
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E_Exit("Unhandled command %04X sent to port A0",val);
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}
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}
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static void write_pa1(Bit32u port,Bit8u val) {
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Bit8u i;
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switch(pic1_icw_state) {
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case 0: /* mask register */
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for (i=0;i<=7;i++) {
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irqs[i+8].masked=(val&1 <<i)>0;
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};
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break;
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case 1: /* icw2 */
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for (i=0;i<=7;i++) {
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irqs[i+8].vector=(val&0xf8)+i;
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};
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default: /* icw2, 3, and 4*/
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if(pic1_icw_state++ >= pic1_icws) pic1_icw_state=0;
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}
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}
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static Bit8u read_pa0(Bit32u port) {
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Bit8u ret=0;
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Bit32u i;
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Bit8u b=1;
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if (pic1_request_iisr) {
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for (i=0;i<=7;i++) {
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if (irqs[i+8].inservice) ret|=b;
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b <<= 1;
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}
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} else {
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for (i=0;i<=7;i++) {
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if (irqs[i+8].active) ret|=b;
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b <<= 1;
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}
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};
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return ret;
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}
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static Bit8u read_pa1(Bit32u port) {
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Bit8u ret=0;
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Bit32u i;
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Bit8u b=1;
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for (i=0;i<=7;i++) {
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if (irqs[i+8].masked) ret|=b;
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b <<= 1;
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}
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return ret;
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}
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void PIC_RegisterIRQ(Bit32u irq,PIC_EOIHandler handler,char * name) {
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if (irq>15) E_Exit("PIC:Illegal IRQ");
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irqs[irq].name=name;
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irqs[irq].handler=handler;
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}
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void PIC_FreeIRQ(Bit32u irq) {
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if (irq>15) E_Exit("PIC:Illegal IRQ");
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irqs[irq].name=0;
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irqs[irq].handler=0;
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irqs[irq].active=0;
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irqs[irq].inservice=0;
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PIC_IRQCheck&=~(1 << irq);
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}
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void PIC_ActivateIRQ(Bit32u irq) {
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if (irq<16) {
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irqs[irq].active=true;
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if (!irqs[irq].masked) {
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PIC_IRQCheck|=(1 << irq);
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}
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}
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}
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void PIC_DeActivateIRQ(Bit32u irq) {
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if (irq<16) {
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irqs[irq].active=false;
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PIC_IRQCheck&=~(1 << irq);
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}
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}
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bool PIC_IRQActive(Bit32u irq) {
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if (irq<16) {
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return irqs[irq].active;
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}
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return true;
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}
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#define PIC_MAXQUEUE 16
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static PIC_Function * pic_queue[PIC_MAXQUEUE];
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static Bit32u pic_queuesize;
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void PIC_QueueFunction(PIC_Function * function) {
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if (pic_queuesize<PIC_MAXQUEUE) {
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pic_queue[pic_queuesize]=function;
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pic_queuesize++;
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} else {
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E_Exit("PIC Queue OverFlow");
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}
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}
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//TODO check for IRQ 2 being masked before checking 8-15 but then again do i need so many irqs
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void PIC_runIRQs(void) {
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Bit32u i;
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if (!flags.intf) goto noirqs;
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if (!PIC_IRQCheck) goto noirqs;
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for (i=0;i<=15;i++) {
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if (i!=2) {
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if (!irqs[i].masked && irqs[i].active /* && !irqs[i].inservice */) {
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irqs[i].inservice=true;
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irqs[i].active=false;
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PIC_IRQCheck&=~(1 << i);
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Interrupt(irqs[i].vector);
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break;
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};
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};
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};
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noirqs:
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/* This also runs special hardware functions that can queue themselves here */
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for (;pic_queuesize>0;) {
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(*pic_queue[--pic_queuesize])();
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}
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};
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void PIC_Init(void) {
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/* Setup pic0 and pic1 with initial values like DOS has normally */
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PIC_IRQCheck=0;
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Bit8u i;
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for (i=0;i<=7;i++) {
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irqs[i].active=false;
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irqs[i].masked=true;
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irqs[i].inservice=false;
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irqs[i+8].active=false;
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irqs[i+8].masked=true;
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irqs[i+8].inservice=false;
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irqs[i].vector=0x8+i;
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irqs[i+8].vector=0x70+i;
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};
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irqs[0].masked=false; /* Enable system timer */
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irqs[1].masked=false; /* Enable Keyboard IRQ */
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irqs[2].masked=false; /* Enable 2nd PIC Although i can't care if this is masked */
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irqs[12].masked=false;
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IO_RegisterReadHandler(0x20,read_p20,"Master PIC Command");
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IO_RegisterReadHandler(0x21,read_p21,"Master PIC Data");
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IO_RegisterWriteHandler(0x20,write_p20,"Master PIC Command");
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IO_RegisterWriteHandler(0x21,write_p21,"Master PIC Data");
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IO_RegisterReadHandler(0xa0,read_pa0,"Slave PIC Command");
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IO_RegisterReadHandler(0xa1,read_pa1,"Slave PIC Data");
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IO_RegisterWriteHandler(0xa0,write_pa0,"Slave PIC Command");
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IO_RegisterWriteHandler(0xa1,write_pa1,"Slave PIC Data");
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};
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