New register layout.
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@139
This commit is contained in:
parent
6624636b32
commit
4651bac31d
1 changed files with 37 additions and 25 deletions
|
@ -51,7 +51,7 @@ struct CPU_Regs {
|
|||
struct {
|
||||
Bit8u l,h;
|
||||
}b;
|
||||
} ax,bx,cx,dx,si,di,sp,bp,ip;
|
||||
} regs[8],ip;
|
||||
};
|
||||
|
||||
extern Segment Segs[6];
|
||||
|
@ -62,37 +62,49 @@ void SetSegment_16(Bit32u seg,Bit16u val);
|
|||
|
||||
|
||||
//extern Bit8u & reg_al=cpu_regs.ax.b.l;
|
||||
#define reg_al cpu_regs.ax.b.l
|
||||
#define reg_ah cpu_regs.ax.b.h
|
||||
#define reg_ax cpu_regs.ax.w
|
||||
#define reg_eax cpu_regs.ax.d
|
||||
enum REG_NUM {
|
||||
REG_NUM_AX, REG_NUM_CX, REG_NUM_DX, REG_NUM_BX,
|
||||
REG_NUM_SP, REG_NUM_BP, REG_NUM_SI, REG_NUM_DI
|
||||
};
|
||||
|
||||
#define reg_bl cpu_regs.bx.b.l
|
||||
#define reg_bh cpu_regs.bx.b.h
|
||||
#define reg_bx cpu_regs.bx.w
|
||||
#define reg_ebx cpu_regs.bx.d
|
||||
//macros to convert a 3-bit register index to the correct register
|
||||
#define reg_8l(reg) (cpu_regs.regs[(reg)].b.l)
|
||||
#define reg_8h(reg) (cpu_regs.regs[(reg)].b.h)
|
||||
#define reg_8(reg) ((reg) & 4 ? reg_8h((reg) & 3) : reg_8l((reg) & 3))
|
||||
#define reg_16(reg) (cpu_regs.regs[(reg)].w)
|
||||
#define reg_32(reg) (cpu_regs.regs[(reg)].d)
|
||||
|
||||
#define reg_cl cpu_regs.cx.b.l
|
||||
#define reg_ch cpu_regs.cx.b.h
|
||||
#define reg_cx cpu_regs.cx.w
|
||||
#define reg_ecx cpu_regs.cx.d
|
||||
#define reg_al cpu_regs.regs[REG_NUM_AX].b.l
|
||||
#define reg_ah cpu_regs.regs[REG_NUM_AX].b.h
|
||||
#define reg_ax cpu_regs.regs[REG_NUM_AX].w
|
||||
#define reg_eax cpu_regs.regs[REG_NUM_AX].d
|
||||
|
||||
#define reg_dl cpu_regs.dx.b.l
|
||||
#define reg_dh cpu_regs.dx.b.h
|
||||
#define reg_dx cpu_regs.dx.w
|
||||
#define reg_edx cpu_regs.dx.d
|
||||
#define reg_bl cpu_regs.regs[REG_NUM_BX].b.l
|
||||
#define reg_bh cpu_regs.regs[REG_NUM_BX].b.h
|
||||
#define reg_bx cpu_regs.regs[REG_NUM_BX].w
|
||||
#define reg_ebx cpu_regs.regs[REG_NUM_BX].d
|
||||
|
||||
#define reg_si cpu_regs.si.w
|
||||
#define reg_esi cpu_regs.si.d
|
||||
#define reg_cl cpu_regs.regs[REG_NUM_CX].b.l
|
||||
#define reg_ch cpu_regs.regs[REG_NUM_CX].b.h
|
||||
#define reg_cx cpu_regs.regs[REG_NUM_CX].w
|
||||
#define reg_ecx cpu_regs.regs[REG_NUM_CX].d
|
||||
|
||||
#define reg_di cpu_regs.di.w
|
||||
#define reg_edi cpu_regs.di.d
|
||||
#define reg_dl cpu_regs.regs[REG_NUM_DX].b.l
|
||||
#define reg_dh cpu_regs.regs[REG_NUM_DX].b.h
|
||||
#define reg_dx cpu_regs.regs[REG_NUM_DX].w
|
||||
#define reg_edx cpu_regs.regs[REG_NUM_DX].d
|
||||
|
||||
#define reg_sp cpu_regs.sp.w
|
||||
#define reg_esp cpu_regs.sp.d
|
||||
#define reg_si cpu_regs.regs[REG_NUM_SI].w
|
||||
#define reg_esi cpu_regs.regs[REG_NUM_SI].d
|
||||
|
||||
#define reg_bp cpu_regs.bp.w
|
||||
#define reg_ebp cpu_regs.bp.d
|
||||
#define reg_di cpu_regs.regs[REG_NUM_DI].w
|
||||
#define reg_edi cpu_regs.regs[REG_NUM_DI].d
|
||||
|
||||
#define reg_sp cpu_regs.regs[REG_NUM_SP].w
|
||||
#define reg_esp cpu_regs.regs[REG_NUM_SP].d
|
||||
|
||||
#define reg_bp cpu_regs.regs[REG_NUM_BP].w
|
||||
#define reg_ebp cpu_regs.regs[REG_NUM_BP].d
|
||||
|
||||
#define reg_ip cpu_regs.ip.w
|
||||
#define reg_eip cpu_regs.ip.d
|
||||
|
|
Loading…
Add table
Reference in a new issue