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Optimize xchg a bit. (jmarsh)

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@4333
This commit is contained in:
Peter Veenstra 2020-02-24 20:02:58 +00:00
parent 5d654fc5c5
commit 5afd7057f3
2 changed files with 6 additions and 4 deletions
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5
src/cpu/core_dyn_x86/risc_x64.h
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@ -608,7 +608,8 @@ static void gen_dop_byte(DualOps op,DynReg * dr1,Bitu di1,DynReg * dr2,Bitu di2)
case DOP_OR: tmp=0x0a; if ((dr1==dr2) && (di1==di2)) goto nochange; break;
case DOP_TEST: tmp=0x84; goto nochange;
case DOP_MOV: if ((dr1==dr2) && (di1==di2)) return; tmp=0x8a; break;
case DOP_XCHG: tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
case DOP_XCHG: if ((dr1==dr2) && (di1==di2)) return;
tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
default:
IllegalOption("gen_dop_byte");
}
@ -786,7 +787,7 @@ static void gen_dop_word(DualOps op,bool dword,DynReg * dr1,DynReg * dr2) {
case DOP_OR: tmp=0x0b; if (dr1==dr2) goto nochange; break;
case DOP_TEST: tmp=0x85; goto nochange;
case DOP_MOV: if (dr1==dr2) return; tmp=0x8b; break;
case DOP_XCHG:
case DOP_XCHG: if (dr1==dr2) return;
dr2->flags|=DYNFLG_CHANGED;
if (dword && !((dr1->flags&DYNFLG_HAS8) ^ (dr2->flags&DYNFLG_HAS8))) {
dr1->genreg=gr2;gr2->dynreg=dr1;

5
src/cpu/core_dyn_x86/risc_x86.h
View file

@ -340,7 +340,8 @@ static void gen_dop_byte(DualOps op,DynReg * dr1,Bit8u di1,DynReg * dr2,Bit8u di
case DOP_OR: tmp=0x0a; if ((dr1==dr2) && (di1==di2)) goto nochange; break;
case DOP_TEST: tmp=0x84; goto nochange;
case DOP_MOV: if ((dr1==dr2) && (di1==di2)) return; tmp=0x8a; break;
case DOP_XCHG: tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
case DOP_XCHG: if ((dr1==dr2) && (di1==di2)) return;
tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
default:
IllegalOption("gen_dop_byte");
}
@ -507,7 +508,7 @@ static void gen_dop_word(DualOps op,bool dword,DynReg * dr1,DynReg * dr2) {
case DOP_OR: tmp=0x0b; if (dr1==dr2) goto nochange; break;
case DOP_TEST: tmp=0x85; goto nochange;
case DOP_MOV: if (dr1==dr2) return; tmp=0x8b; break;
case DOP_XCHG:
case DOP_XCHG: if (dr1==dr2) return;
dr2->flags|=DYNFLG_CHANGED;
if (dword && !((dr1->flags&DYNFLG_HAS8) ^ (dr2->flags&DYNFLG_HAS8))) {
dr1->genreg=gr2;dr1->genreg->dynreg=dr1;