diff --git a/src/cpu/core_dynrec/operators.h b/src/cpu/core_dynrec/operators.h
index 65b3dbfb..be667dcd 100644
--- a/src/cpu/core_dynrec/operators.h
+++ b/src/cpu/core_dynrec/operators.h
@@ -754,7 +754,7 @@ static Bit8u DRC_CALL_CONV dynrec_rol_byte_simple(Bit8u op1,Bit8u op2) {
 static Bit8u DRC_CALL_CONV dynrec_ror_byte(Bit8u op1,Bit8u op2) DRC_FC;
 static Bit8u DRC_CALL_CONV dynrec_ror_byte(Bit8u op1,Bit8u op2) {
 	if (!(op2&0x7)) {
-		if (op2&0x10) {
+		if (op2&0x18) {
 			FillFlagsNoCFOF();
 			SETFLAGBIT(CF,op1>>7);
 			SETFLAGBIT(OF,(op1>>7) ^ ((op1>>6) & 1));
diff --git a/src/cpu/instructions.h b/src/cpu/instructions.h
index 45b2c795..1a69ffb4 100644
--- a/src/cpu/instructions.h
+++ b/src/cpu/instructions.h
@@ -277,7 +277,7 @@
 
 #define RORB(op1,op2,load,save)						\
 	if (!(op2&0x7)) {								\
-		if (op2&0x10) {								\
+		if (op2&0x18) {								\
 			FillFlagsNoCFOF();						\
 			SETFLAGBIT(CF,op1>>7);					\
 			SETFLAGBIT(OF,(op1>>7) ^ ((op1>>6) & 1));			\