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Fix XLAT instruction with 32-bit address size

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Fix BSFw opcode to first load flags
Fix 16-bit bit testing opcodes to correct effective address


Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1569
This commit is contained in:
Sjoerd van der Berg 2004-01-11 16:31:55 +00:00
parent a3a44f588c
commit 69b007c833
4 changed files with 20 additions and 13 deletions
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26
src/cpu/core_full/load.h
View file

@ -78,7 +78,7 @@ l_M_Ewx:
goto l_M_EwGw;
case M_EwGwt:
inst.op2.d=reg_16(inst.rm_index);
inst.rm_eaa+=((Bit32s)inst.op2.d >> 4) * 2;
inst.rm_eaa+=((Bit16s)inst.op2.d >> 4) * 2;
goto l_M_Ew;
l_M_EwGw:
case M_EwGw:
@ -247,8 +247,7 @@ l_M_Ed:
inst.op1.d=reg_32(inst.code.extra);
break;
case L_FLG:
FillFlags();
inst.op1.d = reg_flags;
inst.op1.d = FillFlags();
break;
case L_SEG:
inst.op1.d=SegValue((SegNames)inst.code.extra);
@ -360,13 +359,20 @@ l_M_Ed:
case D_SETALC:
reg_al = get_CF() ? 0xFF : 0;
goto nextopcode;
case D_XLATw:
if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_bx+reg_al);
else reg_al=LoadMb(SegBase(ds)+reg_bx+reg_al);
goto nextopcode;
case D_XLATd:
if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_ebx+reg_al);
else reg_al=LoadMb(SegBase(ds)+reg_ebx+reg_al);
case D_XLAT:
if (inst.prefix & PREFIX_SEG) {
if (inst.prefix & PREFIX_ADDR) {
reg_al=LoadMb(inst.seg.base+(Bit32u)(reg_ebx+reg_al));
} else {
reg_al=LoadMb(inst.seg.base+(Bit16u)(reg_bx+reg_al));
}
} else {
if (inst.prefix & PREFIX_ADDR) {
reg_al=LoadMb(SegBase(ds)+(Bit32u)(reg_ebx+reg_al));
} else {
reg_al=LoadMb(SegBase(ds)+(Bit16u)(reg_bx+reg_al));
}
}
goto nextopcode;
case D_CBW:
reg_ax=(Bit8s)reg_al;

1
src/cpu/core_full/op.h
View file

@ -483,6 +483,7 @@ switch (inst.code.op) {
break;
case O_BSFw:
{
FillFlags();
if (!inst.op1.w) {
SETFLAGBIT(ZF,true);
goto nextopcode;

4
src/cpu/core_full/optable.h
View file

@ -150,7 +150,7 @@ static OpCode OpCodeTable[1024]={
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,6 ,0 ,M_GRP_1 },
{L_MODRM ,5 ,0 ,M_GRP_CL },{L_MODRM ,6 ,0 ,M_GRP_CL },
{L_Ib ,O_AAM ,0 ,0 },{L_Ib ,O_AAD ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLATw ,0 ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLAT ,0 ,0 ,0 },
//TODO FPU
/* 0xd8 - 0xdf */
{L_MODRM ,O_FPU ,0 ,0 },{L_MODRM ,O_FPU ,1 ,0 },
@ -506,7 +506,7 @@ static OpCode OpCodeTable[1024]={
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,7 ,0 ,M_GRP_1 },
{L_MODRM ,5 ,0 ,M_GRP_CL },{L_MODRM ,7 ,0 ,M_GRP_CL },
{L_Ib ,O_AAM ,0 ,0 },{L_Ib ,O_AAD ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLATd ,0 ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLAT ,0 ,0 ,0 },
/* 0x2d8 - 0x2df */
{L_MODRM ,O_FPU ,0 ,0 },{L_MODRM ,O_FPU ,1 ,0 },
{L_MODRM ,O_FPU ,2 ,0 },{L_MODRM ,O_FPU ,3 ,0 },

2
src/cpu/core_full/support.h
View file

@ -32,7 +32,7 @@ enum {
D_CBW,D_CWDE,
D_CWD,D_CDQ,
D_SETALC,
D_XLATw,D_XLATd,
D_XLAT,
D_CLI,D_STI,D_STC,D_CLC,D_CMC,D_CLD,D_STD,
D_NOP,D_WAIT,
D_ENTERw,D_ENTERd,