CPU Cores keep their own flag handling
New lazyflags header file Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1086
This commit is contained in:
Sjoerd van der Berg
parent
cbd33bfa95
commit
708d8cb3c3
8 changed files with 160 additions and 29 deletions
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@ -3,24 +3,51 @@
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#include "pic.h"
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#include "regs.h"
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#include "cpu.h"
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#include "lazyflags.h"
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#include "fpu.h"
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#include "debug.h"
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#include "inout.h"
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#include "callback.h"
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Bit8u PAGE_Readb(PhysPt address);
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Bit16u PAGE_Readw(PhysPt address);
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Bit32u PAGE_Readd(PhysPt address);
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void PAGE_Writeb(PhysPt address,Bit8u val);
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void PAGE_Writew(PhysPt address,Bit16u val);
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void PAGE_Writed(PhysPt address,Bit32u val);
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typedef PhysPt EAPoint;
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#define SegBase(c) SegPhys(c)
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#define LoadMb(off) mem_readb_inline(off)
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#define LoadMw(off) mem_readw_inline(off)
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#define LoadMd(off) mem_readd_inline(off)
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#if 1
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#define LoadMb(off) mem_readb(off)
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#define LoadMw(off) mem_readw(off)
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#define LoadMd(off) mem_readd(off)
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#define LoadMbs(off) (Bit8s)(LoadMb(off))
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#define LoadMws(off) (Bit16s)(LoadMw(off))
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#define LoadMds(off) (Bit32s)(LoadMd(off))
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#define SaveMb(off,val) mem_writeb_inline(off,val)
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#define SaveMw(off,val) mem_writew_inline(off,val)
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#define SaveMd(off,val) mem_writed_inline(off,val)
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#define SaveMb(off,val) mem_writeb(off,val)
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#define SaveMw(off,val) mem_writew(off,val)
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#define SaveMd(off,val) mem_writed(off,val)
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#else
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#define LoadMb(off) PAGE_Readb(off)
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#define LoadMw(off) PAGE_Readw(off)
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#define LoadMd(off) PAGE_Readd(off)
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#define LoadMbs(off) (Bit8s)(LoadMb(off))
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#define LoadMws(off) (Bit16s)(LoadMw(off))
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#define LoadMds(off) (Bit32s)(LoadMd(off))
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#define SaveMb(off,val) PAGE_Writeb(off,val)
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#define SaveMw(off,val) PAGE_Writew(off,val)
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#define SaveMd(off,val) PAGE_Writed(off,val)
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#endif
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#define LoadD(reg) reg
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#define SaveD(reg,val) reg=val
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@ -43,10 +70,14 @@ static INLINE void DecodeModRM(void) {
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if (inst.rm<0xc0) inst.rm_eaa=(inst.prefix & PREFIX_ADDR) ? RMAddress_32() : RMAddress_16();
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}
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#define LEAVECORE \
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SaveIP(); \
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FILLFLAGS;
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#define EXCEPTION(blah) \
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{ \
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Bit8u new_num=blah; \
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SaveIP(); \
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LEAVECORE; \
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Interrupt(new_num); \
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LoadIP(); \
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goto nextopcode; \
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@ -55,11 +86,12 @@ static INLINE void DecodeModRM(void) {
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Bitu Full_DeCode(void) {
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LoadIP();
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flags.type=t_UNKNOWN;
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while (CPU_Cycles>0) {
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#if C_DEBUG
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cycle_count++;
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#if C_HEAVY_DEBUG
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SaveIP();
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LEAVECORE;
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if (DEBUG_HeavyIsBreakpoint()) return 1;
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#endif
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#endif
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@ -76,8 +108,8 @@ restartopcode:
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nextopcode:;
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CPU_Cycles--;
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}
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SaveIP();
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return 0;
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LEAVECORE;
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return CBRET_NONE;
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}
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@ -265,10 +265,12 @@ l_M_Ed:
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inst.op1.d=4;
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break;
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case D_IRETw:
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flags.type=t_UNKNOWN;
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CPU_IRET(false);
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LoadIP();
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goto nextopcode;
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case D_IRETd:
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flags.type=t_UNKNOWN;
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CPU_IRET(true);
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LoadIP();
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goto nextopcode;
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@ -470,7 +472,7 @@ l_M_Ed:
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CPU_CPUID();
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goto nextopcode;
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case D_HLT:
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SaveIP();
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LEAVECORE;
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CPU_HLT();
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return 0x0;
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default:
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@ -80,10 +80,9 @@ static INLINE Bit32u Pop_32(void) {
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}
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}
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#if 0
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if (flags.intf && PIC_IRQCheck) { \
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SaveIP(); \
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LEAVECORE; \
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PIC_runIRQs(); \
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LoadIP(); \
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} \
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@ -339,7 +339,7 @@ switch (inst.code.op) {
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goto nextopcode;
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case O_INT:
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SaveIP();
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LEAVECORE;
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#if C_DEBUG
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if (((inst.entry & 0xFF)==0xcc) && DEBUG_Breakpoint()) return 1;
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else if (DEBUG_IntBreakpoint(inst.op1.b)) return 1;
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@ -371,7 +371,7 @@ switch (inst.code.op) {
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goto nextopcode;
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case O_CBACK:
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if (inst.op1.d<CB_MAX) {
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SaveIP();
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LEAVECORE;
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Bitu ret=CallBack_Handlers[inst.op1.d]();
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switch (ret) {
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case CBRET_NONE:
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@ -409,9 +409,11 @@ switch (inst.code.op) {
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CPU_LTR(inst.op1.d);
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goto nextopcode; /* Else value will saved */
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case 0x04: /* VERR */
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FILLFLAGS;
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CPU_VERR(inst.op1.d);
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goto nextopcode; /* Else value will saved */
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case 0x05: /* VERW */
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FILLFLAGS;
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CPU_VERW(inst.op1.d);
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goto nextopcode; /* Else value will saved */
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@ -452,6 +454,7 @@ switch (inst.code.op) {
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break;
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}
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case 6: /* LMSW */
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FILLFLAGS;
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CPU_LMSW(inst.op1.w);
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goto nextopcode;
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default:
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@ -466,18 +469,21 @@ switch (inst.code.op) {
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break;
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case O_LAR:
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{
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FILLFLAGS;
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Bitu ar;CPU_LAR(inst.op1.d,ar);
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inst.op1.d=ar;
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}
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break;
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case O_LSL:
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{
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FILLFLAGS;
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Bitu limit;CPU_LSL(inst.op1.d,limit);
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inst.op1.d=limit;
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}
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break;
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case O_ARPL:
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{
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FILLFLAGS;
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Bitu new_sel=inst.op1.d;
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CPU_ARPL(new_sel,inst.op2.d);
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inst.op1.d=new_sel;
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@ -99,10 +99,10 @@ switch (inst.code.save) {
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LoadIP();
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break;
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case S_FLGb:
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SETFLAGSb(inst.op1.d);
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SETFLAGSb(inst.op1.b);
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break;
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case S_FLGw:
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SETFLAGSw(inst.op1.d);
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SETFLAGSw(inst.op1.w);
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break;
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case S_FLGd:
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SETFLAGSd(inst.op1.d);
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@ -112,6 +112,10 @@ PhysPt SelBase(Bitu sel) {
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}
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}
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void CPU_SetFlags(Bitu word) {
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flags.word=word;
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}
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bool CPU_CheckState(void) {
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Bitu old_state=cpu.state;
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cpu.state=0;
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@ -184,8 +188,7 @@ bool Interrupt(Bitu num) {
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break;
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};
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#endif
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FILLFLAGS;
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if (!(cpu.state & STATE_PROTECTED)) { /* RealMode Interrupt */
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/* Save everything on a 16-bit stack */
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CPU_Push16(flags.word & 0xffff);
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@ -262,11 +265,11 @@ bool CPU_IRET(bool use32) {
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if (use32) {
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reg_eip=CPU_Pop32();
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SegSet16(cs,CPU_Pop32());
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SETFLAGSw(CPU_Pop32());
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CPU_SetFlags(CPU_Pop32());
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} else {
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reg_eip=CPU_Pop16();
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SegSet16(cs,CPU_Pop16());
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SETFLAGSw(CPU_Pop16());
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CPU_SetFlagsw(CPU_Pop16());
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}
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return true;
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} else { /* Protected mode IRET */
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@ -280,7 +283,7 @@ bool CPU_IRET(bool use32) {
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} else {
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offset=CPU_Pop16();
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selector=CPU_Pop16();
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old_flags=CPU_Pop16();
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old_flags=(flags.word & 0xffff0000) | CPU_Pop16();
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}
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Bitu rpl=selector & 3;
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Descriptor desc;
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@ -304,7 +307,7 @@ bool CPU_IRET(bool use32) {
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Segs.big[cs]=desc.Big();
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Segs.val[cs]=(selector & 0xfffc) | cpu.cpl;;
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reg_eip=offset;
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SETFLAGSw(old_flags);
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CPU_SetFlags(old_flags);
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LOG_MSG("IRET:Same level return to %X:%X",selector,offset);
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} else {
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/* Return to higher privilege */
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@ -591,7 +594,6 @@ bool CPU_LMSW(Bitu word) {
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}
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void CPU_ARPL(Bitu & dest_sel,Bitu src_sel) {
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flags.type=t_UNKNOWN;
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if ((dest_sel & 3) < (src_sel & 3)) {
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dest_sel=(dest_sel & 0xfffc) + (src_sel & 3);
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// dest_sel|=0xff3f0000;
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@ -603,7 +605,6 @@ void CPU_ARPL(Bitu & dest_sel,Bitu src_sel) {
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void CPU_LAR(Bitu selector,Bitu & ar) {
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Descriptor desc;Bitu rpl=selector & 3;
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flags.type=t_UNKNOWN;
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if (!cpu.gdt.GetDescriptor(selector,desc)){
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SETFLAGBIT(ZF,false);
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return;
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@ -651,7 +652,6 @@ void CPU_LAR(Bitu selector,Bitu & ar) {
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void CPU_LSL(Bitu selector,Bitu & limit) {
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Descriptor desc;Bitu rpl=selector & 3;
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flags.type=t_UNKNOWN;
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if (!cpu.gdt.GetDescriptor(selector,desc)){
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SETFLAGBIT(ZF,false);
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return;
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@ -694,7 +694,6 @@ void CPU_LSL(Bitu selector,Bitu & limit) {
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void CPU_VERR(Bitu selector) {
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Descriptor desc;Bitu rpl=selector & 3;
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flags.type=t_UNKNOWN;
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if (!cpu.gdt.GetDescriptor(selector,desc)){
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SETFLAGBIT(ZF,false);
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return;
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@ -727,7 +726,6 @@ void CPU_VERR(Bitu selector) {
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void CPU_VERW(Bitu selector) {
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Descriptor desc;Bitu rpl=selector & 3;
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flags.type=t_UNKNOWN;
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if (!cpu.gdt.GetDescriptor(selector,desc)){
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SETFLAGBIT(ZF,false);
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return;
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@ -846,7 +844,6 @@ void CPU_Init(Section* sec) {
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reg_eip=0;
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flags.word=FLAG_IF;
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flags.type=t_UNKNOWN;
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cpu.full.entry=cpu.full.prefix=0;
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cpu.state=0xff; //To initialize it the first time
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@ -23,6 +23,7 @@
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#include "dosbox.h"
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#include "cpu.h"
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#include "lazyflags.h"
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#include "pic.h"
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94
src/cpu/lazyflags.h
Normal file
94
src/cpu/lazyflags.h
Normal file
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@ -0,0 +1,94 @@
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/*
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* Copyright (C) 2002-2003 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Library General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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//Flag Handling
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Bitu get_CF(void);
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Bitu get_AF(void);
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Bitu get_ZF(void);
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Bitu get_SF(void);
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Bitu get_OF(void);
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Bitu get_PF(void);
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#define SETFLAGSb(FLAGB) \
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{ \
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flags.type=t_UNKNOWN; \
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flags.word&=0xffffff00; \
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flags.word|=(FLAGB&0xff); \
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}
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#define SETFLAGSw(FLAGW) \
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{ \
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flags.type=t_UNKNOWN; \
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CPU_SetFlagsw(FLAGW); \
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}
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#define SETFLAGSd(FLAGD) \
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{ \
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flags.type=t_UNKNOWN; \
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CPU_SetFlags(FLAGD); \
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}
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#define FILLFLAGS \
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{ \
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flags.word=(flags.word & ~FLAG_MASK) | \
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(get_CF() ? FLAG_CF : 0 ) | \
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(get_PF() ? FLAG_PF : 0 ) | \
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(get_AF() ? FLAG_AF : 0 ) | \
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(get_ZF() ? FLAG_ZF : 0 ) | \
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(get_SF() ? FLAG_SF : 0 ) | \
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(get_OF() ? FLAG_OF : 0 ); \
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flags.type=t_UNKNOWN; \
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}
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#define LoadCF SETFLAGBIT(CF,get_CF());
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#define LoadZF SETFLAGBIT(ZF,get_ZF());
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#define LoadSF SETFLAGBIT(SF,get_SF());
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#define LoadOF SETFLAGBIT(OF,get_OF());
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#define LoadAF SETFLAGBIT(AF,get_AF());
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//Types of Flag changing instructions
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enum {
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t_UNKNOWN=0,
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t_ADDb,t_ADDw,t_ADDd,
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t_ORb,t_ORw,t_ORd,
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t_ADCb,t_ADCw,t_ADCd,
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t_SBBb,t_SBBw,t_SBBd,
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t_ANDb,t_ANDw,t_ANDd,
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t_SUBb,t_SUBw,t_SUBd,
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t_XORb,t_XORw,t_XORd,
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t_CMPb,t_CMPw,t_CMPd,
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t_INCb,t_INCw,t_INCd,
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t_DECb,t_DECw,t_DECd,
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t_TESTb,t_TESTw,t_TESTd,
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t_SHLb,t_SHLw,t_SHLd,
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t_SHRb,t_SHRw,t_SHRd,
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t_SARb,t_SARw,t_SARd,
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t_ROLb,t_ROLw,t_ROLd,
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t_RORb,t_RORw,t_RORd,
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t_RCLb,t_RCLw,t_RCLd,
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t_RCRb,t_RCRw,t_RCRd,
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t_NEGb,t_NEGw,t_NEGd,
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t_CF,t_ZF,
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t_DSHLw,t_DSHLd,
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t_DSHRw,t_DSHRd,
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t_MUL,t_DIV,
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t_NOTDONE,
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t_LASTFLAG
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};
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