diff --git a/src/cpu/core_full.cpp b/src/cpu/core_full.cpp index 67999d92..dcaf00d4 100644 --- a/src/cpu/core_full.cpp +++ b/src/cpu/core_full.cpp @@ -47,23 +47,11 @@ typedef PhysPt EAPoint; #define LoadD(reg) reg #define SaveD(reg,val) reg=val -static EAPoint IPPoint; - #include "core_full/loadwrite.h" #include "core_full/support.h" #include "core_full/optable.h" -#include "core_full/ea_lookup.h" #include "instructions.h" -static INLINE void DecodeModRM(void) { - inst.rm=Fetchb(); - inst.rm_index=(inst.rm >> 3) & 7; - inst.rm_eai=inst.rm&07; - inst.rm_mod=inst.rm>>6; - /* Decode address of mod/rm if needed */ - if (inst.rm<0xc0) inst.rm_eaa=(inst.prefix & PREFIX_ADDR) ? RMAddress_32() : RMAddress_16(); -} - #define LEAVECORE \ SaveIP(); \ FillFlags(); @@ -79,7 +67,15 @@ static INLINE void DecodeModRM(void) { } Bits Full_DeCode(void) { - + FullData inst; + if (!cpu.code.big) { + inst.start_prefix=0x0;; + inst.start_entry=0x0; + } else { + inst.start_prefix=PREFIX_ADDR; + inst.start_entry=0x200; + } + EAPoint IPPoint; LoadIP(); flags.type=t_UNKNOWN; while (CPU_Cycles>0) { @@ -98,7 +94,6 @@ Bits Full_DeCode(void) { inst.prefix=inst.start_prefix; restartopcode: inst.entry=(inst.entry & 0xffffff00) | Fetchb(); - inst.code=OpCodeTable[inst.entry]; #include "core_full/load.h" #include "core_full/op.h" @@ -112,12 +107,5 @@ nextopcode:; void CPU_Core_Full_Start(bool big) { - if (!big) { - inst.start_prefix=0x0;; - inst.start_entry=0x0; - } else { - inst.start_prefix=PREFIX_ADDR; - inst.start_entry=0x200; - } cpudecoder=&Full_DeCode; } diff --git a/src/cpu/core_full/ea_lookup.h b/src/cpu/core_full/ea_lookup.h index 0c19b04e..cd8834e0 100644 --- a/src/cpu/core_full/ea_lookup.h +++ b/src/cpu/core_full/ea_lookup.h @@ -1,4 +1,4 @@ -static EAPoint RMAddress_16(void) { +{ EAPoint seg_base; Bit16u off; switch ((inst.rm_mod<<3)|inst.rm_eai) { @@ -103,16 +103,13 @@ static EAPoint RMAddress_16(void) { } inst.rm_off=off; if (inst.prefix & PREFIX_SEG) { - return inst.seg.base+off; + inst.rm_eaa=inst.seg.base+off; } else { - return seg_base+off; + inst.rm_eaa=seg_base+off; } -} +} else { -static Bit32u SIBZero=0; -static Bit32u * SIBIndex[8]= { ®_eax,®_ecx,®_edx,®_ebx,&SIBZero,®_ebp,®_esi,®_edi }; - #define SIB(MODE) { \ Bitu sib=Fetchb(); \ switch (sib&7) { \ @@ -128,9 +125,8 @@ static Bit32u * SIBIndex[8]= { ®_eax,®_ecx,®_edx,®_ebx,&SIBZero,® } \ off+=*SIBIndex[(sib >> 3) &7] << (sib >> 6); \ }; - - -static EAPoint RMAddress_32(void) { + static Bit32u SIBZero=0; + static Bit32u * SIBIndex[8]= { ®_eax,®_ecx,®_edx,®_ebx,&SIBZero,®_ebp,®_esi,®_edi }; EAPoint seg_base; Bit32u off; switch ((inst.rm_mod<<3)|inst.rm_eai) { @@ -231,13 +227,11 @@ static EAPoint RMAddress_32(void) { off=reg_edi+Fetchds(); seg_base=SegBase(ds); break; - - } inst.rm_off=off; if (inst.prefix & PREFIX_SEG) { - return inst.seg.base+off; + inst.rm_eaa=inst.seg.base+off; } else { - return seg_base+off; + inst.rm_eaa=seg_base+off; } } diff --git a/src/cpu/core_full/load.h b/src/cpu/core_full/load.h index e75cd13c..b0adcce4 100644 --- a/src/cpu/core_full/load.h +++ b/src/cpu/core_full/load.h @@ -1,7 +1,15 @@ switch (inst.code.load) { /* General loading */ case L_MODRM: - DecodeModRM(); + inst.rm=Fetchb(); + inst.rm_index=(inst.rm >> 3) & 7; + inst.rm_eai=inst.rm&07; + inst.rm_mod=inst.rm>>6; + /* Decode address of mod/rm if needed */ + if (inst.rm<0xc0) { + if (!(inst.prefix & PREFIX_ADDR)) + #include "ea_lookup.h" + } l_MODRMswitch: switch (inst.code.extra) { /* Byte */ @@ -266,32 +274,46 @@ l_M_Ed: break; case D_IRETw: flags.type=t_UNKNOWN; - CPU_IRET(false); - LoadIP(); + if (!CPU_IRET(false)) return CBRET_NONE; if (GETFLAG(IF) && PIC_IRQCheck) { - SaveIP(); return CBRET_NONE; } + LoadIP(); goto nextopcode; case D_IRETd: flags.type=t_UNKNOWN; - CPU_IRET(true); + if (!CPU_IRET(true)) return CBRET_NONE; + if (GETFLAG(IF) && PIC_IRQCheck) { + return CBRET_NONE; + } LoadIP(); goto nextopcode; case D_RETFwIw: - CPU_RET(false,Fetchw()); + if (!CPU_RET(false,Fetchw())) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case D_RETFw: - CPU_RET(false,0); + if (!CPU_RET(false,0)) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case D_RETFdIw: - CPU_RET(true,Fetchw()); + if (!CPU_RET(true,Fetchw())) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case D_RETFd: - CPU_RET(true,0); + if (!CPU_RET(true,0)) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; /* Direct operations */ diff --git a/src/cpu/core_full/loadwrite.h b/src/cpu/core_full/loadwrite.h index 4b990369..2a9bdb09 100644 --- a/src/cpu/core_full/loadwrite.h +++ b/src/cpu/core_full/loadwrite.h @@ -1,40 +1,32 @@ -static INLINE void SaveIP(void) { - Bitu left=IPPoint-SegBase(cs); - reg_eip=left; -} - -static INLINE void LoadIP(void) { - IPPoint=SegBase(cs)+reg_eip; -} +#define SaveIP() reg_eip=(Bit32u)(IPPoint-SegBase(cs)); +#define LoadIP() IPPoint=SegBase(cs)+reg_eip; -static INLINE Bit8u Fetchb() { - Bit8u temp=LoadMb(IPPoint); - IPPoint+=1; +static INLINE Bit8u the_Fetchb(EAPoint & loc) { + Bit8u temp=LoadMb(loc); + loc+=1; return temp; } -static INLINE Bit16u Fetchw() { - Bit16u temp=LoadMw(IPPoint); - IPPoint+=2; +static INLINE Bit16u the_Fetchw(EAPoint & loc) { + Bit16u temp=LoadMw(loc); + loc+=2; return temp; } -static INLINE Bit32u Fetchd() { - Bit32u temp=LoadMd(IPPoint); - IPPoint+=4; +static INLINE Bit32u the_Fetchd(EAPoint & loc) { + Bit32u temp=LoadMd(loc); + loc+=4; return temp; } -static INLINE Bit8s Fetchbs() { - return Fetchb(); -} -static INLINE Bit16s Fetchws() { - return Fetchw(); -} +#define Fetchb() the_Fetchb(IPPoint) +#define Fetchw() the_Fetchw(IPPoint) +#define Fetchd() the_Fetchd(IPPoint) + +#define Fetchbs() (Bit8s)the_Fetchb(IPPoint) +#define Fetchws() (Bit16s)the_Fetchw(IPPoint) +#define Fetchds() (Bit32s)the_Fetchd(IPPoint) -static INLINE Bit32s Fetchds() { - return Fetchd(); -} static INLINE void Push_16(Bit16u blah) { reg_esp-=2; diff --git a/src/cpu/core_full/op.h b/src/cpu/core_full/op.h index 6eaae095..3a5e4200 100644 --- a/src/cpu/core_full/op.h +++ b/src/cpu/core_full/op.h @@ -321,20 +321,32 @@ switch (inst.code.op) { break; case O_CALLFw: SaveIP(); - CPU_CALL(false,inst.op2.d,inst.op1.d); + if (!CPU_CALL(false,inst.op2.d,inst.op1.d)) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case O_CALLFd: SaveIP(); - CPU_CALL(true,inst.op2.d,inst.op1.d); + if (!CPU_CALL(true,inst.op2.d,inst.op1.d)) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case O_JMPFw: - CPU_JMP(false,inst.op2.d,inst.op1.d); + if (!CPU_JMP(false,inst.op2.d,inst.op1.d)){ + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; case O_JMPFd: - CPU_JMP(true,inst.op2.d,inst.op1.d); + if (!CPU_JMP(true,inst.op2.d,inst.op1.d)) { + FillFlags(); + return CBRET_NONE; + } LoadIP(); goto nextopcode; @@ -344,7 +356,7 @@ switch (inst.code.op) { if (((inst.entry & 0xFF)==0xcc) && DEBUG_Breakpoint()) return debugCallback; else if (DEBUG_IntBreakpoint(inst.op1.b)) return debugCallback; #endif - Interrupt(inst.op1.b); + if (!Interrupt(inst.op1.b)) return CBRET_NONE; LoadIP(); break; case O_INb: @@ -379,14 +391,14 @@ switch (inst.code.op) { { Bitu selector; CPU_SLDT(selector); - inst.op1.d=selector; + inst.op1.d=(Bit32u)selector; } break; case 0x01: /* STR */ { Bitu selector; CPU_STR(selector); - inst.op1.d=selector; + inst.op1.d=(Bit32u)selector; } break; case 0x02: /* LLDT */ @@ -403,8 +415,6 @@ switch (inst.code.op) { FillFlags(); CPU_VERW(inst.op1.d); goto nextopcode; /* Else value will saved */ - - default: LOG(LOG_CPU,LOG_ERROR)("Group 6 Illegal subfunction %X",inst.rm_index); } @@ -458,14 +468,14 @@ switch (inst.code.op) { { FillFlags(); Bitu ar;CPU_LAR(inst.op1.d,ar); - inst.op1.d=ar; + inst.op1.d=(Bit32u)ar; } break; case O_LSL: { FillFlags(); Bitu limit;CPU_LSL(inst.op1.d,limit); - inst.op1.d=limit; + inst.op1.d=(Bit32u)limit; } break; case O_ARPL: @@ -473,7 +483,7 @@ switch (inst.code.op) { FillFlags(); Bitu new_sel=inst.op1.d; CPU_ARPL(new_sel,inst.op2.d); - inst.op1.d=new_sel; + inst.op1.d=(Bit32u)new_sel; } break; case O_BSFw: @@ -549,7 +559,7 @@ switch (inst.code.op) { Bitu mask=1 << (inst.op1.d & 15); FillFlags(); if (inst.rm<0xc0) { - read=inst.rm_eaa+2*(inst.op1.d / 16); + read=inst.rm_eaa;//+2*(inst.op1.d / 16); val=mem_readw(read); } else { val=reg_16(inst.rm_eai); @@ -575,7 +585,7 @@ switch (inst.code.op) { Bitu mask=1 << (inst.op1.d & 31); FillFlags(); if (inst.rm<0xc0) { - read=inst.rm_eaa+4*(inst.op1.d / 32); + read=inst.rm_eaa;//+4*(inst.op1.d / 32); val=mem_readd(read); } else { val=reg_32(inst.rm_eai); diff --git a/src/cpu/core_full/support.h b/src/cpu/core_full/support.h index 5be628e4..fd50313b 100644 --- a/src/cpu/core_full/support.h +++ b/src/cpu/core_full/support.h @@ -154,7 +154,7 @@ struct OpCode { Bit8u load,op,save,extra; }; -static struct { +struct FullData { Bitu entry; EAPoint start; Bitu rm; @@ -178,7 +178,7 @@ static struct { Bitu prefix; Bitu start_prefix; Bitu start_entry; -} inst; +}; #define PREFIX_NONE 0x0