From 7a842811f02fbb2372432fedf66eb25e7026d65d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20Strohh=C3=A4cker?= Date: Sat, 8 Jul 2006 16:32:26 +0000 Subject: [PATCH] fix for virtual pool (vasyl) Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2668 --- include/vga.h | 17 ++++++++++++++++- src/hardware/vga_memory.cpp | 28 +++++++++++++++------------- src/hardware/vga_s3.cpp | 25 +++++++++++++------------ 3 files changed, 44 insertions(+), 26 deletions(-) diff --git a/include/vga.h b/include/vga.h index 8c365c9c..dcf0bd5d 100644 --- a/include/vga.h +++ b/include/vga.h @@ -140,8 +140,23 @@ typedef struct { Bit8u mc[64][64]; } VGA_HWCURSOR; +typedef union { + Bit32u fullbank; +#ifndef WORDS_BIGENDIAN + struct { + Bit16u lowerbank; + Bit16u bank; + } b; +#else + struct { + Bit16u bank; + Bit16u lowerbank; + } b; +#endif +} VGA_S3_BANK; + typedef struct { - Bit8u bank; + VGA_S3_BANK svga_bank; Bit8u reg_lock1; Bit8u reg_lock2; Bit8u reg_31; diff --git a/src/hardware/vga_memory.cpp b/src/hardware/vga_memory.cpp index 6138229a..0a4a5e8d 100644 --- a/src/hardware/vga_memory.cpp +++ b/src/hardware/vga_memory.cpp @@ -83,6 +83,7 @@ static struct { class VGA_UnchainedRead_Handler : public PageHandler { public: Bitu readHandler(PhysPt start) { + start += vga.s3.svga_bank.fullbank; vga.latch.d=vga.mem.latched[start].d; switch (vga.config.read_mode) { case 0: @@ -253,10 +254,10 @@ public: vga.mem.linear[((addr&~3)<<2)|(addr&3)] = val; // Linearized version for faster rendering vga.mem.linear[512*1024+addr] = val; + if (addr >= 320) return; // And replicate the first line - if (addr < 320) - vga.mem.linear[512*1024+addr+64*1024] = val; - } + vga.mem.linear[512*1024+addr+64*1024] = val; + } public: VGA_ChainedVGA_Handler() { flags=PFLAG_NOCODE; @@ -282,13 +283,13 @@ public: class VGA_UnchainedVGA_Handler : public VGA_UnchainedRead_Handler { public: void writeHandler( PhysPt addr, Bit8u val ) { + addr += vga.s3.svga_bank.fullbank; Bit32u data=ModeOperation(val); VGA_Latch pixels; pixels.d=vga.mem.latched[addr].d; pixels.d&=vga.config.full_not_map_mask; pixels.d|=(data & vga.config.full_map_mask); vga.mem.latched[addr].d=pixels.d; - vga.mem.latched[addr+64*1024].d=pixels.d; } public: VGA_UnchainedVGA_Handler() { @@ -336,11 +337,11 @@ public: } HostPt GetHostReadPt(Bitu phys_page) { phys_page-=vgapages.base; - return &vga.mem.linear[vga.s3.bank*64*1024+phys_page*4096]; + return &vga.mem.linear[vga.s3.svga_bank.fullbank+phys_page*4096]; } HostPt GetHostWritePt(Bitu phys_page) { phys_page-=vgapages.base; - return &vga.mem.linear[vga.s3.bank*64*1024+phys_page*4096]; + return &vga.mem.linear[vga.s3.svga_bank.fullbank+phys_page*4096]; } }; @@ -392,18 +393,18 @@ public: flags=PFLAG_NOCODE; } void writeb(PhysPt addr,Bitu val) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); writeHandler(addr+0,(Bit8u)(val >> 0)); } void writew(PhysPt addr,Bitu val) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); writeHandler(addr+0,(Bit8u)(val >> 0)); writeHandler(addr+1,(Bit8u)(val >> 8)); } void writed(PhysPt addr,Bitu val) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); writeHandler(addr+0,(Bit8u)(val >> 0)); writeHandler(addr+1,(Bit8u)(val >> 8)); @@ -411,19 +412,19 @@ public: writeHandler(addr+3,(Bit8u)(val >> 24)); } Bitu readb(PhysPt addr) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); return readHandler(addr); } Bitu readw(PhysPt addr) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); return (readHandler(addr+0) << 0) | (readHandler(addr+1) << 8); } Bitu readd(PhysPt addr) { - addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff); + addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff); addr &= (512*1024-1); return (readHandler(addr+0) << 0) | @@ -634,12 +635,12 @@ void VGA_SetupHandlers(void) { case M_LIN4: range_handler=&vgaph.l4banked; break; - case M_LIN8: case M_LIN15: case M_LIN16: case M_LIN32: range_handler=&vgaph.map; break; + case M_LIN8: case M_VGA: if (vga.config.chained) { if(vga.config.compatible_chain4) @@ -727,6 +728,7 @@ void VGA_UnmapMMIO(void) { void VGA_SetupMemory() { memset((void *)&vga.mem,0,512*1024*4); + vga.s3.svga_bank.fullbank=0; if (machine==MCH_PCJR) { /* PCJr does not have dedicated graphics memory but uses conventional memory below 128k */ diff --git a/src/hardware/vga_s3.cpp b/src/hardware/vga_s3.cpp index 8668cac8..c2459f3d 100644 --- a/src/hardware/vga_s3.cpp +++ b/src/hardware/vga_s3.cpp @@ -16,7 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $Id: vga_s3.cpp,v 1.3 2006-02-14 12:44:38 qbix79 Exp $ */ +/* $Id: vga_s3.cpp,v 1.4 2006-07-08 16:32:26 c2woody Exp $ */ #include "dosbox.h" #include "inout.h" @@ -26,7 +26,8 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) { switch (reg) { case 0x31: /* CR31 Memory Configuration */ //TODO Base address - vga.s3.reg_31 = val; + vga.s3.reg_31 = val; + vga.config.compatible_chain4 = !(val&0x08); VGA_DetermineMode(); break; /* @@ -46,9 +47,9 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) { case 0x35: /* CR35 CRT Register Lock */ if (vga.s3.reg_lock1 != 0x48) return; //Needed for uvconfig detection vga.s3.reg_35=val & 0xf0; - if ((vga.s3.bank & 0xf) ^ (val & 0xf)) { - vga.s3.bank&=0xf0; - vga.s3.bank|=val & 0xf; + if ((vga.s3.svga_bank.b.bank & 0xf) ^ (val & 0xf)) { + vga.s3.svga_bank.b.bank&=0xf0; + vga.s3.svga_bank.b.bank|=val & 0xf; VGA_SetupHandlers(); } break; @@ -128,9 +129,9 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) { //TODO Display start vga.config.display_start&=0xFCFFFF; vga.config.display_start|=(val & 3) << 16; - if ((vga.s3.bank&0xcf) ^ ((val&0xc)<<2)) { - vga.s3.bank&=0xcf; - vga.s3.bank|=(val&0xc)<<2; + if ((vga.s3.svga_bank.b.bank&0xcf) ^ ((val&0xc)<<2)) { + vga.s3.svga_bank.b.bank&=0xcf; + vga.s3.svga_bank.b.bank|=(val&0xc)<<2; VGA_SetupHandlers(); } if (((val & 0x30) ^ (vga.config.scan_len >> 4)) & 0x30) { @@ -297,7 +298,7 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) { } break; case 0x6a: /* Extended System Control 4 */ - vga.s3.bank=val & 0x3f; + vga.s3.svga_bank.b.bank=val & 0x3f; VGA_SetupHandlers(); break; default: @@ -323,7 +324,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) { //TODO mix in bits from baseaddress; return vga.s3.reg_31; case 0x35: /* CR35 CRT Register Lock */ - return vga.s3.reg_35|(vga.s3.bank & 0xf); + return vga.s3.reg_35|(vga.s3.svga_bank.b.bank & 0xf); case 0x36: /* CR36 Reset State Read 1 */ //return 0x8f; return 0x8e; /* PCI version */ @@ -344,7 +345,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) { return vga.s3.hgc.curmode; case 0x51: /* Extended System Control 2 */ return ((vga.config.display_start >> 16) & 3 ) | - ((vga.s3.bank & 0x30) >> 2) | + ((vga.s3.svga_bank.b.bank & 0x30) >> 2) | ((vga.config.scan_len & 0x300) >> 4) | vga.s3.reg_51; case 0x53: @@ -366,7 +367,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) { case 0x69: /* Extended System Control 3 */ return (Bit8u)((vga.config.display_start & 0x1f0000)>>16); case 0x6a: /* Extended System Control 4 */ - return (Bit8u)(vga.s3.bank & 0x3f); + return (Bit8u)(vga.s3.svga_bank.b.bank & 0x3f); default: return 0x00; }