diff --git a/include/vga.h b/include/vga.h
index f61f6e71..5fde426f 100644
--- a/include/vga.h
+++ b/include/vga.h
@@ -62,6 +62,7 @@ typedef struct {
 /* Some other screen related variables */
 	Bitu line_compare;
 	bool chained;					/* Enable or Disabled Chain 4 Mode */
+	bool compatible_chain4;
 
 	/* Pixel Scrolling */
 	Bit8u pel_panning;				/* Amount of pixels to skip when starting horizontal line */
diff --git a/src/hardware/vga_crtc.cpp b/src/hardware/vga_crtc.cpp
index 9c7445fb..82daa008 100644
--- a/src/hardware/vga_crtc.cpp
+++ b/src/hardware/vga_crtc.cpp
@@ -293,6 +293,8 @@ void write_p3d5_vga(Bitu port,Bitu val,Bitu iolen) {
 	case 0x31:	/* CR31 Memory Configuration */
 //TODO Base address
 		vga.s3.reg_31=val;	
+		vga.config.compatible_chain4 = !(val&0x08);
+		VGA_SetupHandlers();
 		break;
 		/*
 			0	Enable Base Address Offset (CPUA BASE). Enables bank operation if
diff --git a/src/hardware/vga_draw.cpp b/src/hardware/vga_draw.cpp
index 9c97e5b3..b0ff8370 100644
--- a/src/hardware/vga_draw.cpp
+++ b/src/hardware/vga_draw.cpp
@@ -131,6 +131,22 @@ static Bit8u * VGA_Draw_VGA_Line(Bitu vidstart,Bitu panning,Bitu line) {
 	return &vga.mem.linear[vidstart*4+panning];
 }
 
+static Bit8u * VGA_Draw_VGAChained_Line(Bitu vidstart,Bitu panning,Bitu line) {
+	if(vga.config.compatible_chain4) {
+		if(vga.crtc.underline_location & 0x40) {
+			Bitu readindex = vidstart*4+panning;
+			Bit32u* draw = (Bit32u*)TempLine;
+			for(Bitu x=0;x<vga.draw.blocks*4;x++) {
+				*draw = vga.mem.latched[readindex&0xfffc].d;
+				draw ++;
+				readindex += 4;
+			}
+			return TempLine;
+		}
+	}
+	return &vga.mem.linear[vidstart*4+panning];
+}
+
 static Bit8u * VGA_Draw_VGA_Line_HWMouse(Bitu vidstart, Bitu panning, Bitu line) {
 	if(vga.s3.hgc.curmode & 0x1) {
 		Bitu lineat = vidstart / ((160 * vga.draw.height) / 480);
@@ -438,7 +454,7 @@ void VGA_SetupDrawing(Bitu val) {
 	case M_VGA:
 		doublewidth=true;
 		width<<=2;
-		VGA_DrawLine=VGA_Draw_VGA_Line;
+		VGA_DrawLine=VGA_Draw_VGAChained_Line;
 		break;
 	case M_LIN8:
 		width<<=3;
diff --git a/src/hardware/vga_memory.cpp b/src/hardware/vga_memory.cpp
index edae45b3..17f8058f 100644
--- a/src/hardware/vga_memory.cpp
+++ b/src/hardware/vga_memory.cpp
@@ -41,9 +41,16 @@ static Bitu VGA_NormalReadHandler(PhysPt start) {
 }
 
 static Bitu VGA_Chain4ReadHandler(PhysPt start) {
+	if(vga.mode == M_VGA)
+		return vga.mem.linear[((start&~3)<<2)|(start&3)];
 	return vga.mem.linear[start];
 }
 
+static void VGA_Chain4WriteHandler(PhysPt start, Bit8u val) {
+	// No need to check for compatible chains here, this one is only enabled if that bit is set
+	vga.mem.linear[((start&~3)<<2)|(start&3)] = val;
+}
+
 //Nice one from DosEmu
 
 INLINE static Bit32u RasterOp(Bit32u input,Bit32u mask) {
@@ -279,6 +286,29 @@ public:
 	}
 };
 
+class VGA_256Chain4_PageHandler : public VGAReadChain4_PageHandler {
+public:	
+	VGA_256Chain4_PageHandler()  {
+		flags=PFLAG_NOCODE;
+	}
+	void writeb(PhysPt addr,Bitu val) {
+		addr = PAGING_GetLinearAddress(addr) & 0xffff;
+		VGA_Chain4WriteHandler(addr+0,(Bit8u)(val >> 0));
+	}
+	void writew(PhysPt addr,Bitu val) {
+		addr = PAGING_GetLinearAddress(addr) & 0xffff;
+		VGA_Chain4WriteHandler(addr+0,(Bit8u)(val >> 0));
+		VGA_Chain4WriteHandler(addr+1,(Bit8u)(val >> 8));
+	}
+	void writed(PhysPt addr,Bitu val) {
+		addr = PAGING_GetLinearAddress(addr) & 0xffff;
+		VGA_Chain4WriteHandler(addr+0,(Bit8u)(val >> 0));
+		VGA_Chain4WriteHandler(addr+1,(Bit8u)(val >> 8));
+		VGA_Chain4WriteHandler(addr+2,(Bit8u)(val >> 16));
+		VGA_Chain4WriteHandler(addr+3,(Bit8u)(val >> 24));
+	}
+};
+
 class VGA_TEXT_PageHandler : public PageHandler {
 public:
 	VGA_TEXT_PageHandler() {
@@ -405,6 +435,7 @@ static struct vg {
 	VGA_TEXT_PageHandler htext;
 	VGA_TANDY_PageHandler htandy;
 	VGA_256_PageHandler h256;
+	VGA_256Chain4_PageHandler h256c4;
 	VGA_16_PageHandler h16;
 	VGA_16Chain4_PageHandler h16c4;
 	VGA_MMIO_PageHandler mmio;
@@ -434,7 +465,10 @@ void VGA_SetupHandlers(void) {
 		break;
 	case M_VGA:
 		if (vga.config.chained) {
-			range_handler=&vgaph.hmap;
+			if(vga.config.compatible_chain4)
+				range_handler = &vgaph.h256c4;
+			else
+				range_handler=&vgaph.hmap;
 		} else {
 			range_handler=&vgaph.h256;
 		}
diff --git a/src/ints/int10_modes.cpp b/src/ints/int10_modes.cpp
index d527a8bf..06db9fdd 100644
--- a/src/ints/int10_modes.cpp
+++ b/src/ints/int10_modes.cpp
@@ -439,6 +439,8 @@ bool INT10_SetVideoMode(Bitu mode) {
 		IO_Write(0x3c4,i);
 		IO_Write(0x3c5,seq_data[i]);
 	}
+	vga.config.compatible_chain4 = true; // this may be changed by SVGA chipset emulation
+
 	/* Program CRTC */
 	/* First disable write protection */
 	IO_Write(crtc_base,0x11);
@@ -822,7 +824,8 @@ dac_text16:
 	IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 16));
 
 	/* Setup some remaining S3 registers */
-	IO_Write(crtc_base,0x31);IO_Write(crtc_base+1,0x9);	//Enable banked memory and 256k+ access
+//	IO_Write(crtc_base,0x31);IO_Write(crtc_base+1,0x9);	//Enable banked memory and 256k+ access
+	IO_Write(crtc_base,0x31);IO_Write(crtc_base+1,CurMode->mode<=0x13?0x1:0x9);	//Enable banked memory and 256k+ access for SVGA modes only
 	IO_Write(crtc_base,0x58);IO_Write(crtc_base+1,0x3);	//Enable 8 mb of linear addressing
 	IO_Write(crtc_base,0x38);IO_Write(crtc_base+1,0x48);	//Register lock 1
 	IO_Write(crtc_base,0x39);IO_Write(crtc_base+1,0xa5);	//Register lock 2