diff --git a/src/cpu/core_dynrec/decoder_opcodes.h b/src/cpu/core_dynrec/decoder_opcodes.h
index 22a5a556..25605046 100644
--- a/src/cpu/core_dynrec/decoder_opcodes.h
+++ b/src/cpu/core_dynrec/decoder_opcodes.h
@@ -16,6 +16,8 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
+/* $Id: decoder_opcodes.h,v 1.9 2009-06-25 19:31:43 c2woody Exp $ */
+
 
 /*
 	The functions in this file are called almost exclusively by	decoder.h,
@@ -544,8 +546,8 @@ static void dyn_dshift_ev_gv(bool left,bool immediate) {
 		MOV_REG_WORD_TO_HOST_REG(FC_OP1,decode.modrm.rm,decode.big_op);
 	}
 	MOV_REG_WORD_TO_HOST_REG(FC_OP2,decode.modrm.reg,decode.big_op);
-	if (immediate) gen_mov_byte_to_reg_low_imm(FC_RETOP,decode_fetchb());
-	else MOV_REG_BYTE_TO_HOST_REG_LOW(FC_RETOP,DRC_REG_ECX,0);
+	if (immediate) gen_mov_byte_to_reg_low_imm(FC_OP3,decode_fetchb());
+	else MOV_REG_BYTE_TO_HOST_REG_LOW(FC_OP3,DRC_REG_ECX,0);
 	if (decode.big_op) dyn_dpshift_dword_gencall(left);
 	else dyn_dpshift_word_gencall(left);
 
diff --git a/src/cpu/core_dynrec/operators.h b/src/cpu/core_dynrec/operators.h
index c4c89f17..eae97390 100644
--- a/src/cpu/core_dynrec/operators.h
+++ b/src/cpu/core_dynrec/operators.h
@@ -16,6 +16,8 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
+/* $Id: operators.h,v 1.8 2009-06-25 19:31:43 c2woody Exp $ */
+
 
 static Bit8u DRC_CALL_CONV dynrec_add_byte(Bit8u op1,Bit8u op2) DRC_FC;
 static Bit8u DRC_CALL_CONV dynrec_add_byte(Bit8u op1,Bit8u op2) {
@@ -1297,20 +1299,20 @@ static Bit32u DRC_CALL_CONV dynrec_dshr_dword_simple(Bit32u op1,Bit32u op2,Bit8u
 
 static void dyn_dpshift_word_gencall(bool left) {
 	if (left) {
-		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshl_word,FC_RETOP);
+		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshl_word,FC_OP3);
 		InvalidateFlagsPartially((void*)&dynrec_dshl_word_simple,proc_addr,t_DSHLw);
 	} else {
-		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshr_word,FC_RETOP);
+		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshr_word,FC_OP3);
 		InvalidateFlagsPartially((void*)&dynrec_dshr_word_simple,proc_addr,t_DSHRw);
 	}
 }
 
 static void dyn_dpshift_dword_gencall(bool left) {
 	if (left) {
-		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshl_dword,FC_RETOP);
+		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshl_dword,FC_OP3);
 		InvalidateFlagsPartially((void*)&dynrec_dshl_dword_simple,proc_addr,t_DSHLd);
 	} else {
-		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshr_dword,FC_RETOP);
+		DRC_PTR_SIZE_IM proc_addr=gen_call_function_R3((void*)&dynrec_dshr_dword,FC_OP3);
 		InvalidateFlagsPartially((void*)&dynrec_dshr_dword_simple,proc_addr,t_DSHRd);
 	}
 }
diff --git a/src/cpu/core_dynrec/risc_armv4le-o3.h b/src/cpu/core_dynrec/risc_armv4le-o3.h
index 4b6916b8..9866a7fe 100644
--- a/src/cpu/core_dynrec/risc_armv4le-o3.h
+++ b/src/cpu/core_dynrec/risc_armv4le-o3.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_armv4le-o3.h,v 1.4 2009-05-16 21:52:47 c2woody Exp $ */
+/* $Id: risc_armv4le-o3.h,v 1.5 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* ARMv4 (little endian) backend by M-HT (size-tweaked arm version) */
@@ -39,6 +39,9 @@
 // register that holds the second parameter
 #define FC_OP2 HOST_a2
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_v2
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_a1
 
diff --git a/src/cpu/core_dynrec/risc_armv4le-s3.h b/src/cpu/core_dynrec/risc_armv4le-s3.h
index c2b7d582..d89ee13b 100644
--- a/src/cpu/core_dynrec/risc_armv4le-s3.h
+++ b/src/cpu/core_dynrec/risc_armv4le-s3.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_armv4le-s3.h,v 1.4 2009-05-16 21:52:47 c2woody Exp $ */
+/* $Id: risc_armv4le-s3.h,v 1.5 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* ARMv4 (little endian) backend by M-HT (speed-tweaked arm version) */
@@ -39,6 +39,9 @@
 // register that holds the second parameter
 #define FC_OP2 HOST_a2
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_v2
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_a1
 
diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h b/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h
index e4e0fe12..0a2f6631 100644
--- a/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h
+++ b/src/cpu/core_dynrec/risc_armv4le-thumb-iw.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_armv4le-thumb-iw.h,v 1.3 2009-05-16 21:52:47 c2woody Exp $ */
+/* $Id: risc_armv4le-thumb-iw.h,v 1.4 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* ARMv4 (little endian) backend by M-HT (thumb version with data pool, requires -mthumb-interwork switch when compiling dosbox) */
@@ -44,6 +44,9 @@
 // register that holds the second parameter
 #define FC_OP2 HOST_a2
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_a4
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_a1
 
diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h b/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h
index d8618f12..0c99cc3c 100644
--- a/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h
+++ b/src/cpu/core_dynrec/risc_armv4le-thumb-niw.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_armv4le-thumb-niw.h,v 1.3 2009-05-16 21:52:47 c2woody Exp $ */
+/* $Id: risc_armv4le-thumb-niw.h,v 1.4 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* ARMv4 (little endian) backend by M-HT (thumb version with data pool) */
@@ -44,6 +44,9 @@
 // register that holds the second parameter
 #define FC_OP2 HOST_a2
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_a4
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_a1
 
diff --git a/src/cpu/core_dynrec/risc_armv4le-thumb.h b/src/cpu/core_dynrec/risc_armv4le-thumb.h
index 58620574..37ae9c12 100644
--- a/src/cpu/core_dynrec/risc_armv4le-thumb.h
+++ b/src/cpu/core_dynrec/risc_armv4le-thumb.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_armv4le-thumb.h,v 1.4 2009-05-16 21:52:47 c2woody Exp $ */
+/* $Id: risc_armv4le-thumb.h,v 1.5 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* ARMv4 (little endian) backend by M-HT (thumb version) */
@@ -44,6 +44,9 @@
 // register that holds the second parameter
 #define FC_OP2 HOST_a2
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_a4
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_a1
 
diff --git a/src/cpu/core_dynrec/risc_mipsel32.h b/src/cpu/core_dynrec/risc_mipsel32.h
index b3da84e5..0da567a0 100644
--- a/src/cpu/core_dynrec/risc_mipsel32.h
+++ b/src/cpu/core_dynrec/risc_mipsel32.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_mipsel32.h,v 1.5 2009-05-27 09:15:41 qbix79 Exp $ */
+/* $Id: risc_mipsel32.h,v 1.6 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 /* MIPS32 (little endian) backend by crazyc */
@@ -74,6 +74,9 @@ typedef Bit8u HostReg;
 // register that holds the second parameter
 #define FC_OP2 HOST_a1
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_???
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_t5
 
diff --git a/src/cpu/core_dynrec/risc_x64.h b/src/cpu/core_dynrec/risc_x64.h
index 55000960..784b46f7 100644
--- a/src/cpu/core_dynrec/risc_x64.h
+++ b/src/cpu/core_dynrec/risc_x64.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_x64.h,v 1.12 2009-05-27 09:15:41 qbix79 Exp $ */
+/* $Id: risc_x64.h,v 1.13 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 // some configuring defines that specify the capabilities of this architecture
@@ -63,6 +63,9 @@ typedef Bit8u HostReg;
 // register that holds the second parameter
 #define FC_OP2 HOST_ESI
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_EAX
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_ECX
 
@@ -290,12 +293,11 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im
 		imm_size=4;	rm_base=0x80;			//Signed dword imm
 	}
 
-	// ea_reg := ea_reg+TEMP_REG_DRC*(2^scale)+imm
-	// ea_reg :=   op1 +   op2      *(2^scale)+imm
+	// ea_reg := ea_reg+scale_reg*(2^scale)+imm
 	cache_addb(0x48);
 	cache_addb(0x8d);			//LEA
 	cache_addb(0x04+(dest_reg << 3)+rm_base);	//The sib indicator
-	cache_addb(dest_reg+(TEMP_REG_DRC<<3)+(scale<<6));
+	cache_addb(dest_reg+(scale_reg<<3)+(scale<<6));
 
 	switch (imm_size) {
 	case 0:	break;
diff --git a/src/cpu/core_dynrec/risc_x86.h b/src/cpu/core_dynrec/risc_x86.h
index 3f2f9dba..e5aacb92 100644
--- a/src/cpu/core_dynrec/risc_x86.h
+++ b/src/cpu/core_dynrec/risc_x86.h
@@ -16,7 +16,7 @@
  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-/* $Id: risc_x86.h,v 1.9 2009-05-27 09:15:41 qbix79 Exp $ */
+/* $Id: risc_x86.h,v 1.10 2009-06-25 19:31:43 c2woody Exp $ */
 
 
 // some configuring defines that specify the capabilities of this architecture
@@ -70,6 +70,9 @@ enum HostReg {
 // register that holds the second parameter
 #define FC_OP2 HOST_EDX
 
+// special register that holds the third parameter for _R3 calls (byte accessible)
+#define FC_OP3 HOST_EAX
+
 // register that holds byte-accessible temporary values
 #define FC_TMP_BA1 HOST_ECX
 
@@ -267,11 +270,10 @@ static INLINE void gen_lea(HostReg dest_reg,HostReg scale_reg,Bitu scale,Bits im
 		imm_size=4;	rm_base=0x80;			//Signed dword imm
 	}
 
-	// ea_reg := ea_reg+TEMP_REG_DRC*(2^scale)+imm
-	// ea_reg :=   op1 +   op2      *(2^scale)+imm
+	// ea_reg := ea_reg+scale_reg*(2^scale)+imm
 	cache_addb(0x8d);			//LEA
 	cache_addb(0x04+(dest_reg << 3)+rm_base);	//The sib indicator
-	cache_addb(dest_reg+(TEMP_REG_DRC<<3)+(scale<<6));
+	cache_addb(dest_reg+(scale_reg<<3)+(scale<<6));
 
 	switch (imm_size) {
 	case 0:	break;
@@ -425,7 +427,9 @@ static void gen_fill_branch_long(Bit32u data) {
 static void gen_run_code(void) {
 	cache_addd(0x0424448b);		// mov eax,[esp+4]
 	cache_addb(0x53);			// push ebx
+	cache_addb(0x56);			// push esi
 	cache_addw(0xd0ff);			// call eax
+	cache_addb(0x5e);			// pop  esi
 	cache_addb(0x5b);			// pop  ebx
 }