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Added VERR and VERW

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@977
This commit is contained in:
Sjoerd van der Berg 2003-05-01 18:08:57 +00:00
parent 06ab2d99bb
commit 82c7fc4021
2 changed files with 63 additions and 2 deletions
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3
include/cpu.h
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@ -90,6 +90,9 @@ Bitu CPU_GET_CRX(Bitu cr);
void CPU_SMSW(Bitu & word);
bool CPU_LMSW(Bitu word);
void CPU_VERR(Bitu selector);
void CPU_VERW(Bitu selector);
bool CPU_JMP(bool use32,Bitu selector,Bitu offset);
bool CPU_CALL(bool use32,Bitu selector,Bitu offset);
bool CPU_RET(bool use32,Bitu bytes);

62
src/cpu/cpu.cpp
View file

@ -96,7 +96,7 @@ PhysPt SelBase(Bitu sel) {
bool CPU_CheckState(void) {
cpu.state=0;
if (!cpu.cr0 & CR0_PROTECTION) {
if (!(cpu.cr0 & CR0_PROTECTION)) {
cpu.full.entry=cpu.full.prefix=0;
return true;
} else {
@ -665,11 +665,69 @@ void CPU_LSL(Bitu selector,Bitu & limit) {
SETFLAGBIT(ZF,false);
return;
}
cpu.gdt.GetDescriptor(selector,desc);
limit=desc.GetLimit();
SETFLAGBIT(ZF,true);
}
void CPU_VERR(Bitu selector) {
Descriptor desc;Bitu rpl=selector & 3;
flags.type=t_UNKNOWN;
if (!cpu.gdt.GetDescriptor(selector,desc)){
SETFLAGBIT(ZF,false);
return;
}
if (!desc.saved.seg.p) {
SETFLAGBIT(ZF,false);
return;
}
switch (desc.Type()){
case DESC_CODE_R_C_A: case DESC_CODE_R_C_NA:
//Conforming readable code segments can be always read
break;
case DESC_DATA_EU_RO_NA: case DESC_DATA_EU_RO_A:
case DESC_DATA_EU_RW_NA: case DESC_DATA_EU_RW_A:
case DESC_DATA_ED_RO_NA: case DESC_DATA_ED_RO_A:
case DESC_DATA_ED_RW_NA: case DESC_DATA_ED_RW_A:
case DESC_CODE_R_NC_A: case DESC_CODE_R_NC_NA:
if (desc.DPL()<cpu.cpl || desc.DPL() < rpl) {
SETFLAGBIT(ZF,false);
return;
}
break;
default:
SETFLAGBIT(ZF,false);
return;
}
SETFLAGBIT(ZF,true);
}
void CPU_VERW(Bitu selector) {
Descriptor desc;Bitu rpl=selector & 3;
flags.type=t_UNKNOWN;
if (!cpu.gdt.GetDescriptor(selector,desc)){
SETFLAGBIT(ZF,false);
return;
}
if (!desc.saved.seg.p) {
SETFLAGBIT(ZF,false);
return;
}
switch (desc.Type()){
case DESC_DATA_EU_RW_NA: case DESC_DATA_EU_RW_A:
case DESC_DATA_ED_RW_NA: case DESC_DATA_ED_RW_A:
if (desc.DPL()<cpu.cpl || desc.DPL() < rpl) {
SETFLAGBIT(ZF,false);
return;
}
break;
default:
SETFLAGBIT(ZF,false);
return;
}
SETFLAGBIT(ZF,true);
}
bool CPU_SetSegGeneral(SegNames seg,Bitu value) {
Segs.val[seg]=value;