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Added EGA Register Interface Library - Write One Register (0xf1). Fixes colours in A-Train

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2197
This commit is contained in:
Peter Veenstra 2005-04-27 20:44:50 +00:00
parent 93a94c5b04
commit 881ae1b28f
3 changed files with 57 additions and 0 deletions
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3
src/ints/int10.cpp
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@ -432,6 +432,9 @@ graphics_chars:
reg_al=0x0;
}
break;
case 0xf1:
INT10_EGA_RIL_F1(reg_bl, reg_bh, reg_dx);
break;
case 0xff:
if (!warned_ff) LOG(LOG_INT10,LOG_NORMAL)("INT10:FF:Weird NC call");
warned_ff=true;

3
src/ints/int10.h
View file

@ -195,3 +195,6 @@ Bit8u VESA_GetPalette(PhysPt data,Bitu index,Bitu count);
/* Sup Groups */
void INT10_SetupRomMemory(void);
void INT10_SetupVESA(void);
/* EGA RIL */
void INT10_EGA_RIL_F1(Bit8u & bl, Bit8u bh, Bit16u dx);

51
src/ints/int10_misc.cpp
View file

@ -124,3 +124,54 @@ void INT10_GetFuncStateInformation(PhysPt save) {
mem_writeb(save+0x31,3);
}
static void EGA_RIL(Bit16u dx, Bitu& port, Bitu& regs) {
port = 0;
regs = 0; //if nul is returned it's a single register port
switch(dx) {
case 0x00: /* CRT Controller (25 reg) 3B4h mono modes, 3D4h color modes */
port = real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
regs = 25;
break;
case 0x08: /* Sequencer (5 registers) 3C4h */
port = 0x3C4;
regs = 5;
break;
case 0x10: /* Graphics Controller (9 registers) 3CEh */
port = 0x3CE;
regs = 9;
break;
case 0x18: /* Attribute Controller (20 registers) 3C0h */
port = 0x3c0;
regs = 20;
break;
case 0x20: /* Miscellaneous Output register 3C2h */
port = 0x3C2;
break;
case 0x28: /* Feature Control register (3BAh mono modes, 3DAh color modes) */
port = real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS) + 6;
break;
case 0x30: /* Graphics 1 Position register 3CCh */
port = 0x3CC;
break;
case 0x38: /* Graphics 2 Position register 3CAh */
port = 0x3CA;
break;
default:
LOG(LOG_INT10,LOG_ERROR)("unknown RIL port selection %X",dx);
break;
}
}
void INT10_EGA_RIL_F1(Bit8u & bl, Bit8u bh, Bit16u dx) {
Bitu port = 0;
Bitu regs = 0;
EGA_RIL(dx,port,regs);
if(regs == 0) {
IO_Write(port,bl);
} else {
IO_Write(port,bl);
IO_Write(port+1,bh);
bl = bh;//Not sure
LOG(LOG_INT10,LOG_NORMAL)("EGA RIL used with multi-reg");
}
}