diff --git a/src/hardware/vga_misc.cpp b/src/hardware/vga_misc.cpp
index c1d6f19e..3ca14fd7 100644
--- a/src/hardware/vga_misc.cpp
+++ b/src/hardware/vga_misc.cpp
@@ -24,7 +24,16 @@
 static Bit8u flip=0;
 static Bit32u keep_vretrace;
 static bool keeping=false;
-static Bit8u p3c2data;
+static Bit8u p3c2data=0;
+
+
+
+
+void write_p3d4(Bit32u port,Bit8u val);
+Bit8u read_p3d4(Bit32u port);
+void write_p3d5(Bit32u port,Bit8u val);
+Bit8u read_p3d5(Bit32u port);
+
 
 static Bit8u read_p3da(Bit32u port) {
 	vga.internal.attrindex=false;
@@ -45,26 +54,70 @@ static Bit8u read_p3da(Bit32u port) {
 		if (flip>5)	return 1;
 		return 0;
 	}
-};
+	/*
+		0	Either Vertical or Horizontal Retrace active if set
+		3	Vertical Retrace in progress if set
+	*/
+}
 
 
 static void write_p3d8(Bit32u port,Bit8u val) {
-	return;
+	/*
+		3	Vertical Sync Select. If set Vertical Sync to the monitor is the
+			logical OR of the vertical sync and the vertical display enable.
+	*/
 }
 
 static void write_p3c2(Bit32u port,Bit8u val) {
 	p3c2data=val;
+	if (val & 1) {
+		S_Warn("Color Mode %X",val);
+		IO_RegisterWriteHandler(0x3d4,write_p3d4,"VGA:CRTC Index Select");
+		IO_RegisterReadHandler(0x3d4,read_p3d4,"VGA:CRTC Index Select");
+		IO_RegisterWriteHandler(0x3d5,write_p3d5,"VGA:CRTC Data Register");
+		IO_RegisterReadHandler(0x3d5,read_p3d5,"VGA:CRTC Data Register");
+		IO_FreeWriteHandler(0x3b4);
+		IO_FreeReadHandler(0x3b4);
+		IO_FreeWriteHandler(0x3b5);
+		IO_FreeReadHandler(0x3b5);
+
+	} else {
+		S_Warn("Mono Mode %X",val);
+		IO_RegisterWriteHandler(0x3b4,write_p3d4,"VGA:CRTC Index Select");
+		IO_RegisterReadHandler(0x3b4,read_p3d4,"VGA:CRTC Index Select");
+		IO_RegisterWriteHandler(0x3b5,write_p3d5,"VGA:CRTC Data Register");
+		IO_RegisterReadHandler(0x3b5,read_p3d5,"VGA:CRTC Data Register");
+		IO_FreeWriteHandler(0x3d4);
+		IO_FreeReadHandler(0x3d4);
+		IO_FreeWriteHandler(0x3d5);
+		IO_FreeReadHandler(0x3d5);
+	}
+	/*
+		0	If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base Address=3Bxh.
+		2-3	Clock Select. 0: 25MHz, 1: 28MHz
+		5	When in Odd/Even modes Select High 64k bank if set
+		6	Horizontal Sync Polarity. Negative if set
+		7	Vertical Sync Polarity. Negative if set
+			Bit 6-7 indicates the number of lines on the display:
+			1:  400, 2: 350, 3: 480
+			Note: Set to all zero on a hardware reset.
+			Note: This register can be read from port 3CCh.
+	*/
 }
-static Bit8u read_p3c2(Bit32u port) {
+
+
+static Bit8u read_p3cc(Bit32u port) {
 	return p3c2data;
 }
 
 
 void VGA_SetupMisc(void) {
 	IO_RegisterReadHandler(0x3da,read_p3da,"VGA Input Status 1");
-//	IO_RegisterWriteHandler(0x3d8,write_p3d8,"VGA Mode Control");
+	IO_RegisterReadHandler(0x3ba,read_p3da,"VGA Input Status 1");
+
+	IO_RegisterWriteHandler(0x3d8,write_p3d8,"VGA Feature Control Register");
 	IO_RegisterWriteHandler(0x3c2,write_p3c2,"VGA Misc Output");
-	IO_RegisterReadHandler(0x3c2,read_p3c2,"VGA Misc Output");
+	IO_RegisterReadHandler(0x3cc,read_p3cc,"VGA Misc Output");
 }