New DMA routines
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1727
This commit is contained in:
Sjoerd van der Berg
parent
12e1f8a18b
commit
8b3fd8a4ae
2 changed files with 233 additions and 555 deletions
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@ -30,445 +30,226 @@
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DmaChannel *DmaChannels[8];
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DmaController *DmaControllers[2];
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Bit16u DmaController::portRead(Bit32u port, bool eightbit) {
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LOG_MSG("Reading DMA controller at %x", port);
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return 0xffff;
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static void DMA_WriteControllerReg(DmaController * cont,Bitu reg,Bitu val,Bitu len) {
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DmaChannel * chan;Bitu i;
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Bitu base=cont->chanbase;
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switch (reg) {
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan->baseaddr=(chan->baseaddr&0xff00)|val;
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chan->curraddr=(chan->curraddr&0xff00)|val;
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} else {
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chan->baseaddr=(chan->baseaddr&0x00ff)|(val << 8);
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chan->curraddr=(chan->curraddr&0x00ff)|(val << 8);
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}
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break;
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan->basecnt=(chan->basecnt&0xff00)|val;
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chan->currcnt=(chan->currcnt&0xff00)|val;
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} else {
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chan->basecnt=(chan->basecnt&0x00ff)|(val << 8);
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chan->currcnt=(chan->currcnt&0x00ff)|(val << 8);
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}
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break;
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case 0x8: /* Comand reg not used */
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break;
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case 0x9: /* Request registers, memory to memory */
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//TODO Warning?
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break;
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case 0xa: /* Mask Register */
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chan=DmaChannels[base+(val & 3 )];
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chan->SetMask((val & 0x4)>0);
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break;
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case 0xb: /* Mode Register */
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chan=DmaChannels[base+(val & 3 )];
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chan->autoinit=(val & 0x10) > 0;
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chan->increment=(val & 0x20) > 0;
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//TODO Maybe other bits?
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break;
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case 0xc: /* Clear Flip/Flip */
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cont->flipflop=false;
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break;
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case 0xd: /* Master Clear/Reset */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(true);
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DmaChannels[base+i]->tcount=false;
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}
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cont->flipflop=false;
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break;
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case 0xe: /* Clear Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(false);
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}
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break;
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case 0xf: /* Multiple Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(val & 1);
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val>>=1;
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}
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break;
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}
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}
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void DmaController::portWrite(Bit32u port, Bit16u val, bool eightbit) {
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bool found;
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found = false;
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if(port == ControllerPorts[ctrlnum][DMA_CLRMASKREG]) {
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found = true;
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flipflop = true;
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// Disable DMA requests
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// Clear command and status registers
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}
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if(port == ControllerPorts[ctrlnum][DMA_SINGLEREG]) {
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found = true;
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int dmachan;
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dmachan = (ctrlnum * 2) + (val & 0x3);
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DmaChannels[dmachan]->masked = ((val & 0x4) == 0x4);
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DmaChannels[dmachan]->Notify();
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}
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if(port == ControllerPorts[ctrlnum][DMA_WRITEALLREG]) {
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found = true;
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int dmachan,i,r;
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dmachan = (ctrlnum * 2);
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r = 0;
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for(i=dmachan;i<dmachan+4;i++) {
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DmaChannels[i]->masked = (((val >> r) & 0x1) == 0x1);
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DmaChannels[i]->Notify();
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r++;
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static Bitu DMA_ReadControllerReg(DmaController * cont,Bitu reg,Bitu len) {
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DmaChannel * chan;Bitu i,ret;
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Bitu base=cont->chanbase;
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switch (reg) {
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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return chan->curraddr & 0xff;
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} else {
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return (chan->curraddr >> 8) & 0xff;
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}
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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return chan->currcnt & 0xff;
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} else {
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return (chan->currcnt >> 8) & 0xff;
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}
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case 0x8:
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ret=0;
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for (i=0;i<4;i++) {
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chan=DmaChannels[base+i];
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if (chan->tcount) ret|=1 << i;
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chan->tcount=false;
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if (chan->callback) ret|=1 << (i+4);
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}
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return ret;
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default:
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LOG_MSG("Trying to read undefined DMA Red %x",reg);
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}
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if(port == ControllerPorts[ctrlnum][DMA_CLEARREG]) {
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found = true;
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flipflop = true;
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}
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if(port == ControllerPorts[ctrlnum][DMA_MODEREG]) {
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found = true;
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int dmachan;
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dmachan = (ctrlnum * 2) + (val & 0x3);
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DmaChannels[dmachan]->trantype = (val >> 2) & 0x3;
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DmaChannels[dmachan]->autoinit = ((val & 0x10) == 0x10);
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DmaChannels[dmachan]->dir = ((val & 0x20) == 0x20);
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DmaChannels[dmachan]->dmamode = (val >> 6) & 0x3;
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DmaChannels[dmachan]->Notify();
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}
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if(!found) LOG_MSG("Write to DMA port %x with %x", port, val);
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return 0xffffffff;
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}
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Bit32u DmaChannel::Read(Bit32s requestsize, Bit8u * buffer) {
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Bit32s bytesread;
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bytesread = 0;
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if(autoinit) {
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while(requestsize>0) {
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if(currcnt>=requestsize) {
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MEM_BlockRead(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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bytesread+=requestsize;
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requestsize=0;
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break;
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} else {
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MEM_BlockRead(curraddr,buffer,currcnt);
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bytesread+=currcnt;
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buffer+=currcnt;
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requestsize-=currcnt;
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reset();
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MakeCallback(true);
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}
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}
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if(currcnt==0) {
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reset();
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MakeCallback(true);
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}
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return bytesread;
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static void DMA_Write_PortB(Bit32u port,Bit8u val) {
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if (port<0x10) {
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DMA_WriteControllerReg(DmaControllers[0],port,val,1);
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} else if (port>=0xc0 && port <=0xdf) {
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DMA_WriteControllerReg(DmaControllers[1],(port-0xc0) >> 1,val,1);
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} else switch (port) {
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case 0x81:DmaChannels[2]->SetPage(val);break;
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case 0x82:DmaChannels[3]->SetPage(val);break;
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case 0x83:DmaChannels[1]->SetPage(val);break;
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case 0x89:DmaChannels[6]->SetPage(val);break;
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case 0x8a:DmaChannels[7]->SetPage(val);break;
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case 0x8b:DmaChannels[5]->SetPage(val);break;
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}
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}
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static Bit8u DMA_Read_PortB(Bit32u port) {
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if (port<0x10) {
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return DMA_ReadControllerReg(DmaControllers[0],port,1);
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} else if (port>=0xc0 && port <=0xdf) {
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return DMA_ReadControllerReg(DmaControllers[1],(port-0xc0) >> 1,1);
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}
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}
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DmaChannel::DmaChannel(Bit8u num, bool dma16) {
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masked = true;
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callback = NULL;
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if(num == 4) return;
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channum = num;
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DMA16 = dma16 ? 0x1 : 0x0;
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pagenum = 0;
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pagebase = 0;
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baseaddr = 0;
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curraddr = 0;
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basecnt = 0;
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currcnt = 0;
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increment = true;
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autoinit = false;
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tcount = false;
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}
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Bitu DmaChannel::Read(Bitu want, Bit8u * buffer) {
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Bitu done=0;
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again:
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Bitu left=(currcnt+1);
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if (want<left) {
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MEM_BlockRead(pagebase+(curraddr << DMA16),buffer,want << DMA16);
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done+=want;
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curraddr+=want;
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currcnt-=want;
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} else {
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if(currcnt>=requestsize) {
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MEM_BlockRead(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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bytesread+=requestsize;
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MEM_BlockRead(pagebase+(curraddr << DMA16),buffer,left << DMA16);
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buffer+=left << DMA16;
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want-=left;
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done+=left;
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ReachedTC();
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if (autoinit) {
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currcnt=basecnt;
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curraddr=baseaddr;
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if (want) goto again;
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} else {
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MEM_BlockRead(curraddr,buffer,currcnt);
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buffer+=currcnt;
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requestsize-=currcnt;
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bytesread+=currcnt;
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currcnt=0;
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curraddr+=left;
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currcnt=0xffff;
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SetMask(true);
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}
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}
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if(currcnt==0) MakeCallback(true);
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return bytesread;
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return done;
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}
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Bit32u DmaChannel::Write(Bit32s requestsize, Bit8u * buffer) {
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Bit32s byteswrite;
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byteswrite = 0;
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if(autoinit) {
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while(requestsize>0) {
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if(currcnt>=requestsize) {
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MEM_BlockWrite(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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byteswrite+=requestsize;
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requestsize=0;
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break;
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} else {
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MEM_BlockWrite(curraddr,buffer,currcnt);
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byteswrite+=currcnt;
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buffer+=currcnt;
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requestsize-=currcnt;
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reset();
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MakeCallback(true);
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}
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}
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if(currcnt==0) {
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reset();
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MakeCallback(true);
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}
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return byteswrite;
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Bitu DmaChannel::Write(Bitu want, Bit8u * buffer) {
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Bitu done=0;
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again:
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Bitu left=(currcnt+1);
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if (want<left) {
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MEM_BlockWrite(pagebase+(curraddr << DMA16),buffer,want << DMA16);
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done+=want;
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curraddr+=want;
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currcnt-=want;
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} else {
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if(currcnt>=requestsize) {
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MEM_BlockWrite(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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byteswrite+=requestsize;
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MEM_BlockWrite(pagebase+(curraddr << DMA16),buffer,left << DMA16);
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buffer+=left << DMA16;
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want-=left;
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done+=left;
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ReachedTC();
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if (autoinit) {
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currcnt=basecnt;
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curraddr=baseaddr;
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if (want) goto again;
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} else {
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MEM_BlockWrite(curraddr,buffer,currcnt);
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buffer+=currcnt;
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requestsize-=currcnt;
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byteswrite+=currcnt;
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currcnt=0;
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curraddr+=left;
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currcnt=0xffff;
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SetMask(true);
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}
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}
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if(currcnt==0) MakeCallback(true);
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return byteswrite;
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return done;
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}
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void DmaChannel::calcPhys(void) {
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if (DMA16) {
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physaddr = (baseaddr << 1) | ((pageaddr >> 1) << 17);
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} else {
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physaddr = (baseaddr) | (pageaddr << 16);
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}
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curraddr = physaddr;
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current_addr = baseaddr;
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}
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#define ff myController->flipflop
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Bit16u DmaChannel::portRead(Bit32u port, bool eightbit) {
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if (port == ChannelPorts[DMA_BASEADDR][channum]) {
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if(eightbit) {
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if(ff) {
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ff = !ff;
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return current_addr & 0xff;
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} else {
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ff = !ff;
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return current_addr >> 8;
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}
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} else {
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return current_addr;
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}
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}
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if (port == ChannelPorts[DMA_TRANSCOUNT][channum]) {
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if(eightbit) {
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if(ff) {
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ff = !ff;
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return (Bit8u)(currcnt-1);
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} else {
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ff = !ff;
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return (Bit8u)((currcnt-1) >> 8);
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}
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} else {
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return (Bit16u)currcnt;
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}
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}
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if (port == ChannelPorts[DMA_PAGEREG][channum]) return pageaddr;
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return 0xffff;
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}
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void DmaChannel::portWrite(Bit32u port, Bit16u val, bool eightbit) {
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if (port == ChannelPorts[DMA_BASEADDR][channum]) {
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if(eightbit) {
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if(ff) {
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baseaddr = (baseaddr & 0xff00) | (Bit8u)val;
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} else {
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baseaddr = (baseaddr & 0xff) | (val << 8);
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}
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ff = !ff;
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} else {
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baseaddr = val;
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}
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calcPhys();
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addr_changed = true;
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}
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if (port == ChannelPorts[DMA_TRANSCOUNT][channum]) {
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if(eightbit) {
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if(ff) {
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transcnt = (transcnt & 0xff00) | (Bit8u)val;
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} else {
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transcnt = (transcnt & 0xff) | (val << 8);
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}
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ff = !ff;
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} else {
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transcnt = val;
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}
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currcnt = transcnt+1;
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addr_changed = true;
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DMA_CheckEnabled(this);
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MakeCallback(false);
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}
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if (port == ChannelPorts[DMA_PAGEREG][channum]) {
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pageaddr = val;
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calcPhys();
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reset();
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}
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}
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#undef ff
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// Notify channel when mask changes
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void DmaChannel::Notify(void) {
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if(!masked) {
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DMA_CheckEnabled(this);
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MakeCallback(false);
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}
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}
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static Bit16u readDMAPorts(Bit32u port, bool eightbit) {
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int i,j;
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// Check for controller access
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for(i=0;i<2;i++) {
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for(j=0;j<7;j++) {
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if(ControllerPorts[i][j] == port) {
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return DmaControllers[i]->portRead(port, eightbit);
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}
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}
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}
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// Check for DMA access
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for(i=0;i<8;i++) {
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for(j=0;j<3;j++) {
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if(ChannelPorts[j][i] == port) {
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return DmaChannels[i]->portRead(port, eightbit);
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}
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}
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}
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LOG_MSG("Unmatched read port %x", port);
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return 0xffff;
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}
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static void writeDMAPorts(Bit32u port, Bit16u val, bool eightbit) {
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int i,j;
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// Check for controller access
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for(i=0;i<2;i++) {
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for(j=0;j<7;j++) {
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if(ControllerPorts[i][j] == port) {
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DmaControllers[i]->portWrite(port,val,eightbit);
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return;
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}
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}
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}
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// Check for DMA access
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for(i=0;i<8;i++) {
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for(j=0;j<3;j++) {
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if(ChannelPorts[j][i] == port) {
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DmaChannels[i]->portWrite(port,val,eightbit);
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return;
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}
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}
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}
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LOG_MSG("Unmatched write port %x - val %x", port, val);
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}
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Bit8u read_dmaB(Bit32u port) { return (Bit8u)readDMAPorts(port,true); }
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Bit16u read_dmaW(Bit32u port) { return readDMAPorts(port,false); }
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void write_dmaB(Bit32u port,Bit8u val) { writeDMAPorts(port,val,true); }
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void write_dmaW(Bit32u port,Bit16u val) { writeDMAPorts(port,val,false); }
|
||||
|
||||
|
||||
// Deprecated DMA read/write routines -- Keep compatibility with Sound Blaster
|
||||
Bitu DMA_8_Read(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
DmaChannel *chan=DmaChannels[dmachan];
|
||||
|
||||
if (chan->masked) return 0;
|
||||
if (!count) return 0;
|
||||
if (chan->addr_changed) chan->reset();
|
||||
|
||||
if (chan->currcnt>(Bits)count) {
|
||||
MEM_BlockRead(chan->curraddr,buffer,count);
|
||||
chan->curraddr+=count;
|
||||
chan->current_addr+=count;
|
||||
chan->currcnt-=count;
|
||||
return count;
|
||||
} else {
|
||||
// Copy remaining piece of first buffer
|
||||
MEM_BlockRead(chan->curraddr,buffer,chan->currcnt);
|
||||
if (!chan->autoinit) {
|
||||
// Set the end of counter bit
|
||||
//dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->currcnt;
|
||||
chan->curraddr+=count;
|
||||
chan->current_addr+=count;
|
||||
chan->currcnt=0;
|
||||
chan->enabled=false;
|
||||
LOG(LOG_DMA,LOG_NORMAL)("8-bit Channel %d reached terminal count",chan->channum);
|
||||
return count;
|
||||
} else {
|
||||
buffer+=chan->currcnt;
|
||||
Bitu left=count-(Bit16u)chan->currcnt;
|
||||
// Autoinit reset the dma channel
|
||||
chan->reset();
|
||||
// Copy the rest of the buffer
|
||||
MEM_BlockRead(chan->curraddr,buffer,left);
|
||||
chan->curraddr+=left;
|
||||
chan->current_addr+=left;
|
||||
chan->currcnt-=left;
|
||||
return count;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Bitu DMA_8_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
DmaChannel *chan=DmaChannels[dmachan];
|
||||
|
||||
if (chan->masked) return 0;
|
||||
if (!count) return 0;
|
||||
if (chan->currcnt>(Bits)count) {
|
||||
MEM_BlockWrite(chan->curraddr,buffer,count);
|
||||
chan->curraddr+=count;
|
||||
chan->currcnt-=count;
|
||||
return count;
|
||||
} else {
|
||||
// Copy remaining piece of first buffer
|
||||
MEM_BlockWrite(chan->curraddr,buffer,chan->currcnt);
|
||||
if (!chan->autoinit) {
|
||||
// Set the end of counter bit
|
||||
//dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->currcnt;
|
||||
chan->curraddr+=count;;
|
||||
chan->currcnt=0;
|
||||
return count;
|
||||
} else {
|
||||
buffer+=chan->currcnt;
|
||||
Bitu left=count-(Bit16u)chan->currcnt;
|
||||
// Autoinit reset the dma channel
|
||||
chan->reset();
|
||||
// Copy the rest of the buffer
|
||||
MEM_BlockWrite(chan->curraddr,buffer,left);
|
||||
chan->curraddr+=left;
|
||||
chan->currcnt-=left;
|
||||
return count;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Bitu DMA_16_Read(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Bitu DMA_16_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void DMA_SetEnabled(void * usechan,bool enabled) {
|
||||
DmaChannel * chan;
|
||||
chan = (DmaChannel *)usechan;
|
||||
|
||||
if (chan->enabled == enabled) return;
|
||||
chan->enabled=enabled;
|
||||
if (chan->enable_callback) (*chan->enable_callback)(enabled);
|
||||
}
|
||||
|
||||
void DMA_CheckEnabled(void * usechan) {
|
||||
DmaChannel * chan;
|
||||
chan = (DmaChannel *)usechan;
|
||||
|
||||
bool enabled;
|
||||
if (chan->masked) enabled=false;
|
||||
else {
|
||||
if (chan->autoinit) enabled=true;
|
||||
else if (chan->currcnt) enabled=true;
|
||||
else enabled=false;
|
||||
}
|
||||
DMA_SetEnabled(chan,enabled);
|
||||
}
|
||||
|
||||
|
||||
void DMA_SetEnableCallBack(Bitu channel,DMA_EnableCallBack callback) {
|
||||
DmaChannel * chan;
|
||||
chan = DmaChannels[channel];
|
||||
chan->enabled=false;
|
||||
chan->enable_callback=callback;
|
||||
DMA_CheckEnabled(chan);
|
||||
}
|
||||
|
||||
|
||||
void DMA_Init(Section* sec) {
|
||||
|
||||
Bitu i;
|
||||
|
||||
DmaControllers[0] = new DmaController(0);
|
||||
DmaControllers[1] = new DmaController(1);
|
||||
|
||||
for(i=0;i<4;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[0],false);
|
||||
for(i=0;i<8;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,i>=4);
|
||||
}
|
||||
for(i=4;i<8;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[1],true);
|
||||
for (i=0;i<0x10;i++) {
|
||||
IO_RegisterWriteBHandler(i,DMA_Write_PortB);
|
||||
IO_RegisterReadBHandler(i,DMA_Read_PortB);
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteBHandler(0xc0+i*2,DMA_Write_PortB);
|
||||
IO_RegisterReadBHandler(0xc0+i*2,DMA_Read_PortB);
|
||||
}
|
||||
}
|
||||
IO_RegisterWriteBHandler(0x81,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x82,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x83,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x89,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x8a,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x8b,DMA_Write_PortB);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue