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Refinements of commit 4291, so that precission can be specified as well and less fixed defines are used

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@4292
This commit is contained in:
Peter Veenstra 2019-11-19 16:16:06 +00:00
parent 01fe58047e
commit 8cb2e08f31
5 changed files with 30 additions and 28 deletions
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10
src/hardware/dma.cpp
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@ -50,7 +50,7 @@ static void DMA_BlockRead(PhysPt spage,PhysPt offset,void * data,Bitu size,Bit8u
Bit32u dma_wrap = ((0xffff<<dma16)+dma16) | dma_wrapping;
for ( ; size ; size--, offset++) {
if (offset>(dma_wrapping<<dma16)) {
LOG_MSG("DMA segbound wrapping (read): %x:%x size " sBitux " [%x] wrap %x",spage,offset,size,dma16,dma_wrapping);
LOG_MSG("DMA segbound wrapping (read): %x:%x size %" sBitfs(x) " [%x] wrap %x",spage,offset,size,dma16,dma_wrapping);
}
offset &= dma_wrap;
Bitu page = highpart_addr_page+(offset >> 12);
@ -71,7 +71,7 @@ static void DMA_BlockWrite(PhysPt spage,PhysPt offset,void * data,Bitu size,Bit8
Bit32u dma_wrap = ((0xffff<<dma16)+dma16) | dma_wrapping;
for ( ; size ; size--, offset++) {
if (offset>(dma_wrapping<<dma16)) {
LOG_MSG("DMA segbound wrapping (write): %x:%x size " sBitux " [%x] wrap %x",spage,offset,size,dma16,dma_wrapping);
LOG_MSG("DMA segbound wrapping (write): %x:%x size %" sBitfs(x) " [%x] wrap %x",spage,offset,size,dma16,dma_wrapping);
}
offset &= dma_wrap;
Bitu page = highpart_addr_page+(offset >> 12);
@ -109,7 +109,7 @@ bool SecondDMAControllerAvailable(void) {
}
static void DMA_Write_Port(Bitu port,Bitu val,Bitu /*iolen*/) {
//LOG(LOG_DMACONTROL,LOG_ERROR)("Write " sBituX " " sBituX,port,val);
//LOG(LOG_DMACONTROL,LOG_ERROR)("Write %" sBitfs(X) " %" sBitfs(X),port,val);
if (port<0x10) {
/* write to the first DMA controller (channels 0-3) */
DmaControllers[0]->WriteControllerReg(port,val,1);
@ -132,7 +132,7 @@ static void DMA_Write_Port(Bitu port,Bitu val,Bitu /*iolen*/) {
}
static Bitu DMA_Read_Port(Bitu port,Bitu iolen) {
//LOG(LOG_DMACONTROL,LOG_ERROR)("Read " sBituX,port);
//LOG(LOG_DMACONTROL,LOG_ERROR)("Read %" sBitfs(X),port);
if (port<0x10) {
/* read from the first DMA controller (channels 0-3) */
return DmaControllers[0]->ReadControllerReg(port,iolen);
@ -258,7 +258,7 @@ Bitu DmaController::ReadControllerReg(Bitu reg,Bitu /*len*/) {
}
return ret;
default:
LOG(LOG_DMACONTROL,LOG_NORMAL)("Trying to read undefined DMA port " sBitux,reg);
LOG(LOG_DMACONTROL,LOG_NORMAL)("Trying to read undefined DMA port %" sBitfs(x),reg);
break;
}
return 0xffffffff;