ignore unneeded fpu-exception flags
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2425
This commit is contained in:
Sebastian Strohhäcker
parent
17ea37fe89
commit
8faeb470b4
1 changed files with 281 additions and 85 deletions
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@ -16,11 +16,31 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: fpu_instructions_x86.h,v 1.1 2005-02-22 13:06:06 qbix79 Exp $ */
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/* $Id: fpu_instructions_x86.h,v 1.2 2006-01-08 18:05:06 c2woody Exp $ */
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#define WEAK_EXCEPTIONS
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#if defined (_MSC_VER)
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#ifdef WEAK_EXCEPTIONS
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#define clx
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#else
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#define clx fclex
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#endif
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#ifdef WEAK_EXCEPTIONS
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#define FPUD_LOAD(op,szI,szA) \
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__asm { \
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__asm mov eax, 8 \
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__asm shl eax, 4 \
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__asm mov ebx, store_to \
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__asm shl ebx, 4 \
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__asm op szI PTR fpu.p_regs[eax].m1 \
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__asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
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}
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#else
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#define FPUD_LOAD(op,szI,szA) \
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Bit16u new_sw; \
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__asm { \
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@ -34,6 +54,7 @@
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__asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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#endif
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#define FPUD_STORE(op,szI,szA) \
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Bit16u new_sw,save_cw; \
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@ -45,12 +66,12 @@
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__asm mov ebx, 8 \
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__asm shl ebx, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm op szI PTR fpu.p_regs[ebx].m1 \
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__asm fnstsw new_sw \
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__asm fldcw save_cw \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fsin,fcos,f2xm1,fchs,fabs
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#define FPUD_TRIG(op) \
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@ -59,15 +80,15 @@
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__asm mov eax, TOP \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fsincos
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#define FPUD_SINCOS \
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#define FPUD_SINCOS() \
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Bit16u new_sw; \
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__asm { \
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__asm mov eax, TOP \
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@ -77,7 +98,7 @@
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__asm shl eax, 4 \
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__asm shl ebx, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm fsincos \
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__asm fnstsw new_sw \
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__asm mov cx, new_sw \
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@ -90,11 +111,11 @@
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__asm fstp st(0) \
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__asm end_sincos: \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
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if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
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// handles fptan
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#define FPUD_PTAN \
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#define FPUD_PTAN() \
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Bit16u new_sw; \
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__asm { \
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__asm mov eax, TOP \
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@ -104,7 +125,7 @@
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__asm shl eax, 4 \
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__asm shl ebx, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm fptan \
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__asm fnstsw new_sw \
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__asm mov cx, new_sw \
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@ -117,10 +138,26 @@
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__asm fstp st(0) \
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__asm end_ptan: \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
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if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
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// handles fxtract
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#ifdef WEAK_EXCEPTIONS
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#define FPUD_XTRACT \
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__asm { \
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__asm mov eax, TOP \
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__asm mov ebx, eax \
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__asm dec ebx \
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__asm and ebx, 7 \
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__asm shl eax, 4 \
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__asm shl ebx, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fxtract \
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__asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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} \
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FPU_PREP_PUSH();
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#else
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#define FPUD_XTRACT \
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Bit16u new_sw; \
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__asm { \
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@ -139,9 +176,47 @@
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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FPU_PREP_PUSH();
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#endif
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// handles fadd,fmul,fsub,fsubr,fdiv,fdivr
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// handles fadd,fmul,fsub,fsubr
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#define FPUD_ARITH1(op) \
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Bit16u new_sw,save_cw; \
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__asm { \
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__asm fnstcw save_cw \
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__asm fldcw fpu.cw_mask_all \
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__asm mov eax, op1 \
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__asm shl eax, 4 \
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__asm mov ebx, op2 \
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__asm shl ebx, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
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__asm clx \
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__asm op st(1), st(0) \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fldcw save_cw \
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} \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fsqrt,frndint
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#define FPUD_ARITH2(op) \
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Bit16u new_sw,save_cw; \
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__asm { \
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__asm fnstcw save_cw \
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__asm fldcw fpu.cw_mask_all \
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__asm mov eax, TOP \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm clx \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fldcw save_cw \
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} \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fdiv,fdivr
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#define FPUD_ARITH3(op) \
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Bit16u new_sw,save_cw; \
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__asm { \
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__asm fnstcw save_cw \
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@ -160,23 +235,6 @@
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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// handles fsqrt,frndint
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#define FPUD_ARITH2(op) \
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Bit16u new_sw,save_cw; \
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__asm { \
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__asm fnstcw save_cw \
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__asm fldcw fpu.cw_mask_all \
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__asm mov eax, TOP \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fldcw save_cw \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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// handles fprem,fprem1,fscale
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#define FPUD_REMINDER(op) \
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Bit16u new_sw; \
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@ -207,11 +265,11 @@
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm op \
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__asm fnstsw new_sw \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fxam,ftst
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#define FPUD_EXAMINE(op) \
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@ -220,15 +278,52 @@
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__asm mov eax, TOP \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm clx \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp st(0) \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fpatan,fyl2x,fyl2xp1
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// handles fpatan,fyl2xp1
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#ifdef WEAK_EXCEPTIONS
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#define FPUD_WITH_POP(op) \
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__asm { \
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__asm mov eax, TOP \
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__asm mov ebx, eax \
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__asm inc ebx \
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__asm and ebx, 7 \
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__asm shl ebx, 4 \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm op \
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__asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
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} \
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FPU_FPOP();
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#else
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#define FPUD_WITH_POP(op) \
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Bit16u new_sw; \
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__asm { \
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__asm mov eax, TOP \
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__asm mov ebx, eax \
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__asm inc ebx \
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__asm and ebx, 7 \
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__asm shl ebx, 4 \
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__asm shl eax, 4 \
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__asm fld TBYTE PTR fpu.p_regs[ebx].m1 \
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__asm fld TBYTE PTR fpu.p_regs[eax].m1 \
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__asm fclex \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[ebx].m1 \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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FPU_FPOP();
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#endif
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// handles fyl2x
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#define FPUD_FYL2X(op) \
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Bit16u new_sw; \
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__asm { \
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__asm mov eax, TOP \
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@ -248,21 +343,37 @@
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FPU_FPOP();
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// load math constants
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#define FPUD_LOAD_CONST(op) \
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Bit16u new_sw; \
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#define FPUD_LOAD_CONST(op) \
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FPU_PREP_PUSH(); \
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__asm { \
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__asm mov eax, TOP \
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__asm shl eax, 4 \
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__asm fclex \
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__asm clx \
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__asm op \
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__asm fnstsw new_sw \
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__asm fstp TBYTE PTR fpu.p_regs[eax].m1 \
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} \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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#else
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#ifdef WEAK_EXCEPTIONS
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#define clx
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#else
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#define clx "fclex"
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#endif
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#ifdef WEAK_EXCEPTIONS
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#define FPUD_LOAD(op,szI,szA) \
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__asm__ volatile ( \
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"movl $8, %%eax \n" \
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"shl $4, %%eax \n" \
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"shl $4, %0 \n" \
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#op #szA " (%1, %%eax) \n" \
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"fstpt (%1, %0) " \
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: \
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: "r" (store_to), "r" (fpu.p_regs) \
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: "eax", "memory" \
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);
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#else
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#define FPUD_LOAD(op,szI,szA) \
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Bit16u new_sw; \
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__asm__ volatile ( \
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@ -278,6 +389,7 @@
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: "eax", "memory" \
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); \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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#endif
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#define FPUD_STORE(op,szI,szA) \
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Bit16u new_sw,save_cw; \
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@ -288,7 +400,7 @@
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"movl $8, %%eax \n" \
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"shl $4, %%eax \n" \
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"fldt (%3, %2) \n" \
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"fclex \n" \
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clx" \n" \
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#op #szA " (%3, %%eax) \n" \
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"fnstsw %0 \n" \
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"fldcw %1 " \
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@ -296,7 +408,7 @@
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: "r" (TOP), "r" (fpu.p_regs), "m" (fpu.cw_mask_all) \
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: "eax", "memory" \
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); \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fsin,fcos,f2xm1,fchs,fabs
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#define FPUD_TRIG(op) \
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@ -304,7 +416,7 @@
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__asm__ volatile ( \
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"shll $4, %1 \n" \
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"fldt (%2, %1) \n" \
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"fclex \n" \
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clx" \n" \
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#op" \n" \
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"fnstsw %0 \n" \
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"fstpt (%2, %1) " \
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@ -312,10 +424,10 @@
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: "r" (TOP), "r" (fpu.p_regs) \
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: "memory" \
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); \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
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// handles fsincos
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#define FPUD_SINCOS \
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#define FPUD_SINCOS() \
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Bit16u new_sw; \
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__asm__ volatile ( \
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"movl %1, %%eax \n" \
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@ -324,7 +436,7 @@
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"andl $7, %%eax \n" \
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"shll $4, %%eax \n" \
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"fldt (%2, %1) \n" \
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"fclex \n" \
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clx" \n" \
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"fsincos \n" \
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"fnstsw %0 \n" \
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"fstpt (%2, %%eax) \n" \
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@ -337,11 +449,11 @@
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: "r" (TOP), "r" (fpu.p_regs) \
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: "eax", "cc", "memory" \
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); \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
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if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
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// handles fptan
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#define FPUD_PTAN \
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#define FPUD_PTAN() \
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Bit16u new_sw; \
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__asm__ volatile ( \
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"movl %1, %%eax \n" \
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@ -350,7 +462,7 @@
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"andl $7, %%eax \n" \
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"shll $4, %%eax \n" \
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"fldt (%2, %1) \n" \
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"fclex \n" \
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clx" \n" \
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"fptan \n" \
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"fnstsw %0 \n" \
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"fstpt (%2, %%eax) \n" \
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@ -363,10 +475,28 @@
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: "r" (TOP), "r" (fpu.p_regs) \
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: "eax", "cc", "memory" \
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); \
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fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
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fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff); \
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if ((new_sw&0x0400)==0) FPU_PREP_PUSH();
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// handles fxtract
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#ifdef WEAK_EXCEPTIONS
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#define FPUD_XTRACT \
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__asm__ volatile ( \
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"movl %0, %%eax \n" \
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"shll $4, %0 \n" \
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"decl %%eax \n" \
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"andl $7, %%eax \n" \
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"shll $4, %%eax \n" \
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"fldt (%1, %0) \n" \
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"fxtract \n" \
|
||||
"fstpt (%1, %%eax) \n" \
|
||||
"fstpt (%1, %0) " \
|
||||
: \
|
||||
: "r" (TOP), "r" (fpu.p_regs) \
|
||||
: "eax", "memory" \
|
||||
); \
|
||||
FPU_PREP_PUSH();
|
||||
#else
|
||||
#define FPUD_XTRACT \
|
||||
Bit16u new_sw; \
|
||||
__asm__ volatile ( \
|
||||
|
|
@ -387,9 +517,50 @@
|
|||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
|
||||
FPU_PREP_PUSH();
|
||||
#endif
|
||||
|
||||
// handles fadd,fmul,fsub,fsubr,fdiv,fdivr
|
||||
// handles fadd,fmul,fsub,fsubr
|
||||
#define FPUD_ARITH1(op) \
|
||||
Bit16u new_sw,save_cw; \
|
||||
__asm__ volatile ( \
|
||||
"fnstcw %1 \n" \
|
||||
"fldcw %5 \n" \
|
||||
"shll $4, %3 \n" \
|
||||
"shll $4, %2 \n" \
|
||||
"fldt (%4, %3) \n" \
|
||||
"fldt (%4, %2) \n" \
|
||||
clx" \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 \n" \
|
||||
"fstpt (%4, %2) \n" \
|
||||
"fldcw %1 " \
|
||||
: "=m" (new_sw), "=m" (save_cw) \
|
||||
: "r" (op1), "r" (op2), "r" (fpu.p_regs), "m" (fpu.cw_mask_all) \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fsqrt,frndint
|
||||
#define FPUD_ARITH2(op) \
|
||||
Bit16u new_sw,save_cw; \
|
||||
__asm__ volatile ( \
|
||||
"fnstcw %1 \n" \
|
||||
"fldcw %4 \n" \
|
||||
"shll $4, %2 \n" \
|
||||
"fldt (%3, %2) \n" \
|
||||
clx" \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 \n" \
|
||||
"fstpt (%3, %2) \n" \
|
||||
"fldcw %1 " \
|
||||
: "=m" (new_sw), "=m" (save_cw) \
|
||||
: "r" (TOP), "r" (fpu.p_regs), "m" (fpu.cw_mask_all) \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fdiv,fdivr
|
||||
#define FPUD_ARITH3(op) \
|
||||
Bit16u new_sw,save_cw; \
|
||||
__asm__ volatile ( \
|
||||
"fnstcw %1 \n" \
|
||||
|
|
@ -405,29 +576,10 @@
|
|||
"fldcw %1 " \
|
||||
: "=m" (new_sw), "=m" (save_cw) \
|
||||
: "r" (op1), "r" (op2), "r" (fpu.p_regs), "m" (fpu.cw_mask_all) \
|
||||
: "memory" \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fsqrt,frndint
|
||||
#define FPUD_ARITH2(op) \
|
||||
Bit16u new_sw,save_cw; \
|
||||
__asm__ volatile ( \
|
||||
"fnstcw %1 \n" \
|
||||
"fldcw %4 \n" \
|
||||
"shll $4, %2 \n" \
|
||||
"fldt (%3, %2) \n" \
|
||||
"fclex \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 \n" \
|
||||
"fstpt (%3, %2) \n" \
|
||||
"fldcw %1 " \
|
||||
: "=m" (new_sw), "=m" (save_cw) \
|
||||
: "r" (TOP), "r" (fpu.p_regs), "m" (fpu.cw_mask_all) \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fprem,fprem1,fscale
|
||||
#define FPUD_REMINDER(op) \
|
||||
Bit16u new_sw; \
|
||||
|
|
@ -458,14 +610,14 @@
|
|||
"shll $4, %1 \n" \
|
||||
"fldt (%3, %2) \n" \
|
||||
"fldt (%3, %1) \n" \
|
||||
"fclex \n" \
|
||||
clx" \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 " \
|
||||
: "=m" (new_sw) \
|
||||
: "r" (op1), "r" (op2), "r" (fpu.p_regs) \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
|
||||
fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fxam,ftst
|
||||
#define FPUD_EXAMINE(op) \
|
||||
|
|
@ -473,7 +625,7 @@
|
|||
__asm__ volatile ( \
|
||||
"shll $4, %1 \n" \
|
||||
"fldt (%2, %1) \n" \
|
||||
"fclex \n" \
|
||||
clx" \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 \n" \
|
||||
"fstp %%st(0) " \
|
||||
|
|
@ -481,9 +633,27 @@
|
|||
: "r" (TOP), "r" (fpu.p_regs) \
|
||||
: "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff);
|
||||
fpu.sw=(new_sw&exc_mask)|(fpu.sw&0x80ff);
|
||||
|
||||
// handles fpatan,fyl2x,fyl2xp1
|
||||
// handles fpatan,fyl2xp1
|
||||
#ifdef WEAK_EXCEPTIONS
|
||||
#define FPUD_WITH_POP(op) \
|
||||
__asm__ volatile ( \
|
||||
"movl %0, %%eax \n" \
|
||||
"incl %%eax \n" \
|
||||
"andl $7, %%eax \n" \
|
||||
"shll $4, %%eax \n" \
|
||||
"shll $4, %0 \n" \
|
||||
"fldt (%1, %%eax) \n" \
|
||||
"fldt (%1, %0) \n" \
|
||||
#op" \n" \
|
||||
"fstpt (%1, %%eax) \n" \
|
||||
: \
|
||||
: "r" (TOP), "r" (fpu.p_regs) \
|
||||
: "eax", "memory" \
|
||||
); \
|
||||
FPU_FPOP();
|
||||
#else
|
||||
#define FPUD_WITH_POP(op) \
|
||||
Bit16u new_sw; \
|
||||
__asm__ volatile ( \
|
||||
|
|
@ -504,23 +674,49 @@
|
|||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
|
||||
FPU_FPOP();
|
||||
#endif
|
||||
|
||||
// load math constants
|
||||
#define FPUD_LOAD_CONST(op) \
|
||||
// handles fyl2x
|
||||
#define FPUD_FYL2X(op) \
|
||||
Bit16u new_sw; \
|
||||
FPU_PREP_PUSH(); \
|
||||
__asm__ volatile ( \
|
||||
"movl %1, %%eax \n" \
|
||||
"incl %%eax \n" \
|
||||
"andl $7, %%eax \n" \
|
||||
"shll $4, %%eax \n" \
|
||||
"shll $4, %1 \n" \
|
||||
"fldt (%2, %%eax) \n" \
|
||||
"fldt (%2, %1) \n" \
|
||||
"fclex \n" \
|
||||
#op" \n" \
|
||||
"fnstsw %0 \n" \
|
||||
"fstpt (%2, %1) \n" \
|
||||
"fstpt (%2, %%eax) \n" \
|
||||
: "=m" (new_sw) \
|
||||
: "r" (TOP), "r" (fpu.p_regs) \
|
||||
: "memory" \
|
||||
: "eax", "memory" \
|
||||
); \
|
||||
fpu.sw=(new_sw&0xffbf)|(fpu.sw&0x80ff); \
|
||||
FPU_FPOP();
|
||||
|
||||
// load math constants
|
||||
#define FPUD_LOAD_CONST(op) \
|
||||
FPU_PREP_PUSH(); \
|
||||
__asm__ volatile ( \
|
||||
"shll $4, %0 \n" \
|
||||
clx" \n" \
|
||||
#op" \n" \
|
||||
"fstpt (%1, %0) \n" \
|
||||
: \
|
||||
: "r" (TOP), "r" (fpu.p_regs) \
|
||||
: "memory" \
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef WEAK_EXCEPTIONS
|
||||
const Bit16u exc_mask=0x7f00;
|
||||
#else
|
||||
const Bit16u exc_mask=0xffbf;
|
||||
#endif
|
||||
|
||||
static void FPU_FINIT(void) {
|
||||
|
|
@ -643,7 +839,7 @@ static void FPU_FSIN(void){
|
|||
}
|
||||
|
||||
static void FPU_FSINCOS(void){
|
||||
FPUD_SINCOS
|
||||
FPUD_SINCOS()
|
||||
}
|
||||
|
||||
static void FPU_FCOS(void){
|
||||
|
|
@ -659,7 +855,7 @@ static void FPU_FPATAN(void){
|
|||
}
|
||||
|
||||
static void FPU_FPTAN(void){
|
||||
FPUD_PTAN
|
||||
FPUD_PTAN()
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -668,11 +864,11 @@ static void FPU_FADD(Bitu op1, Bitu op2){
|
|||
}
|
||||
|
||||
static void FPU_FDIV(Bitu op1, Bitu op2){
|
||||
FPUD_ARITH1(fdivp)
|
||||
FPUD_ARITH3(fdivp)
|
||||
}
|
||||
|
||||
static void FPU_FDIVR(Bitu op1, Bitu op2){
|
||||
FPUD_ARITH1(fdivrp)
|
||||
FPUD_ARITH3(fdivrp)
|
||||
}
|
||||
|
||||
static void FPU_FMUL(Bitu op1, Bitu op2){
|
||||
|
|
@ -750,7 +946,7 @@ static void FPU_F2XM1(void){
|
|||
}
|
||||
|
||||
static void FPU_FYL2X(void){
|
||||
FPUD_WITH_POP(fyl2x)
|
||||
FPUD_FYL2X(fyl2x)
|
||||
}
|
||||
|
||||
static void FPU_FYL2XP1(void){
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue