add video state functionality
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2996
This commit is contained in:
Sebastian Strohhäcker
parent
d64648208a
commit
9c45a245e8
5 changed files with 439 additions and 5 deletions
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@ -3,5 +3,5 @@ AM_CPPFLAGS = -I$(top_srcdir)/include
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noinst_LIBRARIES = libints.a
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libints_a_SOURCES = mouse.cpp xms.cpp xms.h ems.cpp \
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int10.cpp int10.h int10_char.cpp int10_memory.cpp int10_misc.cpp int10_modes.cpp \
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int10_vesa.cpp int10_pal.cpp int10_put_pixel.cpp \
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bios.cpp bios_disk.cpp bios_keyboard.cpp
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int10_vesa.cpp int10_pal.cpp int10_put_pixel.cpp int10_video_state.cpp \
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bios.cpp bios_disk.cpp bios_keyboard.cpp
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@ -424,9 +424,29 @@ graphics_chars:
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}
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break;
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case 0x1C: /* Video Save Area */
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if (IS_VGA_ARCH) break;
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if (reg_al==0) reg_bx = 0;
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reg_al = 0x1C;
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if (!IS_VGA_ARCH) break;
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switch (reg_al) {
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case 0: {
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Bitu ret=INT10_VideoState_GetSize(reg_cx);
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if (ret) {
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reg_al=0x1c;
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reg_bx=ret;
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} else reg_al=0;
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}
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break;
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case 1:
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if (INT10_VideoState_Save(reg_cx,RealMake(SegValue(es),reg_bx))) reg_al=0x1c;
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else reg_al=0;
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break;
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case 2:
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if (INT10_VideoState_Restore(reg_cx,RealMake(SegValue(es),reg_bx))) reg_al=0x1c;
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else reg_al=0;
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break;
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default:
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if (svgaCard==SVGA_TsengET4K) reg_ax=0;
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else reg_al=0;
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break;
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}
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break;
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case 0x4f: /* VESA Calls */
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if ((!IS_VGA_ARCH) || (svgaCard==SVGA_None)) break;
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@ -447,6 +467,30 @@ graphics_chars:
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reg_al=0x4f;
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reg_ah=VESA_GetSVGAMode(reg_bx);
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break;
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case 0x04: /* Save/restore state */
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reg_al=0x4f;
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switch (reg_dl) {
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case 0: {
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Bitu ret=INT10_VideoState_GetSize(reg_cx);
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if (ret) {
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reg_ah=0;
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reg_bx=ret;
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} else reg_ah=1;
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}
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break;
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case 1:
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if (INT10_VideoState_Save(reg_cx,RealMake(SegValue(es),reg_bx))) reg_ah=0;
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else reg_ah=1;
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break;
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case 2:
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if (INT10_VideoState_Restore(reg_cx,RealMake(SegValue(es),reg_bx))) reg_ah=0;
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else reg_ah=1;
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break;
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default:
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reg_ah=1;
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break;
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}
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break;
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case 0x05:
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if (reg_bh==0) { /* Set CPU Window */
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reg_ah=VESA_SetCPUWindow(reg_bl,reg_dl);
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@ -212,3 +212,8 @@ void INT10_EGA_RIL_ReadRegisterRange(Bit8u & bl, Bit8u ch, Bit8u cl, Bit16u dx,
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void INT10_EGA_RIL_WriteRegisterRange(Bit8u & bl, Bit8u ch, Bit8u cl, Bit16u dx, PhysPt dst);
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void INT10_EGA_RIL_ReadRegisterSet(Bit16u cx, PhysPt tbl);
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void INT10_EGA_RIL_WriteRegisterSet(Bit16u cx, PhysPt tbl);
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/* Video State */
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Bitu INT10_VideoState_GetSize(Bitu state);
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bool INT10_VideoState_Save(Bitu state,RealPt buffer);
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bool INT10_VideoState_Restore(Bitu state,RealPt buffer);
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382
src/ints/int10_video_state.cpp
Normal file
382
src/ints/int10_video_state.cpp
Normal file
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@ -0,0 +1,382 @@
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/*
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* Copyright (C) 2002-2007 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: */
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#include "dosbox.h"
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#include "mem.h"
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#include "inout.h"
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#include "int10.h"
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Bitu INT10_VideoState_GetSize(Bitu state) {
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// state: bit0=hardware, bit1=bios data, bit2=color regs/dac state
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if ((state&7)==0) return 0;
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Bitu size=0x20;
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if (state&1) size+=0x46;
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if (state&2) size+=0x3a;
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if (state&4) size+=0x303;
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if ((svgaCard==SVGA_S3Trio) && (state&8)) size+=0x43;
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if (size!=0) size=(size-1)/64+1;
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return size;
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}
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bool INT10_VideoState_Save(Bitu state,RealPt buffer) {
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Bitu ct;
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if ((state&7)==0) return false;
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Bitu base_seg=RealSeg(buffer);
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Bitu base_dest=RealOff(buffer)+0x20;
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if (state&1) {
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real_writew(base_seg,RealOff(buffer),base_dest);
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Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
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real_writew(base_seg,base_dest+0x40,crt_reg);
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real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c4));
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real_writeb(base_seg,base_dest+0x01,IO_ReadB(0x3d4));
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real_writeb(base_seg,base_dest+0x02,IO_ReadB(0x3ce));
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IO_ReadB(crt_reg+6);
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real_writeb(base_seg,base_dest+0x03,IO_ReadB(0x3c0));
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real_writeb(base_seg,base_dest+0x04,IO_ReadB(0x3ca));
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// sequencer
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for (ct=1; ct<5; ct++) {
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IO_WriteB(0x3c4,ct);
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real_writeb(base_seg,base_dest+0x04+ct,IO_ReadB(0x3c5));
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}
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real_writeb(base_seg,base_dest+0x09,IO_ReadB(0x3cc));
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// crt controller
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for (ct=0; ct<0x19; ct++) {
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IO_WriteB(crt_reg,ct);
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real_writeb(base_seg,base_dest+0x0a+ct,IO_ReadB(crt_reg+1));
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}
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// attr registers
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for (ct=0; ct<4; ct++) {
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IO_ReadB(crt_reg+6);
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IO_WriteB(0x3c0,0x10+ct);
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real_writeb(base_seg,base_dest+0x33+ct,IO_ReadB(0x3c1));
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}
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// graphics registers
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for (ct=0; ct<9; ct++) {
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IO_WriteB(0x3ce,ct);
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real_writeb(base_seg,base_dest+0x37+ct,IO_ReadB(0x3cf));
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}
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// save some registers
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IO_WriteB(0x3c4,2);
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Bit8u crtc_2=IO_ReadB(0x3c5);
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IO_WriteB(0x3c4,4);
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Bit8u crtc_4=IO_ReadB(0x3c5);
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IO_WriteB(0x3ce,6);
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Bit8u gfx_6=IO_ReadB(0x3cf);
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IO_WriteB(0x3ce,5);
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Bit8u gfx_5=IO_ReadB(0x3cf);
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IO_WriteB(0x3ce,4);
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Bit8u gfx_4=IO_ReadB(0x3cf);
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// reprogram for full access to plane latches
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IO_WriteW(0x3c4,0x0f02);
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IO_WriteW(0x3c4,0x0704);
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IO_WriteW(0x3ce,0x0406);
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IO_WriteW(0x3ce,0x0105);
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mem_writeb(0xaffff,0);
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for (ct=0; ct<4; ct++) {
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IO_WriteW(0x3ce,0x0004+ct*0x100);
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real_writeb(base_seg,base_dest+0x42+ct,mem_readb(0xaffff));
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}
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// restore registers
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IO_WriteW(0x3ce,0x0004|(gfx_4<<8));
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IO_WriteW(0x3ce,0x0005|(gfx_5<<8));
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IO_WriteW(0x3ce,0x0006|(gfx_6<<8));
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IO_WriteW(0x3c4,0x0004|(crtc_4<<8));
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IO_WriteW(0x3c4,0x0002|(crtc_2<<8));
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for (ct=0; ct<0x10; ct++) {
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IO_ReadB(crt_reg+6);
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IO_WriteB(0x3c0,ct);
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real_writeb(base_seg,base_dest+0x23+ct,IO_ReadB(0x3c1));
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}
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IO_WriteB(0x3c0,0x20);
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base_dest+=0x46;
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}
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if (state&2) {
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real_writew(base_seg,RealOff(buffer)+2,base_dest);
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real_writeb(base_seg,base_dest+0x00,mem_readb(0x410)&0x30);
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for (ct=0; ct<0x1e; ct++) {
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real_writeb(base_seg,base_dest+0x01+ct,mem_readb(0x449+ct));
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}
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for (ct=0; ct<0x07; ct++) {
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real_writeb(base_seg,base_dest+0x1f+ct,mem_readb(0x484+ct));
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}
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real_writed(base_seg,base_dest+0x26,mem_readd(0x48a));
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real_writed(base_seg,base_dest+0x2a,mem_readd(0x14)); // int 5
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real_writed(base_seg,base_dest+0x2e,mem_readd(0x74)); // int 1d
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real_writed(base_seg,base_dest+0x32,mem_readd(0x7c)); // int 1f
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real_writed(base_seg,base_dest+0x36,mem_readd(0x10c)); // int 43
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base_dest+=0x3a;
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}
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if (state&4) {
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real_writew(base_seg,RealOff(buffer)+4,base_dest);
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Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
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IO_ReadB(crt_reg+6);
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IO_WriteB(0x3c0,0x14);
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real_writeb(base_seg,base_dest+0x303,IO_ReadB(0x3c1));
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Bitu dac_state=IO_ReadB(0x3c7)&1;
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Bitu dac_windex=IO_ReadB(0x3c8);
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if (dac_state!=0) dac_windex--;
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real_writeb(base_seg,base_dest+0x000,dac_state);
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real_writeb(base_seg,base_dest+0x001,dac_windex);
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real_writeb(base_seg,base_dest+0x002,IO_ReadB(0x3c6));
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for (ct=0; ct<0x100; ct++) {
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IO_WriteB(0x3c7,ct);
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real_writeb(base_seg,base_dest+0x003+ct*3+0,IO_ReadB(0x3c9));
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real_writeb(base_seg,base_dest+0x003+ct*3+1,IO_ReadB(0x3c9));
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real_writeb(base_seg,base_dest+0x003+ct*3+2,IO_ReadB(0x3c9));
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}
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IO_ReadB(crt_reg+6);
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IO_WriteB(0x3c0,0x20);
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base_dest+=0x303;
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}
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if ((svgaCard==SVGA_S3Trio) && (state&8)) {
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real_writew(base_seg,RealOff(buffer)+6,base_dest);
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Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
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IO_WriteB(0x3c4,0x08);
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Bitu seq_8=IO_ReadB(0x3c5);
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// real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c5));
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IO_WriteB(0x3c5,0x06); // unlock s3-specific registers
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// sequencer
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for (ct=0; ct<0x13; ct++) {
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IO_WriteB(0x3c4,0x09+ct);
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real_writeb(base_seg,base_dest+0x00+ct,IO_ReadB(0x3c5));
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}
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// unlock s3-specific registers
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IO_WriteW(crt_reg,0x4838);
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IO_WriteW(crt_reg,0xa539);
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// crt controller
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Bitu ct_dest=0x13;
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for (ct=0; ct<0x40; ct++) {
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if ((ct==0x4a-0x30) || (ct==0x4b-0x30)) {
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IO_WriteB(crt_reg,0x45);
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IO_ReadB(crt_reg+1);
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IO_WriteB(crt_reg,0x30+ct);
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real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
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real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
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real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
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} else {
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IO_WriteB(crt_reg,0x30+ct);
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real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
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}
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}
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}
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return true;
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}
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bool INT10_VideoState_Restore(Bitu state,RealPt buffer) {
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Bitu ct;
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if ((state&7)==0) return false;
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Bit16u base_seg=RealSeg(buffer);
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Bit16u base_dest;
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if (state&1) {
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base_dest=real_readw(base_seg,RealOff(buffer));
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Bit16u crt_reg=real_readw(base_seg,base_dest+0x40);
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// reprogram for full access to plane latches
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IO_WriteW(0x3c4,0x0704);
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IO_WriteW(0x3ce,0x0406);
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IO_WriteW(0x3ce,0x0005);
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IO_WriteW(0x3c4,0x0002);
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mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x42));
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IO_WriteW(0x3c4,0x0102);
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mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x43));
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IO_WriteW(0x3c4,0x0202);
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mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x44));
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IO_WriteW(0x3c4,0x0402);
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mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x45));
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IO_WriteW(0x3c4,0x0f02);
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mem_readb(0xaffff);
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IO_WriteW(0x3c4,0x0100);
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// sequencer
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for (ct=1; ct<5; ct++) {
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IO_WriteW(0x3c4,ct+(real_readb(base_seg,base_dest+0x04+ct)<<8));
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}
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IO_WriteB(0x3c2,real_readb(base_seg,base_dest+0x09));
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IO_WriteW(0x3c4,0x0300);
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IO_WriteW(crt_reg,0x0011);
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// crt controller
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for (ct=0; ct<0x19; ct++) {
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IO_WriteW(crt_reg,ct+(real_readb(base_seg,base_dest+0x0a+ct)<<8));
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}
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IO_ReadB(crt_reg+6);
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// attr registers
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for (ct=0; ct<4; ct++) {
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IO_WriteB(0x3c0,0x10+ct);
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IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x33+ct));
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}
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// graphics registers
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for (ct=0; ct<9; ct++) {
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IO_WriteW(0x3ce,ct+(real_readb(base_seg,base_dest+0x37+ct)<<8));
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}
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IO_WriteB(crt_reg+6,real_readb(base_seg,base_dest+0x04));
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IO_ReadB(crt_reg+6);
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// attr registers
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for (ct=0; ct<0x10; ct++) {
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IO_WriteB(0x3c0,ct);
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IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x23+ct));
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}
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IO_WriteB(0x3c4,real_readb(base_seg,base_dest+0x00));
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IO_WriteB(0x3d4,real_readb(base_seg,base_dest+0x01));
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IO_WriteB(0x3ce,real_readb(base_seg,base_dest+0x02));
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IO_ReadB(crt_reg+6);
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IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x03));
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}
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if (state&2) {
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base_dest=real_readw(base_seg,RealOff(buffer)+2);
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mem_writeb(0x410,(mem_readb(0x410)&0xcf) | real_readb(base_seg,base_dest+0x00));
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for (ct=0; ct<0x1e; ct++) {
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mem_writeb(0x449+ct,real_readb(base_seg,base_dest+0x01+ct));
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}
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for (ct=0; ct<0x07; ct++) {
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mem_writeb(0x484+ct,real_readb(base_seg,base_dest+0x1f+ct));
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}
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mem_writed(0x48a,real_readd(base_seg,base_dest+0x26));
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mem_writed(0x14,real_readd(base_seg,base_dest+0x2a)); // int 5
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mem_writed(0x74,real_readd(base_seg,base_dest+0x2e)); // int 1d
|
||||
mem_writed(0x7c,real_readd(base_seg,base_dest+0x32)); // int 1f
|
||||
mem_writed(0x10c,real_readd(base_seg,base_dest+0x36)); // int 43
|
||||
}
|
||||
|
||||
if (state&4) {
|
||||
base_dest=real_readw(base_seg,RealOff(buffer)+4);
|
||||
|
||||
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
|
||||
|
||||
IO_WriteB(0x3c6,real_readb(base_seg,base_dest+0x002));
|
||||
|
||||
for (ct=0; ct<0x100; ct++) {
|
||||
IO_WriteB(0x3c8,ct);
|
||||
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+0));
|
||||
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+1));
|
||||
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+2));
|
||||
}
|
||||
|
||||
IO_ReadB(crt_reg+6);
|
||||
IO_WriteB(0x3c0,0x14);
|
||||
IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x303));
|
||||
|
||||
Bitu dac_state=real_readb(base_seg,base_dest+0x000);
|
||||
if (dac_state==0) {
|
||||
IO_WriteB(0x3c8,real_readb(base_seg,base_dest+0x001));
|
||||
} else {
|
||||
IO_WriteB(0x3c7,real_readb(base_seg,base_dest+0x001));
|
||||
}
|
||||
}
|
||||
|
||||
if ((svgaCard==SVGA_S3Trio) && (state&8)) {
|
||||
base_dest=real_readw(base_seg,RealOff(buffer)+6);
|
||||
|
||||
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
|
||||
|
||||
Bitu seq_idx=IO_ReadB(0x3c4);
|
||||
IO_WriteB(0x3c4,0x08);
|
||||
Bitu seq_8=IO_ReadB(0x3c5);
|
||||
// real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c5));
|
||||
IO_WriteB(0x3c5,0x06); // unlock s3-specific registers
|
||||
|
||||
// sequencer
|
||||
for (ct=0; ct<0x13; ct++) {
|
||||
IO_WriteW(0x3c4,(0x09+ct)+(real_readb(base_seg,base_dest+0x00+ct)<<8));
|
||||
}
|
||||
IO_WriteB(0x3c4,seq_idx);
|
||||
|
||||
Bitu crtc_idx=IO_ReadB(0x3d4);
|
||||
|
||||
// unlock s3-specific registers
|
||||
IO_WriteW(crt_reg,0x4838);
|
||||
IO_WriteW(crt_reg,0xa539);
|
||||
|
||||
// crt controller
|
||||
Bitu ct_dest=0x13;
|
||||
for (ct=0; ct<0x40; ct++) {
|
||||
if ((ct==0x4a-0x30) || (ct==0x4b-0x30)) {
|
||||
IO_WriteB(crt_reg,0x45);
|
||||
IO_ReadB(crt_reg+1);
|
||||
IO_WriteB(crt_reg,0x30+ct);
|
||||
IO_WriteB(crt_reg,real_readb(base_seg,base_dest+(ct_dest++)));
|
||||
} else {
|
||||
IO_WriteW(crt_reg,(0x30+ct)+(real_readb(base_seg,base_dest+(ct_dest++))<<8));
|
||||
}
|
||||
}
|
||||
|
||||
// mmio
|
||||
/* IO_WriteB(crt_reg,0x40);
|
||||
Bitu sysval1=IO_ReadB(crt_reg+1);
|
||||
IO_WriteB(crt_reg+1,sysval|1);
|
||||
IO_WriteB(crt_reg,0x53);
|
||||
Bitu sysva2=IO_ReadB(crt_reg+1);
|
||||
IO_WriteB(crt_reg+1,sysval2|0x10);
|
||||
|
||||
real_writew(0xa000,0x8128,0xffff);
|
||||
|
||||
IO_WriteB(crt_reg,0x40);
|
||||
IO_WriteB(crt_reg,sysval1);
|
||||
IO_WriteB(crt_reg,0x53);
|
||||
IO_WriteB(crt_reg,sysval2);
|
||||
IO_WriteB(crt_reg,crtc_idx); */
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -689,6 +689,9 @@
|
|||
<File
|
||||
RelativePath="..\src\ints\int10_vesa.cpp">
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\src\ints\int10_video_state.cpp">
|
||||
</File>
|
||||
</Filter>
|
||||
</Filter>
|
||||
<Filter
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue