New io handler functions
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1758
This commit is contained in:
Sjoerd van der Berg
parent
d0e2bfa15f
commit
9cd769b878
23 changed files with 309 additions and 367 deletions
|
|
@ -16,30 +16,44 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
typedef Bit8u (IO_ReadBHandler)(Bit32u port);
|
||||
typedef Bit16u (IO_ReadWHandler)(Bit32u port);
|
||||
typedef Bit32u (IO_ReadDHandler)(Bit32u port);
|
||||
typedef void (IO_WriteBHandler)(Bit32u port,Bit8u value);
|
||||
typedef void (IO_WriteWHandler)(Bit32u port,Bit16u value);
|
||||
typedef void (IO_WriteDHandler)(Bit32u port,Bit32u value);
|
||||
#define IO_MAX (64*1024+3)
|
||||
|
||||
void IO_RegisterReadBHandler(Bitu port,IO_ReadBHandler * handler);
|
||||
void IO_RegisterReadWHandler(Bitu port,IO_ReadWHandler * handler);
|
||||
void IO_RegisterReadDHandler(Bitu port,IO_ReadDHandler * handler);
|
||||
#define IO_MB 0x1
|
||||
#define IO_MW 0x2
|
||||
#define IO_MD 0x4
|
||||
#define IO_MA (IO_MB | IO_MW | IO_MD )
|
||||
|
||||
void IO_RegisterWriteBHandler(Bitu port,IO_WriteBHandler * handler);
|
||||
void IO_RegisterWriteWHandler(Bitu port,IO_WriteWHandler * handler);
|
||||
void IO_RegisterWriteDHandler(Bitu port,IO_WriteDHandler * handler);
|
||||
typedef Bitu IO_ReadHandler(Bitu port,Bitu iolen);
|
||||
typedef void IO_WriteHandler(Bitu port,Bitu val,Bitu iolen);
|
||||
|
||||
void IO_FreeReadHandler(Bitu port);
|
||||
void IO_FreeWriteHandler(Bitu port);
|
||||
extern IO_WriteHandler * io_writehandlers[3][IO_MAX];
|
||||
extern IO_ReadHandler * io_readhandlers[3][IO_MAX];
|
||||
|
||||
void IO_WriteB(Bitu port,Bit8u val);
|
||||
Bit8u IO_ReadB(Bitu port);
|
||||
void IO_WriteW(Bitu port,Bit16u val);
|
||||
Bit16u IO_ReadW(Bitu port);
|
||||
void IO_WriteD(Bitu port,Bit32u val);
|
||||
Bit32u IO_ReadD(Bitu port);
|
||||
void IO_RegisterReadHandler(Bitu port,IO_ReadHandler * handler,Bitu mask,Bitu range=1);
|
||||
void IO_RegisterWriteHandler(Bitu port,IO_WriteHandler * handler,Bitu mask,Bitu range=1);
|
||||
|
||||
void IO_FreeReadHandler(Bitu port,Bitu mask,Bitu range=0);
|
||||
void IO_FreeWriteHandler(Bitu port,Bitu mask,Bitu range=0);
|
||||
|
||||
INLINE void IO_WriteB(Bitu port,Bitu val) {
|
||||
io_writehandlers[0][port](port,val,1);
|
||||
};
|
||||
INLINE void IO_WriteW(Bitu port,Bitu val) {
|
||||
io_writehandlers[1][port](port,val,2);
|
||||
};
|
||||
INLINE void IO_WriteD(Bitu port,Bitu val) {
|
||||
io_writehandlers[2][port](port,val,4);
|
||||
};
|
||||
|
||||
INLINE Bitu IO_ReadB(Bitu port) {
|
||||
return io_readhandlers[0][port](port,1);
|
||||
}
|
||||
INLINE Bitu IO_ReadW(Bitu port) {
|
||||
return io_readhandlers[1][port](port,2);
|
||||
}
|
||||
INLINE Bitu IO_ReadD(Bitu port) {
|
||||
return io_readhandlers[2][port](port,4);
|
||||
}
|
||||
|
||||
INLINE void IO_Write(Bitu port,Bit8u val) {
|
||||
IO_WriteB(port,val);
|
||||
|
|
@ -48,11 +62,4 @@ INLINE Bit8u IO_Read(Bitu port){
|
|||
return IO_ReadB(port);
|
||||
}
|
||||
|
||||
INLINE void IO_RegisterReadHandler(Bitu port,IO_ReadBHandler * handler,char * name) {
|
||||
IO_RegisterReadBHandler(port,handler);
|
||||
}
|
||||
INLINE void IO_RegisterWriteHandler(Bitu port,IO_WriteBHandler * handler,char * name) {
|
||||
IO_RegisterWriteBHandler(port,handler);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -50,11 +50,11 @@ public:
|
|||
virtual ~CSerial();
|
||||
|
||||
// External port functions for IOHandlers //
|
||||
void write_port(Bit32u port, Bit8u val);
|
||||
Bit8u read_port(Bit32u port);
|
||||
void write_port(Bitu port, Bitu val);
|
||||
Bitu read_port(Bitu port);
|
||||
|
||||
static void write_serial(Bit32u port,Bit8u val);
|
||||
static Bit8u read_serial(Bit32u port);
|
||||
static void write_serial(Bitu port,Bitu val,Bitu iolen);
|
||||
static Bitu read_serial(Bitu port,Bitu iolen);
|
||||
|
||||
void SetMCHandler(MControl_Handler * mcontrol);
|
||||
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ static void OPL_CallBack(Bit8u *stream, Bit32u len) {
|
|||
}
|
||||
}
|
||||
|
||||
Bit8u OPL_Read(Bit32u port) {
|
||||
static Bitu OPL_Read(Bitu port,Bitu iolen) {
|
||||
Bitu addr=port & 3;
|
||||
switch (opl.mode) {
|
||||
case OPL_opl2:
|
||||
|
|
@ -126,7 +126,7 @@ Bit8u OPL_Read(Bit32u port) {
|
|||
return 0xff;
|
||||
}
|
||||
|
||||
void OPL_Write(Bit32u port,Bit8u val) {
|
||||
void OPL_Write(Bitu port,Bitu val,Bitu iolen) {
|
||||
opl.last_used=PIC_Ticks;
|
||||
if (!opl.active) {
|
||||
opl.active=true;
|
||||
|
|
@ -147,7 +147,6 @@ void OPL_Write(Bit32u port,Bit8u val) {
|
|||
}
|
||||
|
||||
void OPL_Init(Section* sec,Bitu base,OPL_Mode oplmode,Bitu rate) {
|
||||
Bitu i;
|
||||
Section_prop * section=static_cast<Section_prop *>(sec);
|
||||
if (OPL2::YM3812Init(2,OPL2_INTERNAL_FREQ,rate)) {
|
||||
E_Exit("Can't create OPL2 Emulator");
|
||||
|
|
@ -158,16 +157,13 @@ void OPL_Init(Section* sec,Bitu base,OPL_Mode oplmode,Bitu rate) {
|
|||
E_Exit("Can't create OPL3 Emulator");
|
||||
};
|
||||
THEOPL3::YMF262SetTimerHandler(0,THEOPL3::TimerHandler,0);
|
||||
for (i=0;i<4;i++) {
|
||||
IO_RegisterWriteHandler(0x388+i,OPL_Write,"OPL Write");
|
||||
IO_RegisterReadHandler(0x388+i,OPL_Read,"OPL read");
|
||||
IO_RegisterWriteHandler(base+i,OPL_Write,"OPL Write");
|
||||
IO_RegisterReadHandler(base+i,OPL_Read,"OPL read");
|
||||
}
|
||||
IO_RegisterWriteHandler(base+8,OPL_Write,"OPL Write");
|
||||
IO_RegisterWriteHandler(base+9,OPL_Write,"OPL Write");
|
||||
IO_RegisterReadHandler(base+8,OPL_Read,"OPL read");
|
||||
IO_RegisterReadHandler(base+9,OPL_Read,"OPL read");
|
||||
IO_RegisterWriteHandler(0x388,OPL_Write,IO_MB,4);
|
||||
IO_RegisterReadHandler(0x388,OPL_Read,IO_MB,4);
|
||||
IO_RegisterWriteHandler(base,OPL_Write,IO_MB,4);
|
||||
IO_RegisterReadHandler(base,OPL_Read,IO_MB,4);
|
||||
|
||||
IO_RegisterWriteHandler(base+8,OPL_Write,IO_MB,2);
|
||||
IO_RegisterReadHandler(base+8,OPL_Read,IO_MB,2);
|
||||
|
||||
|
||||
opl.active=false;
|
||||
|
|
|
|||
|
|
@ -62,12 +62,12 @@ static void cmos_checktimer(void) {
|
|||
PIC_AddEvent(cmos_timerevent,cmos.timer.micro);
|
||||
}
|
||||
|
||||
void cmos_selreg(Bit32u port,Bit8u val) {
|
||||
void cmos_selreg(Bitu port,Bitu val,Bitu iolen) {
|
||||
cmos.reg=val & 0x3f;
|
||||
cmos.nmi=(val & 0x80)>0;
|
||||
}
|
||||
|
||||
static void cmos_writereg(Bit32u port,Bit8u val) {
|
||||
static void cmos_writereg(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (cmos.reg) {
|
||||
case 0x00: /* Seconds */
|
||||
case 0x02: /* Minutes */
|
||||
|
|
@ -84,10 +84,9 @@ static void cmos_writereg(Bit32u port,Bit8u val) {
|
|||
LOG(LOG_BIOS,LOG_NORMAL)("CMOS:Trying to set alarm");
|
||||
cmos.regs[cmos.reg]=val;
|
||||
break;
|
||||
|
||||
case 0x0a: /* Status reg A */
|
||||
cmos.regs[cmos.reg]=val & 0x7f;
|
||||
if (val & 0x70!=0x20) LOG(LOG_BIOS,LOG_ERROR)("CMOS Illegal 22 stage divider value");
|
||||
if ((val & 0x70)!=0x20) LOG(LOG_BIOS,LOG_ERROR)("CMOS Illegal 22 stage divider value");
|
||||
cmos.timer.div=(val & 0xf);
|
||||
cmos_checktimer();
|
||||
break;
|
||||
|
|
@ -110,7 +109,7 @@ static void cmos_writereg(Bit32u port,Bit8u val) {
|
|||
|
||||
#define MAKE_RETURN(_VAL) (cmos.bcd ? (((_VAL / 10) << 4) | (_VAL % 10)) : _VAL);
|
||||
|
||||
static Bit8u cmos_readreg(Bit32u port) {
|
||||
static Bitu cmos_readreg(Bitu port,Bitu iolen) {
|
||||
if (cmos.reg>0x3f) {
|
||||
LOG(LOG_BIOS,LOG_ERROR)("CMOS:Read from illegal register %x",cmos.reg);
|
||||
return 0xff;
|
||||
|
|
@ -189,14 +188,14 @@ void CMOS_SetRegister(Bitu regNr, Bit8u val)
|
|||
};
|
||||
|
||||
void CMOS_Init(Section* sec) {
|
||||
IO_RegisterWriteHandler(0x70,cmos_selreg,"CMOS");
|
||||
IO_RegisterWriteHandler(0x71,cmos_writereg,"CMOS");
|
||||
IO_RegisterReadHandler(0x71,cmos_readreg,"CMOS");
|
||||
IO_RegisterWriteHandler(0x70,cmos_selreg,IO_MB);
|
||||
IO_RegisterWriteHandler(0x71,cmos_writereg,IO_MB);
|
||||
IO_RegisterReadHandler(0x71,cmos_readreg,IO_MB);
|
||||
cmos.timer.enabled=false;
|
||||
cmos.reg=0xa;
|
||||
cmos_writereg(0x71,0x26);
|
||||
cmos_writereg(0x71,0x26,1);
|
||||
cmos.reg=0xb;
|
||||
cmos_writereg(0x71,0);
|
||||
cmos_writereg(0x71,0,1);
|
||||
/* Fill in extended memory size */
|
||||
Bitu exsize=(MEM_TotalPages()*4)-1024;
|
||||
cmos.regs[0x17]=(Bit8u)exsize;
|
||||
|
|
|
|||
|
|
@ -20,9 +20,7 @@
|
|||
#include "dosbox.h"
|
||||
#include "inout.h"
|
||||
#include "mixer.h"
|
||||
#include "dma.h"
|
||||
#include "pic.h"
|
||||
#include "hardware.h"
|
||||
#include "setup.h"
|
||||
#include "programs.h"
|
||||
|
||||
|
|
@ -41,7 +39,7 @@ static struct {
|
|||
MIXER_Channel * chan;
|
||||
} disney;
|
||||
|
||||
static void disney_write(Bit32u port,Bit8u val) {
|
||||
static void disney_write(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (port-DISNEY_BASE) {
|
||||
case 0: /* Data Port */
|
||||
disney.data=val;
|
||||
|
|
@ -62,8 +60,7 @@ static void disney_write(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u disney_read(Bit32u port) {
|
||||
|
||||
static Bitu disney_read(Bitu port,Bitu iolen) {
|
||||
switch (port-DISNEY_BASE) {
|
||||
case 0: /* Data Port */
|
||||
// LOG(LOG_MISC,LOG_NORMAL)("DISNEY:Read from data port");
|
||||
|
|
@ -103,13 +100,8 @@ void DISNEY_Init(Section* sec) {
|
|||
Section_prop * section=static_cast<Section_prop *>(sec);
|
||||
if(!section->Get_bool("disney")) return;
|
||||
|
||||
IO_RegisterWriteHandler(DISNEY_BASE,disney_write,"DISNEY");
|
||||
IO_RegisterWriteHandler(DISNEY_BASE+1,disney_write,"DISNEY");
|
||||
IO_RegisterWriteHandler(DISNEY_BASE+2,disney_write,"DISNEY");
|
||||
|
||||
IO_RegisterReadHandler(DISNEY_BASE,disney_read,"DISNEY");
|
||||
IO_RegisterReadHandler(DISNEY_BASE+1,disney_read,"DISNEY");
|
||||
IO_RegisterReadHandler(DISNEY_BASE+2,disney_read,"DISNEY");
|
||||
IO_RegisterWriteHandler(DISNEY_BASE,disney_write,IO_MB,3);
|
||||
IO_RegisterReadHandler(DISNEY_BASE,disney_read,IO_MB,3);
|
||||
|
||||
disney.chan=MIXER_AddChannel(&DISNEY_CallBack,7000,"DISNEY");
|
||||
MIXER_SetMode(disney.chan,MIXER_8MONO);
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static Bitu DMA_ReadControllerReg(DmaController * cont,Bitu reg,Bitu len) {
|
|||
}
|
||||
|
||||
|
||||
static void DMA_Write_PortB(Bit32u port,Bit8u val) {
|
||||
static void DMA_Write_Port(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (port<0x10) {
|
||||
DMA_WriteControllerReg(DmaControllers[0],port,val,1);
|
||||
} else if (port>=0xc0 && port <=0xdf) {
|
||||
|
|
@ -142,15 +142,11 @@ static void DMA_Write_PortB(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void DMA_Write_PortW(Bit32u port,Bit16u val) {
|
||||
LOG_MSG("Ahh 16bit write port %x val %x",port,val);
|
||||
}
|
||||
static Bit8u DMA_Read_PortB(Bit32u port) {
|
||||
static Bitu DMA_Read_Port(Bitu port,Bitu iolen) {
|
||||
if (port<0x10) {
|
||||
return DMA_ReadControllerReg(DmaControllers[0],port,1);
|
||||
return DMA_ReadControllerReg(DmaControllers[0],port,iolen);
|
||||
} else if (port>=0xc0 && port <=0xdf) {
|
||||
return DMA_ReadControllerReg(DmaControllers[1],(port-0xc0) >> 1,1);
|
||||
return DMA_ReadControllerReg(DmaControllers[1],(port-0xc0) >> 1,iolen);
|
||||
} else switch (port) {
|
||||
case 0x81:return DmaChannels[2]->pagenum;
|
||||
case 0x82:return DmaChannels[3]->pagenum;
|
||||
|
|
@ -159,6 +155,7 @@ static Bit8u DMA_Read_PortB(Bit32u port) {
|
|||
case 0x8a:return DmaChannels[7]->pagenum;
|
||||
case 0x8b:return DmaChannels[5]->pagenum;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
DmaChannel::DmaChannel(Bit8u num, bool dma16) {
|
||||
|
|
@ -244,27 +241,27 @@ void DMA_Init(Section* sec) {
|
|||
DmaChannels[i] = new DmaChannel(i,i>=4);
|
||||
}
|
||||
for (i=0;i<0x10;i++) {
|
||||
IO_RegisterWriteBHandler(i,DMA_Write_PortB);
|
||||
IO_RegisterWriteWHandler(i,DMA_Write_PortW);
|
||||
IO_RegisterReadBHandler(i,DMA_Read_PortB);
|
||||
Bitu mask=i<8 ? (IO_MB|IO_MW) : IO_MB;
|
||||
IO_RegisterWriteHandler(i,DMA_Write_Port,mask);
|
||||
IO_RegisterReadHandler(i,DMA_Read_Port,mask);
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteBHandler(0xc0+i*2,DMA_Write_PortB);
|
||||
IO_RegisterReadBHandler(0xc0+i*2,DMA_Read_PortB);
|
||||
IO_RegisterWriteHandler(0xc0+i*2,DMA_Write_Port,mask);
|
||||
IO_RegisterReadHandler(0xc0+i*2,DMA_Read_Port,mask);
|
||||
}
|
||||
}
|
||||
IO_RegisterWriteBHandler(0x81,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x82,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x83,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x89,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x8a,DMA_Write_PortB);
|
||||
IO_RegisterWriteBHandler(0x8b,DMA_Write_PortB);
|
||||
IO_RegisterWriteHandler(0x81,DMA_Write_Port,IO_MB);
|
||||
IO_RegisterWriteHandler(0x82,DMA_Write_Port,IO_MB);
|
||||
IO_RegisterWriteHandler(0x83,DMA_Write_Port,IO_MB);
|
||||
IO_RegisterWriteHandler(0x89,DMA_Write_Port,IO_MB);
|
||||
IO_RegisterWriteHandler(0x8a,DMA_Write_Port,IO_MB);
|
||||
IO_RegisterWriteHandler(0x8b,DMA_Write_Port,IO_MB);
|
||||
|
||||
IO_RegisterReadBHandler(0x81,DMA_Read_PortB);
|
||||
IO_RegisterReadBHandler(0x82,DMA_Read_PortB);
|
||||
IO_RegisterReadBHandler(0x83,DMA_Read_PortB);
|
||||
IO_RegisterReadBHandler(0x89,DMA_Read_PortB);
|
||||
IO_RegisterReadBHandler(0x8a,DMA_Read_PortB);
|
||||
IO_RegisterReadBHandler(0x8b,DMA_Read_PortB);
|
||||
IO_RegisterReadHandler(0x81,DMA_Read_Port,IO_MB);
|
||||
IO_RegisterReadHandler(0x82,DMA_Read_Port,IO_MB);
|
||||
IO_RegisterReadHandler(0x83,DMA_Read_Port,IO_MB);
|
||||
IO_RegisterReadHandler(0x89,DMA_Read_Port,IO_MB);
|
||||
IO_RegisterReadHandler(0x8a,DMA_Read_Port,IO_MB);
|
||||
IO_RegisterReadHandler(0x8b,DMA_Read_Port,IO_MB);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -363,7 +363,7 @@ static void saa1099_write_port_w( int chip, int offset, int data )
|
|||
}
|
||||
|
||||
|
||||
static void write_cms(Bit32u port,Bit8u val) {
|
||||
static void write_cms(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (last_command + 100 < PIC_Ticks) MIXER_Enable(cms_chan,true);
|
||||
last_command = PIC_Ticks;
|
||||
switch (port) {
|
||||
|
|
@ -424,10 +424,7 @@ static void write_cms(Bit32u port,Bit8u val) {
|
|||
Section_prop * section=static_cast<Section_prop *>(sec);
|
||||
sample_rate=rate;
|
||||
|
||||
IO_RegisterWriteHandler(base+0x0,write_cms,"CMS");
|
||||
IO_RegisterWriteHandler(base+0x1,write_cms,"CMS");
|
||||
IO_RegisterWriteHandler(base+0x2,write_cms,"CMS");
|
||||
IO_RegisterWriteHandler(base+0x3,write_cms,"CMS");
|
||||
IO_RegisterWriteHandler(base,write_cms,IO_MB,4);
|
||||
|
||||
/* Register the Mixer CallBack */
|
||||
|
||||
|
|
|
|||
|
|
@ -19,130 +19,90 @@
|
|||
#include "dosbox.h"
|
||||
#include "inout.h"
|
||||
|
||||
#define IO_MAX 1024
|
||||
IO_WriteHandler * io_writehandlers[3][IO_MAX];
|
||||
IO_ReadHandler * io_readhandlers[3][IO_MAX];
|
||||
|
||||
static struct IO_Block {
|
||||
IO_WriteBHandler * write_b[IO_MAX];
|
||||
IO_WriteWHandler * write_w[IO_MAX];
|
||||
IO_WriteDHandler * write_d[IO_MAX];
|
||||
|
||||
IO_ReadBHandler * read_b[IO_MAX];
|
||||
IO_ReadWHandler * read_w[IO_MAX];
|
||||
IO_ReadDHandler * read_d[IO_MAX];
|
||||
} io;
|
||||
|
||||
void IO_WriteB(Bitu port,Bit8u val) {
|
||||
if (port<IO_MAX) io.write_b[port](port,val);
|
||||
else LOG(LOG_IO,LOG_WARN)("WriteB:Out or range write %X to port %4X",val,port);
|
||||
static Bitu IO_ReadBlocked(Bitu port,Bitu iolen) {
|
||||
return (Bitu)-1;
|
||||
}
|
||||
void IO_WriteW(Bitu port,Bit16u val) {
|
||||
if (port<(IO_MAX & ~1)) io.write_w[port](port,val);
|
||||
else LOG(LOG_IO,LOG_WARN)("WriteW:Out or range write %X to port %4X",val,port);
|
||||
}
|
||||
void IO_WriteD(Bitu port,Bit32u val) {
|
||||
if (port<(IO_MAX & ~3)) io.write_d[port](port,val);
|
||||
else LOG(LOG_IO,LOG_WARN)("WriteD:Out or range write %X to port %4X",val,port);
|
||||
static void IO_WriteBlocked(Bitu port,Bitu val,Bitu iolen) {
|
||||
}
|
||||
|
||||
Bit8u IO_ReadB(Bitu port) {
|
||||
if (port<IO_MAX) return io.read_b[port](port);
|
||||
else LOG(LOG_IO,LOG_WARN)("ReadB:Out or range read from port %4X",port);
|
||||
return 0xff;
|
||||
}
|
||||
Bit16u IO_ReadW(Bitu port) {
|
||||
if (port<(IO_MAX & ~1)) return io.read_w[port](port);
|
||||
else LOG(LOG_IO,LOG_WARN)("ReadW:Out or range read from port %4X",port);
|
||||
return 0xffff;
|
||||
}
|
||||
Bit32u IO_ReadD(Bitu port) {
|
||||
if (port<(IO_MAX & ~3)) return io.read_d[port](port);
|
||||
else LOG(LOG_IO,LOG_WARN)("ReadD:Out or range read from port %4X",port);
|
||||
return 0xffffffff;
|
||||
static Bitu IO_ReadDefault(Bitu port,Bitu iolen) {
|
||||
switch (iolen) {
|
||||
case 1:
|
||||
LOG(LOG_IO,LOG_WARN)("Read from port %04X",port);
|
||||
io_readhandlers[0][port]=IO_ReadBlocked;
|
||||
return 0xff;
|
||||
case 2:
|
||||
return
|
||||
(io_readhandlers[0][port+0](port+0,1) << 0) |
|
||||
(io_readhandlers[0][port+1](port+1,1) << 8);
|
||||
case 4:
|
||||
return
|
||||
(io_readhandlers[1][port+0](port+0,2) << 0) |
|
||||
(io_readhandlers[1][port+2](port+2,2) << 16);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static Bit8u IO_ReadBBlocked(Bit32u port) {
|
||||
return 0xff;
|
||||
}
|
||||
static void IO_WriteBBlocked(Bit32u port,Bit8u val) {
|
||||
void IO_WriteDefault(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (iolen) {
|
||||
case 1:
|
||||
LOG(LOG_IO,LOG_WARN)("Writing %02X to port %04X",val,port);
|
||||
io_writehandlers[0][port]=IO_WriteBlocked;
|
||||
break;
|
||||
case 2:
|
||||
io_writehandlers[0][port+0](port+0,(val >> 0) & 0xff,1);
|
||||
io_writehandlers[0][port+1](port+1,(val >> 8) & 0xff,1);
|
||||
break;
|
||||
case 4:
|
||||
io_writehandlers[1][port+0](port+0,(val >> 0 ) & 0xffff,2);
|
||||
io_writehandlers[1][port+2](port+2,(val >> 16) & 0xffff,2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static Bit8u IO_ReadDefaultB(Bit32u port) {
|
||||
LOG(LOG_IO,LOG_WARN)("Reading from undefined port %04X",port);
|
||||
io.read_b[port]=IO_ReadBBlocked;
|
||||
return 0xff;
|
||||
void IO_RegisterReadHandler(Bitu port,IO_ReadHandler * handler,Bitu mask,Bitu range) {
|
||||
while (range--) {
|
||||
if (mask&IO_MB) io_readhandlers[0][port]=handler;
|
||||
if (mask&IO_MW) io_readhandlers[1][port]=handler;
|
||||
if (mask&IO_MD) io_readhandlers[2][port]=handler;
|
||||
port++;
|
||||
}
|
||||
}
|
||||
static Bit16u IO_ReadDefaultW(Bit32u port) {
|
||||
return io.read_b[port](port) | (io.read_b[port+1](port+1) << 8);
|
||||
}
|
||||
static Bit32u IO_ReadDefaultD(Bit32u port) {
|
||||
return io.read_b[port](port) | (io.read_b[port+1](port+1) << 8) |
|
||||
(io.read_b[port+2](port+2) << 16) | (io.read_b[port+3](port+3) << 24);
|
||||
void IO_RegisterWriteHandler(Bitu port,IO_WriteHandler * handler,Bitu mask,Bitu range) {
|
||||
while (range--) {
|
||||
if (mask&IO_MB) io_writehandlers[0][port]=handler;
|
||||
if (mask&IO_MW) io_writehandlers[1][port]=handler;
|
||||
if (mask&IO_MD) io_writehandlers[2][port]=handler;
|
||||
port++;
|
||||
}
|
||||
}
|
||||
|
||||
void IO_WriteDefaultB(Bit32u port,Bit8u val) {
|
||||
LOG(LOG_IO,LOG_WARN)("Writing %02X to undefined port %04X",static_cast<Bit32u>(val),port);
|
||||
io.write_b[port]=IO_WriteBBlocked;
|
||||
}
|
||||
void IO_WriteDefaultW(Bit32u port,Bit16u val) {
|
||||
io.write_b[port](port,(Bit8u)val);
|
||||
io.write_b[port+1](port+1,(Bit8u)(val>>8));
|
||||
}
|
||||
void IO_WriteDefaultD(Bit32u port,Bit32u val) {
|
||||
io.write_b[port](port,(Bit8u)val);
|
||||
io.write_b[port+1](port+1,(Bit8u)(val>>8));
|
||||
io.write_b[port+2](port+2,(Bit8u)(val>>16));
|
||||
io.write_b[port+3](port+3,(Bit8u)(val>>24));
|
||||
void IO_FreeReadHandler(Bitu port,Bitu mask,Bitu range) {
|
||||
while (range--) {
|
||||
if (mask&IO_MB) io_readhandlers[0][port]=IO_ReadDefault;
|
||||
if (mask&IO_MW) io_readhandlers[1][port]=IO_ReadDefault;
|
||||
if (mask&IO_MD) io_readhandlers[2][port]=IO_ReadDefault;
|
||||
port++;
|
||||
}
|
||||
}
|
||||
|
||||
void IO_RegisterReadBHandler(Bitu port,IO_ReadBHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.read_b[port]=handler;
|
||||
}
|
||||
void IO_RegisterReadWHandler(Bitu port,IO_ReadWHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.read_w[port]=handler;
|
||||
}
|
||||
void IO_RegisterReadDHandler(Bitu port,IO_ReadDHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.read_d[port]=handler;
|
||||
}
|
||||
void IO_RegisterWriteBHandler(Bitu port,IO_WriteBHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.write_b[port]=handler;
|
||||
}
|
||||
void IO_RegisterWriteWHandler(Bitu port,IO_WriteWHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.write_w[port]=handler;
|
||||
}
|
||||
void IO_RegisterWriteDHandler(Bitu port,IO_WriteDHandler * handler) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.write_d[port]=handler;
|
||||
}
|
||||
|
||||
|
||||
void IO_FreeReadHandler(Bitu port) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.read_b[port]=IO_ReadDefaultB;
|
||||
io.read_w[port]=IO_ReadDefaultW;
|
||||
io.read_d[port]=IO_ReadDefaultD;
|
||||
}
|
||||
void IO_FreeWriteHandler(Bitu port) {
|
||||
if (port>=IO_MAX) return;
|
||||
io.write_b[port]=IO_WriteDefaultB;
|
||||
io.write_w[port]=IO_WriteDefaultW;
|
||||
io.write_d[port]=IO_WriteDefaultD;
|
||||
}
|
||||
|
||||
void IO_Init(Section * sect) {
|
||||
for (Bitu i=0;i<IO_MAX;i++) {
|
||||
io.read_b[i]=IO_ReadDefaultB;
|
||||
io.read_w[i]=IO_ReadDefaultW;
|
||||
io.read_d[i]=IO_ReadDefaultD;
|
||||
io.write_b[i]=IO_WriteDefaultB;
|
||||
io.write_w[i]=IO_WriteDefaultW;
|
||||
io.write_d[i]=IO_WriteDefaultD;
|
||||
void IO_FreeWriteHandler(Bitu port,Bitu mask,Bitu range) {
|
||||
while (range--) {
|
||||
if (mask&IO_MB) io_writehandlers[0][port]=IO_WriteDefault;
|
||||
if (mask&IO_MW) io_writehandlers[1][port]=IO_WriteDefault;
|
||||
if (mask&IO_MD) io_writehandlers[2][port]=IO_WriteDefault;
|
||||
port++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void IO_Init(Section * sect) {
|
||||
IO_FreeReadHandler(0,IO_MA,IO_MAX);
|
||||
IO_FreeWriteHandler(0,IO_MA,IO_MAX);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ struct JoyStick {
|
|||
static JoyStick stick[2];
|
||||
|
||||
|
||||
static Bit8u read_p201(Bit32u port) {
|
||||
static Bitu read_p201(Bitu port,Bitu iolen) {
|
||||
/** Format of the byte to be returned:
|
||||
** | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
||||
** +-------------------------------+
|
||||
|
|
@ -58,7 +58,7 @@ static Bit8u read_p201(Bit32u port) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void write_p201(Bit32u port,Bit8u val) {
|
||||
static void write_p201(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (stick[0].enabled) {
|
||||
stick[0].xcount=(Bitu)((stick[0].xpos*RANGE)+RANGE);
|
||||
stick[0].ycount=(Bitu)((stick[0].ypos*RANGE)+RANGE);
|
||||
|
|
@ -115,8 +115,8 @@ float JOYSTICK_GetMove_Y(Bitu which)
|
|||
};
|
||||
|
||||
void JOYSTICK_Init(Section* sec) {
|
||||
IO_RegisterReadHandler(0x201,read_p201,"JOYSTICK");
|
||||
IO_RegisterWriteHandler(0x201,write_p201,"JOYSTICK");
|
||||
IO_RegisterReadHandler(0x201,read_p201,IO_MB);
|
||||
IO_RegisterWriteHandler(0x201,write_p201,IO_MB);
|
||||
stick[0].enabled=false;
|
||||
stick[1].enabled=false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* $Id: keyboard.cpp,v 1.21 2004-02-07 18:35:24 harekiet Exp $ */
|
||||
/* $Id: keyboard.cpp,v 1.22 2004-04-03 19:35:34 harekiet Exp $ */
|
||||
|
||||
#include <string.h>
|
||||
#include "dosbox.h"
|
||||
|
|
@ -147,7 +147,7 @@ void KEYBOARD_ReadKey(Bitu & scancode,Bitu & ascii,Bitu & mod) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_p60(Bit32u port) {
|
||||
static Bitu read_p60(Bitu port,Bitu iolen) {
|
||||
keyb.key_on_60 = false;
|
||||
switch (keyb.buf.state) {
|
||||
case STATE_NORMAL:
|
||||
|
|
@ -168,7 +168,7 @@ static Bit8u read_p60(Bit32u port) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void write_p60(Bit32u port,Bit8u val) {
|
||||
static void write_p60(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (keyb.command) {
|
||||
case CMD_NONE: /* None */
|
||||
KEYBOARD_ClrBuffer();
|
||||
|
|
@ -217,13 +217,13 @@ static void write_p60(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_p61(Bit32u port) {
|
||||
static Bitu read_p61(Bitu port,Bitu iolen) {
|
||||
port_61_data^=0x20;
|
||||
port_61_data^=0x10;
|
||||
return port_61_data;
|
||||
}
|
||||
|
||||
static void write_p61(Bit32u port,Bit8u val) {
|
||||
static void write_p61(Bitu port,Bitu val,Bitu iolen) {
|
||||
/*
|
||||
if (val & 128) if (!keyb.read_active) KEYBOARD_ReadBuffer();
|
||||
Keys should get acknowledged just by reading 0x60.
|
||||
|
|
@ -233,7 +233,7 @@ static void write_p61(Bit32u port,Bit8u val) {
|
|||
port_61_data=val;
|
||||
}
|
||||
|
||||
static void write_p64(Bit32u port,Bit8u val) {
|
||||
static void write_p64(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (val) {
|
||||
case 0xae: /* Activate keyboard */
|
||||
keyb.active=true;
|
||||
|
|
@ -261,7 +261,7 @@ static void write_p64(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_p64(Bit32u port) {
|
||||
static Bitu read_p64(Bitu port,Bitu iolen) {
|
||||
// Bit8u status= 0x1c | ((keyb.buf.used ||keyb.key_on_60)? 0x1 : 0x0);
|
||||
// Old one. Digitracker 2 doesn't like this. key_on_60 is much more advanged.
|
||||
Bit8u status= 0x1c | (keyb.key_on_60? 0x1 : 0x0);
|
||||
|
|
@ -420,12 +420,12 @@ void KEYBOARD_AddKey(KBD_KEYS keytype,Bitu unicode,Bitu mod,bool pressed) {
|
|||
}
|
||||
|
||||
void KEYBOARD_Init(Section* sec) {
|
||||
IO_RegisterWriteHandler(0x60,write_p60,"Keyboard");
|
||||
IO_RegisterReadHandler(0x60,read_p60,"Keyboard");
|
||||
IO_RegisterWriteHandler(0x61,write_p61,"Keyboard");
|
||||
IO_RegisterReadHandler(0x61,read_p61,"Keyboard");
|
||||
IO_RegisterWriteHandler(0x64,write_p64,"Keyboard");
|
||||
IO_RegisterReadHandler(0x64,read_p64,"Keyboard");
|
||||
IO_RegisterWriteHandler(0x60,write_p60,IO_MB);
|
||||
IO_RegisterReadHandler(0x60,read_p60,IO_MB);
|
||||
IO_RegisterWriteHandler(0x61,write_p61,IO_MB);
|
||||
IO_RegisterReadHandler(0x61,read_p61,IO_MB);
|
||||
IO_RegisterWriteHandler(0x64,write_p64,IO_MB);
|
||||
IO_RegisterReadHandler(0x64,read_p64,IO_MB);
|
||||
|
||||
port_61_data=0; /* Direct Speaker control and output disabled */
|
||||
// memset(&event_handlers,0,sizeof(event_handlers));
|
||||
|
|
|
|||
|
|
@ -512,14 +512,14 @@ void MEM_PhysWriteD(Bitu addr,Bit32u val) {
|
|||
}
|
||||
|
||||
|
||||
static void write_p92(Bit32u port,Bit8u val) {
|
||||
static void write_p92(Bitu port,Bitu val,Bitu iolen) {
|
||||
// Bit 0 = system reset (switch back to real mode)
|
||||
if (val&1) E_Exit("XMS: CPU reset via port 0x92 not supported.");
|
||||
memory.a20.controlport = val & ~2;
|
||||
MEM_A20_Enable((val & 2)>0);
|
||||
}
|
||||
|
||||
static Bit8u read_p92(Bit32u port) {
|
||||
static Bitu read_p92(Bitu port,Bitu iolen) {
|
||||
return memory.a20.controlport | (memory.a20.enabled ? 0x02 : 0);
|
||||
}
|
||||
|
||||
|
|
@ -589,8 +589,8 @@ void MEM_Init(Section * sec) {
|
|||
/* Reset some links */
|
||||
memory.links.used=0;
|
||||
// A20 Line - PS/2 system control port A
|
||||
IO_RegisterWriteHandler(0x92,write_p92,"Control Port");
|
||||
IO_RegisterReadHandler(0x92,read_p92,"Control Port");
|
||||
IO_RegisterWriteHandler(0x92,write_p92,IO_MB);
|
||||
IO_RegisterReadHandler(0x92,read_p92,IO_MB);
|
||||
MEM_A20_Enable(false);
|
||||
/* shutdown function */
|
||||
sec->AddDestroyFunction(&MEM_ShutDown);
|
||||
|
|
|
|||
|
|
@ -214,13 +214,13 @@ static void ClrQueue(void) {
|
|||
mpu.queue_pos=0;
|
||||
}
|
||||
|
||||
static Bit8u MPU401_ReadStatus(Bit32u port) {
|
||||
static Bitu MPU401_ReadStatus(Bitu port,Bitu iolen) {
|
||||
Bit8u ret=0x3f; /* Bits 6 and 7 clear */
|
||||
if (!mpu.queue_used) ret|=0x80;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void MPU401_WriteCommand(Bit32u port,Bit8u val) {
|
||||
static void MPU401_WriteCommand(Bitu port,Bitu val,Bitu iolen) {
|
||||
LOG(LOG_MISC,LOG_NORMAL)("MPU-401:Command %x",val);
|
||||
if (val && val<=0x2f) {
|
||||
switch (val&3) {
|
||||
|
|
@ -386,7 +386,7 @@ static void MPU401_WriteCommand(Bit32u port,Bit8u val) {
|
|||
QueueByte(MSG_CMD_ACK);
|
||||
}
|
||||
|
||||
static Bit8u MPU401_ReadData(Bit32u port) {
|
||||
static Bitu MPU401_ReadData(Bitu port,Bitu iolen) {
|
||||
Bit8u ret=MSG_CMD_ACK;
|
||||
if (mpu.queue_used) {
|
||||
ret=mpu.queue[mpu.queue_pos];
|
||||
|
|
@ -409,7 +409,7 @@ static Bit8u MPU401_ReadData(Bit32u port) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void MPU401_WriteData(Bit32u port,Bit8u val) {
|
||||
static void MPU401_WriteData(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (mpu.mode==M_UART) {MIDI_RawOutByte(val);return;}
|
||||
if (mpu.state.command_byte) MPU401_EOIHandler(); /* S101, Time Quest */
|
||||
switch (mpu.state.command_byte) {
|
||||
|
|
@ -613,8 +613,8 @@ static void UpdateTrack(Bit8u chan) {
|
|||
|
||||
static void UpdateConductor(void) {
|
||||
if (mpu.condbuf.type!=OVERFLOW) {
|
||||
MPU401_WriteCommand(0x331,mpu.condbuf.value[0]);
|
||||
if (mpu.state.command_byte) MPU401_WriteData(0x330,mpu.condbuf.value[1]);
|
||||
MPU401_WriteCommand(0x331,mpu.condbuf.value[0],1);
|
||||
if (mpu.state.command_byte) MPU401_WriteData(0x330,mpu.condbuf.value[1],1);
|
||||
}
|
||||
mpu.condbuf.vlength=0;
|
||||
mpu.condbuf.type=OVERFLOW;
|
||||
|
|
@ -727,10 +727,10 @@ void MPU401_Init(Section* sec) {
|
|||
|
||||
if (!MIDI_Available()) return;
|
||||
|
||||
IO_RegisterWriteHandler(0x330,&MPU401_WriteData,"MPU401");
|
||||
IO_RegisterWriteHandler(0x331,&MPU401_WriteCommand,"MPU401");
|
||||
IO_RegisterReadHandler(0x330,&MPU401_ReadData,"MPU401");
|
||||
IO_RegisterReadHandler(0x331,&MPU401_ReadStatus,"MPU401");
|
||||
IO_RegisterWriteHandler(0x330,&MPU401_WriteData,IO_MB);
|
||||
IO_RegisterWriteHandler(0x331,&MPU401_WriteCommand,IO_MB);
|
||||
IO_RegisterReadHandler(0x330,&MPU401_ReadData,IO_MB);
|
||||
IO_RegisterReadHandler(0x331,&MPU401_ReadStatus,IO_MB);
|
||||
|
||||
mpu.queue_used=0;
|
||||
mpu.queue_pos=0;
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* $Id: pic.cpp,v 1.19 2004-03-10 13:53:40 qbix79 Exp $ */
|
||||
/* $Id: pic.cpp,v 1.20 2004-04-03 19:34:10 harekiet Exp $ */
|
||||
|
||||
#include <list>
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ static struct {
|
|||
PICEntry * next_entry;
|
||||
} pic;
|
||||
|
||||
static void write_command(Bit32u port,Bit8u val) {
|
||||
static void write_command(Bitu port,Bitu val,Bitu iolen) {
|
||||
PIC_Controller * pic=&pics[port==0x20 ? 0 : 1];
|
||||
Bitu irq_base=port==0x20 ? 0 : 8;
|
||||
Bitu i;
|
||||
|
|
@ -125,7 +125,7 @@ static void write_command(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static void write_data(Bit32u port,Bit8u val) {
|
||||
static void write_data(Bitu port,Bitu val,Bitu iolen) {
|
||||
PIC_Controller * pic=&pics[port==0x21 ? 0 : 1];
|
||||
Bitu irq_base=(port==0x21) ? 0 : 8;
|
||||
Bitu i;
|
||||
|
|
@ -175,7 +175,7 @@ static void write_data(Bit32u port,Bit8u val) {
|
|||
}
|
||||
|
||||
|
||||
static Bit8u read_command(Bit32u port) {
|
||||
static Bitu read_command(Bitu port,Bitu iolen) {
|
||||
PIC_Controller * pic=&pics[port==0x20 ? 0 : 1];
|
||||
Bitu irq_base=(port==0x20) ? 0 : 8;
|
||||
Bitu i;Bit8u ret=0;Bit8u b=1;
|
||||
|
|
@ -193,7 +193,7 @@ static Bit8u read_command(Bit32u port) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
static Bit8u read_data(Bit32u port) {
|
||||
static Bitu read_data(Bitu port,Bitu iolen) {
|
||||
PIC_Controller * pic=&pics[port==0x21 ? 0 : 1];
|
||||
Bitu irq_base=(port==0x21) ? 0 : 8;
|
||||
Bitu i;Bit8u ret=0;Bit8u b=1;
|
||||
|
|
@ -460,14 +460,14 @@ void PIC_Init(Section* sec) {
|
|||
irqs[1].masked=false; /* Enable Keyboard IRQ */
|
||||
irqs[8].masked=false; /* Enable RTC IRQ */
|
||||
/* irqs[12].masked=false; moved to mouse.cpp */ /* Enable Mouse IRQ */
|
||||
IO_RegisterReadHandler(0x20,read_command,"Master PIC Command");
|
||||
IO_RegisterReadHandler(0x21,read_data,"Master PIC Data");
|
||||
IO_RegisterWriteHandler(0x20,write_command,"Master PIC Command");
|
||||
IO_RegisterWriteHandler(0x21,write_data,"Master PIC Data");
|
||||
IO_RegisterReadHandler(0xa0,read_command,"Slave PIC Command");
|
||||
IO_RegisterReadHandler(0xa1,read_data,"Slave PIC Data");
|
||||
IO_RegisterWriteHandler(0xa0,write_command,"Slave PIC Command");
|
||||
IO_RegisterWriteHandler(0xa1,write_data,"Slave PIC Data");
|
||||
IO_RegisterReadHandler(0x20,read_command,IO_MB);
|
||||
IO_RegisterReadHandler(0x21,read_data,IO_MB);
|
||||
IO_RegisterWriteHandler(0x20,write_command,IO_MB);
|
||||
IO_RegisterWriteHandler(0x21,write_data,IO_MB);
|
||||
IO_RegisterReadHandler(0xa0,read_command,IO_MB);
|
||||
IO_RegisterReadHandler(0xa1,read_data,IO_MB);
|
||||
IO_RegisterWriteHandler(0xa0,write_command,IO_MB);
|
||||
IO_RegisterWriteHandler(0xa1,write_data,IO_MB);
|
||||
/* Initialize the pic queue */
|
||||
for (i=0;i<PIC_QUEUESIZE-1;i++) {
|
||||
pic.entries[i].next=&pic.entries[i+1];
|
||||
|
|
|
|||
|
|
@ -936,7 +936,7 @@ static Bit8u MIXER_Read(void) {
|
|||
}
|
||||
|
||||
|
||||
static Bit8u read_sb(Bit32u port) {
|
||||
static Bitu read_sb(Bitu port,Bitu iolen) {
|
||||
switch (port-sb.hw.base) {
|
||||
case MIXER_INDEX:
|
||||
return sb.mixer.index;
|
||||
|
|
@ -968,7 +968,7 @@ static Bit8u read_sb(Bit32u port) {
|
|||
return 0xff;
|
||||
}
|
||||
|
||||
static void write_sb(Bit32u port,Bit8u val) {
|
||||
static void write_sb(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (port-sb.hw.base) {
|
||||
case DSP_RESET:
|
||||
DSP_DoReset(val);
|
||||
|
|
@ -1062,8 +1062,8 @@ void SBLASTER_Init(Section* sec) {
|
|||
|
||||
for (i=4;i<0xf;i++) {
|
||||
if (i==8 || i==9) continue;
|
||||
IO_RegisterReadHandler(sb.hw.base+i,read_sb,"SB");
|
||||
IO_RegisterWriteHandler(sb.hw.base+i,write_sb,"SB");
|
||||
IO_RegisterReadHandler(sb.hw.base+i,read_sb,IO_MB);
|
||||
IO_RegisterWriteHandler(sb.hw.base+i,write_sb,IO_MB);
|
||||
}
|
||||
PIC_RegisterIRQ(sb.hw.irq,0,"SB");
|
||||
DSP_Reset();
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static struct {
|
|||
|
||||
|
||||
|
||||
static void SN76496Write(Bit32u port,Bit8u data)
|
||||
static void SN76496Write(Bitu port,Bitu data,Bitu iolen)
|
||||
{
|
||||
struct SN76496 *R = &sn;
|
||||
|
||||
|
|
@ -301,7 +301,7 @@ void TANDYSOUND_Init(Section* sec) {
|
|||
Section_prop * section=static_cast<Section_prop *>(sec);
|
||||
if(!section->Get_bool("tandy")) return;
|
||||
|
||||
IO_RegisterWriteHandler(0xc0,SN76496Write,"Tandy Sound");
|
||||
IO_RegisterWriteHandler(0xc0,SN76496Write,IO_MB);
|
||||
|
||||
Bit32u sample_rate = section->Get_int("tandyrate");
|
||||
tandy.chan=MIXER_AddChannel(&SN76496Update,sample_rate,"TANDY");
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* $Id: timer.cpp,v 1.22 2004-03-03 12:37:12 qbix79 Exp $ */
|
||||
/* $Id: timer.cpp,v 1.23 2004-04-03 19:34:10 harekiet Exp $ */
|
||||
|
||||
#include "dosbox.h"
|
||||
#include "inout.h"
|
||||
|
|
@ -102,7 +102,7 @@ static void counter_latch(Bitu counter) {
|
|||
}
|
||||
|
||||
|
||||
static void write_latch(Bit32u port,Bit8u val) {
|
||||
static void write_latch(Bitu port,Bitu val,Bitu iolen) {
|
||||
Bitu counter=port-0x40;
|
||||
PIT_Block * p=&pit[counter];
|
||||
if(p->bcd == true) BIN2BCD(p->write_latch);
|
||||
|
|
@ -149,7 +149,7 @@ static void write_latch(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_latch(Bit32u port) {
|
||||
static Bitu read_latch(Bitu port,Bitu iolen) {
|
||||
Bit32u counter=port-0x40;
|
||||
if (pit[counter].go_read_latch == true)
|
||||
counter_latch(counter);
|
||||
|
|
@ -186,7 +186,7 @@ static Bit8u read_latch(Bit32u port) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void write_p43(Bit32u port,Bit8u val) {
|
||||
static void write_p43(Bitu port,Bitu val,Bitu iolen) {
|
||||
Bitu latch=(val >> 6) & 0x03;
|
||||
switch (latch) {
|
||||
case 0:
|
||||
|
|
@ -219,12 +219,12 @@ static void write_p43(Bit32u port,Bit8u val) {
|
|||
|
||||
|
||||
void TIMER_Init(Section* sect) {
|
||||
IO_RegisterWriteHandler(0x40,write_latch,"PIT Timer 0");
|
||||
IO_RegisterWriteHandler(0x42,write_latch,"PIT Timer 2");
|
||||
IO_RegisterWriteHandler(0x43,write_p43,"PIT Mode Control");
|
||||
IO_RegisterReadHandler(0x40,read_latch,"PIT Timer 0");
|
||||
// IO_RegisterReadHandler(0x41,read_p41,"PIT Timer 1");
|
||||
IO_RegisterReadHandler(0x42,read_latch,"PIT Timer 2");
|
||||
IO_RegisterWriteHandler(0x40,write_latch,IO_MB);
|
||||
IO_RegisterWriteHandler(0x42,write_latch,IO_MB);
|
||||
IO_RegisterWriteHandler(0x43,write_p43,IO_MB);
|
||||
IO_RegisterReadHandler(0x40,read_latch,IO_MB);
|
||||
// IO_RegisterReadHandler(0x41,read_p41,IO_MB);
|
||||
IO_RegisterReadHandler(0x42,read_latch,IO_MB);
|
||||
/* Setup Timer 0 */
|
||||
pit[0].cntr=0x10000;
|
||||
pit[0].write_state = 3;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ void VGA_ATTR_SetPalette(Bit8u index,Bit8u val) {
|
|||
VGA_DAC_CombineColor(index,val);
|
||||
}
|
||||
|
||||
void write_p3c0(Bit32u port,Bit8u val) {
|
||||
void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (!vga.internal.attrindex) {
|
||||
attr(index)=val & 0x1F;
|
||||
vga.internal.attrindex=true;
|
||||
|
|
@ -156,7 +156,7 @@ void write_p3c0(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
Bit8u read_p3c1(Bit32u port) {
|
||||
Bitu read_p3c1(Bitu port,Bitu iolen) {
|
||||
vga.internal.attrindex=false;
|
||||
switch (attr(index)) {
|
||||
/* Palette */
|
||||
|
|
@ -188,8 +188,8 @@ Bit8u read_p3c1(Bit32u port) {
|
|||
|
||||
void VGA_SetupAttr(void) {
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteHandler(0x3c0,write_p3c0,"VGA Attribute controller");
|
||||
IO_RegisterReadHandler(0x3c1,read_p3c1,"VGA Attribute Read");
|
||||
IO_RegisterWriteHandler(0x3c0,write_p3c0,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c1,read_p3c1,IO_MB);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -24,15 +24,15 @@
|
|||
|
||||
#define crtc(blah) vga.crtc.blah
|
||||
|
||||
void write_p3d4_vga(Bit32u port,Bit8u val) {
|
||||
void write_p3d4_vga(Bitu port,Bitu val,Bitu iolen) {
|
||||
crtc(index)=val;
|
||||
}
|
||||
|
||||
Bit8u read_p3d4_vga(Bit32u port) {
|
||||
Bitu read_p3d4_vga(Bitu port,Bitu iolen) {
|
||||
return crtc(index);
|
||||
}
|
||||
|
||||
void write_p3d5_vga(Bit32u port,Bit8u val) {
|
||||
void write_p3d5_vga(Bitu port,Bitu val,Bitu iolen) {
|
||||
// if (crtc(index)>0x18) LOG_MSG("VGA CRCT write %X to reg %X",val,crtc(index));
|
||||
switch(crtc(index)) {
|
||||
case 0x00: /* Horizontal Total Register */
|
||||
|
|
@ -509,7 +509,7 @@ void write_p3d5_vga(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
Bit8u read_p3d5_vga(Bit32u port) {
|
||||
Bitu read_p3d5_vga(Bitu port,Bitu iolen) {
|
||||
// LOG_MSG("VGA CRCT read from reg %X",crtc(index));
|
||||
switch(crtc(index)) {
|
||||
case 0x00: /* Horizontal Total Register */
|
||||
|
|
|
|||
|
|
@ -51,36 +51,36 @@ Note: Each read or write of this register will cycle through first the
|
|||
enum {DAC_READ,DAC_WRITE};
|
||||
|
||||
|
||||
static void write_p3c6(Bit32u port,Bit8u val) {
|
||||
static void write_p3c6(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (val!=0xff) LOG(LOG_VGAGFX,LOG_NORMAL)("VGA:Pel Mask not 0xff");
|
||||
vga.dac.pel_mask=val;
|
||||
}
|
||||
|
||||
|
||||
static Bit8u read_p3c6(Bit32u port) {
|
||||
static Bitu read_p3c6(Bitu port,Bitu iolen) {
|
||||
return vga.dac.pel_mask;
|
||||
}
|
||||
|
||||
|
||||
static void write_p3c7(Bit32u port,Bit8u val) {
|
||||
static void write_p3c7(Bitu port,Bitu val,Bitu iolen) {
|
||||
vga.dac.read_index=val;
|
||||
vga.dac.pel_index=0;
|
||||
vga.dac.state=DAC_READ;
|
||||
|
||||
}
|
||||
|
||||
static Bit8u read_p3c7(Bit32u port) {
|
||||
static Bitu read_p3c7(Bitu port,Bitu iolen) {
|
||||
if (vga.dac.state==DAC_READ) return 0x3;
|
||||
else return 0x0;
|
||||
}
|
||||
|
||||
static void write_p3c8(Bit32u port,Bit8u val) {
|
||||
static void write_p3c8(Bitu port,Bitu val,Bitu iolen) {
|
||||
vga.dac.write_index=val;
|
||||
vga.dac.pel_index=0;
|
||||
vga.dac.state=DAC_WRITE;
|
||||
}
|
||||
|
||||
static void write_p3c9(Bit32u port,Bit8u val) {
|
||||
static void write_p3c9(Bitu port,Bitu val,Bitu iolen) {
|
||||
val&=0x3f;
|
||||
switch (vga.dac.pel_index) {
|
||||
case 0:
|
||||
|
|
@ -121,7 +121,7 @@ static void write_p3c9(Bit32u port,Bit8u val) {
|
|||
};
|
||||
}
|
||||
|
||||
static Bit8u read_p3c9(Bit32u port) {
|
||||
static Bitu read_p3c9(Bitu port,Bitu iolen) {
|
||||
Bit8u ret;
|
||||
switch (vga.dac.pel_index) {
|
||||
case 0:
|
||||
|
|
@ -183,13 +183,13 @@ void VGA_SetupDAC(void) {
|
|||
vga.dac.write_index=0;
|
||||
if (machine==MCH_VGA) {
|
||||
/* Setup the DAC IO port Handlers */
|
||||
IO_RegisterWriteHandler(0x3c6,write_p3c6,"PEL Mask");
|
||||
IO_RegisterReadHandler(0x3c6,read_p3c6,"PEL Mask");
|
||||
IO_RegisterWriteHandler(0x3c7,write_p3c7,"PEL Read Mode");
|
||||
IO_RegisterReadHandler(0x3c7,read_p3c7,"PEL Status Mode");
|
||||
IO_RegisterWriteHandler(0x3c8,write_p3c8,"PEL Write Mode");
|
||||
IO_RegisterWriteHandler(0x3c9,write_p3c9,"PEL Data");
|
||||
IO_RegisterReadHandler(0x3c9,read_p3c9,"PEL Data");
|
||||
IO_RegisterWriteHandler(0x3c6,write_p3c6,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c6,read_p3c6,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3c7,write_p3c7,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c7,read_p3c7,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3c8,write_p3c8,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3c9,write_p3c9,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c9,read_p3c9,IO_MB);
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,15 +23,15 @@
|
|||
#define gfx(blah) vga.gfx.blah
|
||||
static bool index9warned=false;
|
||||
|
||||
static void write_p3ce(Bit32u port,Bit8u val) {
|
||||
static void write_p3ce(Bitu port,Bitu val,Bitu iolen) {
|
||||
gfx(index)=val & 0x0f;
|
||||
}
|
||||
|
||||
static Bit8u read_p3ce(Bit32u port) {
|
||||
static Bitu read_p3ce(Bitu port,Bitu iolen) {
|
||||
return gfx(index);
|
||||
}
|
||||
|
||||
static void write_p3cf(Bit32u port,Bit8u val) {
|
||||
static void write_p3cf(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (gfx(index)) {
|
||||
case 0: /* Set/Reset Register */
|
||||
gfx(set_reset)=val & 0x0f;
|
||||
|
|
@ -184,7 +184,7 @@ static void write_p3cf(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_p3cf(Bit32u port) {
|
||||
static Bitu read_p3cf(Bitu port,Bitu iolen) {
|
||||
switch (gfx(index)) {
|
||||
case 0: /* Set/Reset Register */
|
||||
return gfx(set_reset);
|
||||
|
|
@ -214,10 +214,10 @@ static Bit8u read_p3cf(Bit32u port) {
|
|||
|
||||
void VGA_SetupGFX(void) {
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteHandler(0x3ce,write_p3ce,"VGA Graphics Index");
|
||||
IO_RegisterWriteHandler(0x3cf,write_p3cf,"VGA Graphics Data");
|
||||
IO_RegisterReadHandler(0x3ce,read_p3ce,"Vga Graphics Index");
|
||||
IO_RegisterReadHandler(0x3cf,read_p3cf,"Vga Graphics Data");
|
||||
IO_RegisterWriteHandler(0x3ce,write_p3ce,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3cf,write_p3cf,IO_MB);
|
||||
IO_RegisterReadHandler(0x3ce,read_p3ce,IO_MB);
|
||||
IO_RegisterReadHandler(0x3cf,read_p3cf,IO_MB);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -23,17 +23,12 @@
|
|||
|
||||
static Bit8u flip=0;
|
||||
|
||||
void write_p3d4_vga(Bit32u port,Bit8u val);
|
||||
Bit8u read_p3d4_vga(Bit32u port);
|
||||
void write_p3d5_vga(Bit32u port,Bit8u val);
|
||||
Bit8u read_p3d5_vga(Bit32u port);
|
||||
void write_p3d4_vga(Bitu port,Bitu val,Bitu iolen);
|
||||
Bitu read_p3d4_vga(Bitu port,Bitu iolen);
|
||||
void write_p3d5_vga(Bitu port,Bitu val,Bitu iolen);
|
||||
Bitu read_p3d5_vga(Bitu port,Bitu iolen);
|
||||
|
||||
void write_p3d4_cga(Bit32u port,Bit8u val);
|
||||
Bit8u read_p3d4_cga(Bit32u port);
|
||||
void write_p3d5_cga(Bit32u port,Bit8u val);
|
||||
Bit8u read_p3d5_cga(Bit32u port);
|
||||
|
||||
static Bit8u read_p3da(Bit32u port) {
|
||||
static Bitu read_p3da(Bitu port,Bitu iolen) {
|
||||
vga.internal.attrindex=false;
|
||||
if (vga.config.retrace) {
|
||||
switch (machine) {
|
||||
|
|
@ -54,32 +49,32 @@ static Bit8u read_p3da(Bit32u port) {
|
|||
}
|
||||
|
||||
|
||||
static void write_p3c2(Bit32u port,Bit8u val) {
|
||||
static void write_p3c2(Bitu port,Bitu val,Bitu iolen) {
|
||||
vga.misc_output=val;
|
||||
if (val & 0x1) {
|
||||
IO_RegisterWriteHandler(0x3d4,write_p3d4_vga,"VGA:CRTC Index Select");
|
||||
IO_RegisterReadHandler(0x3d4,read_p3d4_vga,"VGA:CRTC Index Select");
|
||||
IO_RegisterWriteHandler(0x3d5,write_p3d5_vga,"VGA:CRTC Data Register");
|
||||
IO_RegisterReadHandler(0x3d5,read_p3d5_vga,"VGA:CRTC Data Register");
|
||||
IO_RegisterReadHandler(0x3da,read_p3da,"VGA Input Status 1");
|
||||
IO_RegisterWriteHandler(0x3d4,write_p3d4_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3d4,read_p3d4_vga,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3d5,write_p3d5_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3d5,read_p3d5_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3da,read_p3da,IO_MB);
|
||||
|
||||
IO_FreeWriteHandler(0x3b4);
|
||||
IO_FreeReadHandler(0x3b4);
|
||||
IO_FreeWriteHandler(0x3b5);
|
||||
IO_FreeReadHandler(0x3b5);
|
||||
IO_FreeReadHandler(0x3ba);
|
||||
IO_FreeWriteHandler(0x3b4,IO_MB);
|
||||
IO_FreeReadHandler(0x3b4,IO_MB);
|
||||
IO_FreeWriteHandler(0x3b5,IO_MB);
|
||||
IO_FreeReadHandler(0x3b5,IO_MB);
|
||||
IO_FreeReadHandler(0x3ba,IO_MB);
|
||||
} else {
|
||||
IO_RegisterWriteHandler(0x3b4,write_p3d4_vga,"VGA:CRTC Index Select");
|
||||
IO_RegisterReadHandler(0x3b4,read_p3d4_vga,"VGA:CRTC Index Select");
|
||||
IO_RegisterWriteHandler(0x3b5,write_p3d5_vga,"VGA:CRTC Data Register");
|
||||
IO_RegisterReadHandler(0x3b5,read_p3d5_vga,"VGA:CRTC Data Register");
|
||||
IO_RegisterReadHandler(0x3ba,read_p3da,"VGA Input Status 1");
|
||||
IO_RegisterWriteHandler(0x3b4,write_p3d4_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3b4,read_p3d4_vga,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3b5,write_p3d5_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3b5,read_p3d5_vga,IO_MB);
|
||||
IO_RegisterReadHandler(0x3ba,read_p3da,IO_MB);
|
||||
|
||||
IO_FreeWriteHandler(0x3d4);
|
||||
IO_FreeReadHandler(0x3d4);
|
||||
IO_FreeWriteHandler(0x3d5);
|
||||
IO_FreeReadHandler(0x3d5);
|
||||
IO_FreeReadHandler(0x3da);
|
||||
IO_FreeWriteHandler(0x3d4,IO_MB);
|
||||
IO_FreeReadHandler(0x3d4,IO_MB);
|
||||
IO_FreeWriteHandler(0x3d5,IO_MB);
|
||||
IO_FreeReadHandler(0x3d5,IO_MB);
|
||||
IO_FreeReadHandler(0x3da,IO_MB);
|
||||
}
|
||||
/*
|
||||
0 If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base Address=3Bxh.
|
||||
|
|
@ -95,7 +90,7 @@ static void write_p3c2(Bit32u port,Bit8u val) {
|
|||
}
|
||||
|
||||
|
||||
static Bit8u read_p3cc(Bit32u port) {
|
||||
static Bitu read_p3cc(Bitu port,Bitu iolen) {
|
||||
return vga.misc_output;
|
||||
}
|
||||
|
||||
|
|
@ -103,12 +98,12 @@ static Bit8u read_p3cc(Bit32u port) {
|
|||
|
||||
void VGA_SetupMisc(void) {
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteHandler(0x3c2,write_p3c2,"VGA Misc Output");
|
||||
IO_RegisterReadHandler(0x3cc,read_p3cc,"VGA Misc Output");
|
||||
IO_RegisterWriteHandler(0x3c2,write_p3c2,IO_MB);
|
||||
IO_RegisterReadHandler(0x3cc,read_p3cc,IO_MB);
|
||||
} else if (machine==MCH_CGA || machine==MCH_TANDY) {
|
||||
IO_RegisterReadHandler(0x3da,read_p3da,"VGA Input Status 1");
|
||||
IO_RegisterReadHandler(0x3da,read_p3da,IO_MB);
|
||||
} else if (machine==MCH_HERC) {
|
||||
IO_RegisterReadHandler(0x3ba,read_p3da,"VGA Input Status 1");
|
||||
IO_RegisterReadHandler(0x3ba,read_p3da,IO_MB);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,15 +21,15 @@
|
|||
#include "inout.h"
|
||||
#include "vga.h"
|
||||
|
||||
static void write_crtc_index_other(Bit32u port,Bit8u val) {
|
||||
static void write_crtc_index_other(Bitu port,Bitu val,Bitu iolen) {
|
||||
vga.other.index=val;
|
||||
}
|
||||
|
||||
static Bit8u read_crtc_index_other(Bit32u port) {
|
||||
static Bitu read_crtc_index_other(Bitu port,Bitu iolen) {
|
||||
return vga.other.index;
|
||||
}
|
||||
|
||||
static void write_crtc_data_other(Bit32u port,Bit8u val) {
|
||||
static void write_crtc_data_other(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (vga.other.index) {
|
||||
case 0x00: //Horizontal total
|
||||
if (vga.other.htotal ^ val) VGA_StartResize();
|
||||
|
|
@ -84,7 +84,7 @@ static void write_crtc_data_other(Bit32u port,Bit8u val) {
|
|||
LOG_MSG("Write %X to illgal index %x",val,vga.other.index);
|
||||
}
|
||||
}
|
||||
static Bit8u read_crtc_data_other(Bit32u port) {
|
||||
static Bitu read_crtc_data_other(Bitu port,Bitu iolen) {
|
||||
switch (vga.other.index) {
|
||||
case 0x00: //Horizontal total
|
||||
return vga.other.htotal;
|
||||
|
|
@ -115,6 +115,7 @@ static Bit8u read_crtc_data_other(Bit32u port) {
|
|||
default:
|
||||
LOG_MSG("Read from illgal index %x",vga.other.index);
|
||||
}
|
||||
return (Bitu)-1;
|
||||
}
|
||||
|
||||
static void write_color_select(Bit8u val) {
|
||||
|
|
@ -140,7 +141,6 @@ static void write_color_select(Bit8u val) {
|
|||
}
|
||||
}
|
||||
break;
|
||||
case M_CGA16:
|
||||
case M_TEXT:
|
||||
case M_TANDY16:
|
||||
break;
|
||||
|
|
@ -153,11 +153,6 @@ static void write_mode_control(Bit8u val) {
|
|||
VGA_SetBlinking((val & 0x20));
|
||||
if (val & 0x2) {
|
||||
if (val & 0x10) {
|
||||
if (val & 0x8) {
|
||||
VGA_SetMode(M_CGA16); //Video burst 16 160x200 color mode
|
||||
} else {
|
||||
VGA_SetMode(M_CGA2);
|
||||
}
|
||||
} else VGA_SetMode(M_CGA4);
|
||||
write_color_select(vga.tandy.color_select); //Setup the correct palette
|
||||
} else {
|
||||
|
|
@ -198,13 +193,17 @@ static void write_tandy_reg(Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static void write_cga(Bit32u port,Bit8u val) {
|
||||
static void write_cga(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (port) {
|
||||
case 0x3d8:
|
||||
vga.tandy.mode_control=val;
|
||||
if (vga.tandy.mode_control & 0x2) {
|
||||
if (vga.tandy.mode_control & 0x10) {
|
||||
VGA_SetMode(M_TANDY2);
|
||||
if (val & 0x8 && machine==MCH_CGA) {
|
||||
VGA_SetMode(M_CGA16); //Video burst 16 160x200 color mode
|
||||
} else {
|
||||
VGA_SetMode(M_TANDY2);
|
||||
}
|
||||
} else VGA_SetMode(M_TANDY4);
|
||||
write_color_select(vga.tandy.color_select);
|
||||
} else {
|
||||
|
|
@ -217,7 +216,7 @@ static void write_cga(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static void write_tandy(Bit32u port,Bit8u val) {
|
||||
static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (port) {
|
||||
case 0x3d8:
|
||||
vga.tandy.mode_control=val;
|
||||
|
|
@ -240,7 +239,7 @@ static void write_tandy(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static void write_hercules(Bit32u port,Bit8u val) {
|
||||
static void write_hercules(Bitu port,Bitu val,Bitu iolen) {
|
||||
switch (port) {
|
||||
case 0x3b8:
|
||||
if (vga.herc.enable_bits & 1) {
|
||||
|
|
@ -263,7 +262,7 @@ static void write_hercules(Bit32u port,Bit8u val) {
|
|||
}
|
||||
}
|
||||
|
||||
static Bit8u read_hercules(Bit32u port) {
|
||||
static Bitu read_hercules(Bitu port,Bitu iolen) {
|
||||
LOG_MSG("read from Herc port %x",port);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -280,28 +279,28 @@ void VGA_SetupOther(void) {
|
|||
for (i=0;i<256;i++) memcpy(&vga.draw.font[i*32],&int10_font_14[i*14],14);
|
||||
}
|
||||
if (machine==MCH_CGA) {
|
||||
IO_RegisterWriteBHandler(0x3d8,write_cga);
|
||||
IO_RegisterWriteBHandler(0x3d9,write_cga);
|
||||
IO_RegisterWriteHandler(0x3d8,write_cga,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3d9,write_cga,IO_MB);
|
||||
}
|
||||
if (machine==MCH_HERC) {
|
||||
vga.herc.enable_bits=0;
|
||||
vga.herc.mode_control=0x8;
|
||||
IO_RegisterWriteBHandler(0x3b8,write_hercules);
|
||||
IO_RegisterWriteBHandler(0x3bf,write_hercules);
|
||||
IO_RegisterWriteHandler(0x3b8,write_hercules,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3bf,write_hercules,IO_MB);
|
||||
}
|
||||
if (machine==MCH_TANDY) {
|
||||
IO_RegisterWriteBHandler(0x3d8,write_tandy);
|
||||
IO_RegisterWriteBHandler(0x3d9,write_tandy);
|
||||
IO_RegisterWriteBHandler(0x3de,write_tandy);
|
||||
IO_RegisterWriteBHandler(0x3df,write_tandy);
|
||||
IO_RegisterWriteBHandler(0x3da,write_tandy);
|
||||
IO_RegisterWriteHandler(0x3d8,write_tandy,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3d9,write_tandy,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3de,write_tandy,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3df,write_tandy,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3da,write_tandy,IO_MB);
|
||||
}
|
||||
if (machine==MCH_CGA || machine==MCH_HERC || machine==MCH_TANDY) {
|
||||
Bitu base=machine==MCH_HERC ? 0x3b4 : 0x3d4;
|
||||
IO_RegisterWriteBHandler(base,write_crtc_index_other);
|
||||
IO_RegisterWriteBHandler(base+1,write_crtc_data_other);
|
||||
IO_RegisterReadBHandler(base,read_crtc_index_other);
|
||||
IO_RegisterReadBHandler(base+1,read_crtc_data_other);
|
||||
IO_RegisterWriteHandler(base,write_crtc_index_other,IO_MB);
|
||||
IO_RegisterWriteHandler(base+1,write_crtc_data_other,IO_MB);
|
||||
IO_RegisterReadHandler(base,read_crtc_index_other,IO_MB);
|
||||
IO_RegisterReadHandler(base+1,read_crtc_data_other,IO_MB);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,15 +22,15 @@
|
|||
|
||||
#define seq(blah) vga.seq.blah
|
||||
|
||||
Bit8u read_p3c4(Bit32u port) {
|
||||
Bitu read_p3c4(Bitu port,Bitu iolen) {
|
||||
return seq(index);
|
||||
}
|
||||
|
||||
void write_p3c4(Bit32u port,Bit8u val) {
|
||||
void write_p3c4(Bitu port,Bitu val,Bitu iolen) {
|
||||
seq(index)=val;
|
||||
};
|
||||
|
||||
void write_p3c5(Bit32u port,Bit8u val) {
|
||||
void write_p3c5(Bitu port,Bitu val,Bitu iolen) {
|
||||
if (seq(index)>0x8 && vga.s3.pll.lock!=0x6) return;
|
||||
// LOG_MSG("SEQ WRITE reg %X val %X",seq(index),val);
|
||||
switch(seq(index)) {
|
||||
|
|
@ -127,7 +127,7 @@ void write_p3c5(Bit32u port,Bit8u val) {
|
|||
};
|
||||
|
||||
|
||||
Bit8u read_p3c5(Bit32u port) {
|
||||
Bitu read_p3c5(Bitu port,Bitu iolen) {
|
||||
// LOG_MSG("VGA:SEQ:Read from index %2X",seq(index));
|
||||
if (seq(index)>0x8 && vga.s3.pll.lock!=0x6) return seq(index);
|
||||
switch(seq(index)) {
|
||||
|
|
@ -168,10 +168,10 @@ Bit8u read_p3c5(Bit32u port) {
|
|||
|
||||
void VGA_SetupSEQ(void) {
|
||||
if (machine==MCH_VGA) {
|
||||
IO_RegisterWriteHandler(0x3c4,write_p3c4,"VGA:Sequencer Index");
|
||||
IO_RegisterWriteHandler(0x3c5,write_p3c5,"VGA:Sequencer Data");
|
||||
IO_RegisterReadHandler(0x3c4,read_p3c4,"VGA:Sequencer Index");
|
||||
IO_RegisterReadHandler(0x3c5,read_p3c5,"VGA:Sequencer Data");
|
||||
IO_RegisterWriteHandler(0x3c4,write_p3c4,IO_MB);
|
||||
IO_RegisterWriteHandler(0x3c5,write_p3c5,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c4,read_p3c4,IO_MB);
|
||||
IO_RegisterReadHandler(0x3c5,read_p3c5,IO_MB);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue