From b055c7a87f91b96e710b707abd39400795e32553 Mon Sep 17 00:00:00 2001
From: Ralf Grillenberger <h-a-l-9000@users.sourceforge.net>
Date: Sun, 4 Apr 2010 21:07:27 +0000
Subject: [PATCH] Fix vsync pulse position for CGA, Hercules, PCJr and Tandy
 machines. Set the display enable bit for mode 6.

Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3571
---
 src/ints/int10_modes.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ints/int10_modes.cpp b/src/ints/int10_modes.cpp
index b8eec1b4..e7777e17 100644
--- a/src/ints/int10_modes.cpp
+++ b/src/ints/int10_modes.cpp
@@ -475,7 +475,7 @@ bool INT10_SetVideoMode_OTHER(Bit16u mode,bool clearmem) {
 	//Vertical displayed
 	IO_WriteW(crtc_base,0x06 | (CurMode->vdispend) << 8);
 	//Vertical sync position
-	IO_WriteW(crtc_base,0x07 | (CurMode->vdispend+1) << 8);
+	IO_WriteW(crtc_base,0x07 | (CurMode->vdispend + ((CurMode->vtotal - CurMode->vdispend)/2)-1) << 8);
 	//Maximum scanline
 	Bit8u scanline,crtpage;
 	scanline=8;
@@ -504,7 +504,7 @@ bool INT10_SetVideoMode_OTHER(Bit16u mode,bool clearmem) {
 	//Setup the special registers for each machine type
 	Bit8u mode_control_list[0xa+1]={
 		0x2c,0x28,0x2d,0x29,	//0-3
-		0x2a,0x2e,0x16,0x29,	//4-7		
+		0x2a,0x2e,0x1e,0x29,	//4-7
 		0x2a,0x2b,0x3b			//8-a
 	};
 	Bit8u mode_control_list_pcjr[0xa+1]={