From b7040481ab7770b69cdf24f0e0d7660c1b38db8b Mon Sep 17 00:00:00 2001 From: Sjoerd van der Berg Date: Sun, 6 Apr 2003 08:36:37 +0000 Subject: [PATCH] Support for 0x0f prefixed 386 opcodes and added some new instructions Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@871 --- src/cpu/core_full/load.h | 29 +++++- src/cpu/core_full/op.h | 53 ++++++++++ src/cpu/core_full/optable.h | 191 +++++++++++++++++++++++++++++++++--- src/cpu/core_full/support.h | 16 +-- 4 files changed, 269 insertions(+), 20 deletions(-) diff --git a/src/cpu/core_full/load.h b/src/cpu/core_full/load.h index c3c8a23a..328540ba 100644 --- a/src/cpu/core_full/load.h +++ b/src/cpu/core_full/load.h @@ -8,6 +8,10 @@ l_MODRMswitch: case M_Ib: inst.op1.d=Fetchb(); break; + case M_Ebx: + if (inst.rm<0xc0) inst.op1.ds=(Bit8s)LoadMb(inst.rm_eaa); + else inst.op1.ds=(Bit8s)reg_8(inst.rm_eai); + break; case M_EbIb: inst.op2.d=Fetchb(); case M_Eb: @@ -38,6 +42,7 @@ l_MODRMswitch: case M_EwxIwx: inst.op2.ds=Fetchws(); l_M_Ewx: + case M_Ewx: if (inst.rm<0xc0) inst.op1.ds=(Bit16s)LoadMw(inst.rm_eaa); else inst.op1.ds=(Bit16s)reg_16(inst.rm_eai); break; @@ -46,10 +51,16 @@ l_M_Ewx: goto l_M_Ew; case M_EwIw: inst.op2.d=Fetchw(); - goto l_M_Ew; + goto l_M_Ew; + case M_EwGwCL: + inst.imm.d=reg_cl; + goto l_M_EwGw; + case M_EwGwIb: + inst.imm.d=Fetchb(); +l_M_EwGw: case M_EwGw: inst.op2.d=reg_16(inst.rm_index); -l_M_Ew: +l_M_Ew: case M_Ew: if (inst.rm<0xc0) inst.op1.d=LoadMw(inst.rm_eaa); else inst.op1.d=reg_16(inst.rm_eai); @@ -64,15 +75,27 @@ l_M_Ew: case M_Id: inst.op1.d=Fetchd(); break; + case M_EdxGdx: + inst.op2.ds=(Bit32s)reg_32(inst.rm_index); + case M_Edx: + if (inst.rm<0xc0) inst.op1.d=(Bit32s)LoadMd(inst.rm_eaa); + else inst.op1.d=(Bit32s)reg_32(inst.rm_eai); + break; case M_EdIbx: inst.op2.ds=Fetchbs(); goto l_M_Ed; case M_EdId: inst.op2.d=Fetchd(); goto l_M_Ed; + case M_EdGdCL: + inst.imm.d=reg_cl; + goto l_M_EdGd; + case M_EdGdIb: + inst.imm.d=Fetchb(); +l_M_EdGd: case M_EdGd: inst.op2.d=reg_32(inst.rm_index); -l_M_Ed: +l_M_Ed: case M_Ed: if (inst.rm<0xc0) inst.op1.d=LoadMd(inst.rm_eaa); else inst.op1.d=reg_32(inst.rm_eai); diff --git a/src/cpu/core_full/op.h b/src/cpu/core_full/op.h index e2c7426e..80179bad 100644 --- a/src/cpu/core_full/op.h +++ b/src/cpu/core_full/op.h @@ -127,6 +127,27 @@ switch (inst.code.op) { SARD(inst.op1.d,inst.op2.b,LoadD,SaveD); break; + case O_DSHLw: + { + DSHLW(inst.op1.w,inst.op2.w,inst.imm.b,,LoadD,SaveD); + break; + } + case O_DSHRw: + { + DSHRW(inst.op1.w,inst.op2.w,inst.imm.b,,LoadD,SaveD); + break; + } + case O_DSHLd: + { + DSHLD(inst.op1.d,inst.op2.d,inst.imm.b,,LoadD,SaveD); + break; + } + case O_DSHRd: + { + DSHRD(inst.op1.d,inst.op2.d,inst.imm.b,,LoadD,SaveD); + break; + } + case t_NEGb: flags.var1.b=inst.op1.b; inst.op1.b=flags.result.b=0-inst.op1.b; @@ -157,6 +178,18 @@ switch (inst.code.op) { flags.cf=true;flags.of=true; } break; + case O_IMULRd: + { + Bit64s res=(Bit64s)inst.op1.ds*(Bit64s)inst.op2.ds; + inst.op1.ds=(Bit32s)res; + flags.type=t_MUL; + if ((res>-((Bit64s)(2147483647)+1)) && (res<(Bit64s)2147483647)) { + flags.cf=false;flags.of=false; + } else { + flags.cf=true;flags.of=true; + } + break; + } case O_MULb: flags.type=t_MUL; reg_ax=reg_al*inst.op1.b; @@ -227,6 +260,16 @@ switch (inst.code.op) { if (quo!=reg_ax) { inst.op1.b=0;goto doint;} goto nextopcode; } + case O_DIVd: + { + if (!inst.op1.d) goto doint; + Bit64u val=(((Bit64u)reg_edx)<<32)|reg_eax; + Bit64u quo=val/inst.op1.d; + reg_edx=(Bit32u)(val % inst.op1.d); + reg_eax=(Bit32u)quo; + if (quo!=reg_eax) { inst.op1.b=0;goto doint;} + goto nextopcode; + } case O_IDIVb: { if (!inst.op1.b) goto doint; @@ -245,6 +288,16 @@ switch (inst.code.op) { if (quo!=(Bit16s)reg_ax) { inst.op1.b=0;goto doint;} goto nextopcode; } + case O_IDIVd: + { + if (!inst.op1.d) goto doint; + Bit64s val=(((Bit64u)reg_edx)<<32)|reg_eax; + Bit64s quo=val/inst.op1.ds; + reg_edx=(Bit32s)(val % inst.op1.ds); + reg_eax=(Bit32s)(quo); + if (quo!=(Bit32s)reg_eax) { inst.op1.b=0;goto doint;} + goto nextopcode; + } case O_AAM: reg_ah=reg_al / inst.op1.b; reg_al=reg_al % inst.op1.b; diff --git a/src/cpu/core_full/optable.h b/src/cpu/core_full/optable.h index 01f72660..032d392d 100644 --- a/src/cpu/core_full/optable.h +++ b/src/cpu/core_full/optable.h @@ -295,12 +295,12 @@ static OpCode OpCodeTable[1024]={ /* 0x1a0 - 0x1a7 */ {L_SEG ,0 ,S_PUSHw ,fs },{L_POPw ,0 ,S_SEGI ,fs }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_DSHLw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHLw ,S_Ew ,M_EwGwCL }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, /* 0x1a8 - 0x1af */ {L_SEG ,0 ,S_PUSHw ,gs },{L_POPw ,0 ,S_SEGI ,gs }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_DSHRw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHRw ,S_Ew ,M_EwGwCL }, {0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRw ,S_Gw ,M_EwxGwx }, /* 0x1b0 - 0x1b7 */ @@ -312,7 +312,7 @@ static OpCode OpCodeTable[1024]={ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,0 ,S_Gw ,M_Ebx },{L_MODRM ,0 ,S_Gw ,M_Ewx }, /* 0x1c0 - 0x1cc */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, @@ -363,23 +363,23 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,t_ADDb ,S_Eb ,M_EbGb },{L_MODRM ,t_ADDd ,S_Ed ,M_EdGd }, {L_MODRM ,t_ADDb ,S_Gb ,M_GbEb },{L_MODRM ,t_ADDd ,S_Gd ,M_GdEd }, {L_REGbIb ,t_ADDb ,S_REGb ,REGI_AL },{L_REGdId ,t_ADDd ,S_REGd ,REGI_AX }, -{L_SEG ,0 ,S_PUSHw,es },{L_POPw ,0 ,S_SEGI ,es }, +{L_SEG ,0 ,S_PUSHd,es },{L_POPd ,0 ,S_SEGI ,es }, /* 0x208 - 0x20f */ {L_MODRM ,t_ORb ,S_Eb ,M_EbGb },{L_MODRM ,t_ORd ,S_Ed ,M_EdGd }, {L_MODRM ,t_ORb ,S_Gb ,M_GbEb },{L_MODRM ,t_ORd ,S_Gd ,M_GdEd }, {L_REGbIb ,t_ORb ,S_REGb ,REGI_AL },{L_REGdId ,t_ORd ,S_REGd ,REGI_AX }, -{L_SEG ,0 ,S_PUSHw,cs },{L_DOUBLE ,0 ,0 ,0 }, +{L_SEG ,0 ,S_PUSHd,cs },{L_DOUBLE ,0 ,0 ,0 }, /* 0x210 - 0x217 */ {L_MODRM ,t_ADCb ,S_Eb ,M_EbGb },{L_MODRM ,t_ADCd ,S_Ed ,M_EdGd }, {L_MODRM ,t_ADCb ,S_Gb ,M_GbEb },{L_MODRM ,t_ADCd ,S_Gd ,M_GdEd }, {L_REGbIb ,t_ADCb ,S_REGb ,REGI_AL },{L_REGdId ,t_ADCd ,S_REGd ,REGI_AX }, -{L_SEG ,0 ,S_PUSHw,ss },{L_POPw ,0 ,S_SEGI ,ss }, +{L_SEG ,0 ,S_PUSHd,ss },{L_POPd ,0 ,S_SEGI ,ss }, /* 0x218 - 0x21f */ {L_MODRM ,t_SBBb ,S_Eb ,M_EbGb },{L_MODRM ,t_SBBd ,S_Ed ,M_EdGd }, {L_MODRM ,t_SBBb ,S_Gb ,M_GbEb },{L_MODRM ,t_SBBd ,S_Gd ,M_GdEd }, {L_REGbIb ,t_SBBb ,S_REGb ,REGI_AL },{L_REGdId ,t_SBBd ,S_REGd ,REGI_AX }, -{L_SEG ,0 ,S_PUSHw,ds },{L_POPw ,0 ,S_SEGI ,ds }, +{L_SEG ,0 ,S_PUSHd,ds },{L_POPd ,0 ,S_SEGI ,ds }, /* 0x220 - 0x227 */ {L_MODRM ,t_ANDb ,S_Eb ,M_EbGb },{L_MODRM ,t_ANDd ,S_Ed ,M_EdGd }, @@ -461,7 +461,7 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0 ,S_SEGm ,M_Ew },{L_MODRM ,0 ,S_Ed ,M_POPd }, /* 0x290 - 0x297 */ -{D_NOP ,0 ,0 ,0 },{L_REGw ,O_XCHG_EAX ,S_REGw ,REGI_CX}, +{D_NOP ,0 ,0 ,0 },{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_CX}, {L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_DX},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_BX}, {L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_SP},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_BP}, {L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_SI},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_DI}, @@ -538,14 +538,183 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0xb ,0 ,M_GRP },{L_MODRM ,0xd ,0 ,M_GRP }, - +/* 0x200 - 0x207 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x208 - 0x20f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x100 - 0x107 */ +/* 0x210 - 0x217 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x218 - 0x21f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x220 - 0x227 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x228 - 0x22f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x230 - 0x237 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x238 - 0x23f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x240 - 0x247 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x248 - 0x24f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x250 - 0x257 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x258 - 0x25f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x260 - 0x267 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x268 - 0x26f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x108 - 0x10f */ +/* 0x270 - 0x277 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x278 - 0x27f */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x280 - 0x287 */ +{L_Idx ,O_C_O ,S_C_ADDIP,0 },{L_Idx ,O_C_NO ,S_C_ADDIP,0 }, +{L_Idx ,O_C_B ,S_C_ADDIP,0 },{L_Idx ,O_C_NB ,S_C_ADDIP,0 }, +{L_Idx ,O_C_Z ,S_C_ADDIP,0 },{L_Idx ,O_C_NZ ,S_C_ADDIP,0 }, +{L_Idx ,O_C_BE ,S_C_ADDIP,0 },{L_Idx ,O_C_NBE ,S_C_ADDIP,0 }, +/* 0x288 - 0x28f */ +{L_Idx ,O_C_S ,S_C_ADDIP,0 },{L_Idx ,O_C_NS ,S_C_ADDIP,0 }, +{L_Idx ,O_C_P ,S_C_ADDIP,0 },{L_Idx ,O_C_NP ,S_C_ADDIP,0 }, +{L_Idx ,O_C_L ,S_C_ADDIP,0 },{L_Idx ,O_C_NL ,S_C_ADDIP,0 }, +{L_Idx ,O_C_LE ,S_C_ADDIP,0 },{L_Idx ,O_C_NLE ,S_C_ADDIP,0 }, + +/* 0x290 - 0x297 */ +{L_MODRM ,O_C_O ,S_C_Eb,0 },{L_MODRM ,O_C_NO ,S_C_Eb,0 }, +{L_MODRM ,O_C_B ,S_C_Eb,0 },{L_MODRM ,O_C_NB ,S_C_Eb,0 }, +{L_MODRM ,O_C_Z ,S_C_Eb,0 },{L_MODRM ,O_C_NZ ,S_C_Eb,0 }, +{L_MODRM ,O_C_BE ,S_C_Eb,0 },{L_MODRM ,O_C_NBE ,S_C_Eb,0 }, +/* 0x298 - 0x29f */ +{L_MODRM ,O_C_S ,S_C_Eb,0 },{L_MODRM ,O_C_NS ,S_C_Eb,0 }, +{L_MODRM ,O_C_P ,S_C_Eb,0 },{L_MODRM ,O_C_NP ,S_C_Eb,0 }, +{L_MODRM ,O_C_L ,S_C_Eb,0 },{L_MODRM ,O_C_NL ,S_C_Eb,0 }, +{L_MODRM ,O_C_LE ,S_C_Eb,0 },{L_MODRM ,O_C_NLE ,S_C_Eb,0 }, + +/* 0x2a0 - 0x2a7 */ +{L_SEG ,0 ,S_PUSHd ,fs },{L_POPd ,0 ,S_SEGI ,fs }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_DSHLd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHLd ,S_Ed ,M_EdGdCL }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x2a8 - 0x2af */ +{L_SEG ,0 ,S_PUSHd ,gs },{L_POPd ,0 ,S_SEGI ,gs }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_DSHRd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHRd ,S_Ed ,M_EdGdCL }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdxGdx }, + +/* 0x2b0 - 0x2b7 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_SEGFS ,S_SEGGd,M_Efd },{L_MODRM ,O_SEGGS ,S_SEGGd,M_Efd }, +{L_MODRM ,0 ,S_Gd ,M_Eb },{L_MODRM ,0 ,S_Gd ,M_Ew }, +/* 0x2b8 - 0x2bf */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,0 ,S_Gd ,M_Ebx },{L_MODRM ,0 ,S_Gd ,M_Ewx }, + +/* 0x2c0 - 0x2cc */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x2c8 - 0x2cf */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x2d0 - 0x2d7 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x2d8 - 0x2df */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x2e0 - 0x2ee */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x2e8 - 0x2ef */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x2f0 - 0x2fc */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x2f8 - 0x2ff */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, }; diff --git a/src/cpu/core_full/support.h b/src/cpu/core_full/support.h index 7dcee792..6df98558 100644 --- a/src/cpu/core_full/support.h +++ b/src/cpu/core_full/support.h @@ -65,6 +65,9 @@ enum { O_IDIVb,O_IDIVw,O_IDIVd, O_CBACK, + + O_DSHLw,O_DSHLd, + O_DSHRw,O_DSHRd, O_C_O ,O_C_NO ,O_C_B ,O_C_NB ,O_C_Z ,O_C_NZ ,O_C_BE ,O_C_NBE, O_C_S ,O_C_NS ,O_C_P ,O_C_NP ,O_C_L ,O_C_NL ,O_C_LE ,O_C_NLE, }; @@ -104,12 +107,13 @@ enum { enum { M_None=0, - M_Eb,M_Gb,M_EbGb,M_GbEb, - M_Ew,M_Gw,M_EwGw,M_GwEw,M_EwxGwx, - M_Ed,M_Gd,M_EdGd,M_GdEd, + M_Ebx,M_Eb,M_Gb,M_EbGb,M_GbEb, + M_Ewx,M_Ew,M_Gw,M_EwGw,M_GwEw,M_EwxGwx, + M_Edx,M_Ed,M_Gd,M_EdGd,M_GdEd,M_EdxGdx, + M_EbIb, - M_EwIw,M_EwIbx,M_EwxIbx,M_EwxIwx, - M_EdId,M_EdIbx, + M_EwIw,M_EwIbx,M_EwxIbx,M_EwxIwx,M_EwGwIb,M_EwGwCL, + M_EdId,M_EdIbx,M_EdGdIb,M_EdGdCL, M_Efw,M_Efd, @@ -141,7 +145,7 @@ static struct { Bit8u b;Bit8s bs; Bit16u w;Bit16s ws; Bit32u d;Bit32s ds; - } op1,op2; + } op1,op2,imm; Bitu new_flags; struct { EAPoint base;