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Fix for 32-bit mov [offset],segment doing 32-bit store, should be 16.

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1051
This commit is contained in:
Sjoerd van der Berg 2003-06-12 12:03:59 +00:00
parent 6daab43bf7
commit bb45fd24d7
4 changed files with 17 additions and 4 deletions
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10
src/cpu/core_full/op.h
View file

@ -616,6 +616,16 @@ switch (inst.code.op) {
LOG(LOG_CPU,LOG_ERROR)("Unhandled FPU ESCAPE %d",inst.code.save);
goto nextopcode;
#endif
case O_BOUNDw:
{
Bit16s bound_min, bound_max;
bound_min=LoadMw(inst.rm_eaa);
bound_max=LoadMw(inst.rm_eaa+2);
if ( (((Bit16s)inst.op1.w) < bound_min) || (((Bit16s)inst.op1.w) > bound_max) ) {
EXCEPTION(5);
}
}
break;
case 0:
break;
default:

5
src/cpu/core_full/optable.h
View file

@ -69,7 +69,7 @@ static OpCode OpCodeTable[1024]={
/* 0x60 - 0x67 */
{D_PUSHAw ,0 ,0 ,0 },{D_POPAw ,0 ,0 ,0 },
{L_MODRM ,O_BOUNDw ,0 ,0 },{L_MODRM ,O_ARPL ,S_Ew ,M_EwGw },
{L_MODRM ,O_BOUNDw ,0 ,M_Gw },{L_MODRM ,O_ARPL ,S_Ew ,M_EwGw },
{L_PRESEG ,0 ,0 ,fs },{L_PRESEG ,0 ,0 ,gs },
{L_PREOP ,0 ,0 ,0 },{L_PREADD ,0 ,0 ,0 },
/* 0x68 - 0x6f */
@ -455,8 +455,7 @@ static OpCode OpCodeTable[1024]={
/* 0x288 - 0x28f */
{L_MODRM ,0 ,S_Eb ,M_Gb },{L_MODRM ,0 ,S_Ed ,M_Gd },
{L_MODRM ,0 ,S_Gb ,M_Eb },{L_MODRM ,0 ,S_Gd ,M_Ed },
//TODO Check if the saving a segment in 32bit reg does zero extension?
{L_MODRM ,0 ,S_Ed ,M_SEG },{L_MODRM ,0 ,S_Gd ,M_EA },
{L_MODRM ,0 ,S_EdMw ,M_SEG },{L_MODRM ,0 ,S_Gd ,M_EA },
{L_MODRM ,0 ,S_SEGm ,M_Ew },{L_MODRM ,0 ,S_Ed ,M_POPd },
/* 0x290 - 0x297 */

4
src/cpu/core_full/save.h
View file

@ -33,6 +33,10 @@ switch (inst.code.save) {
if (inst.rm<0xc0) SaveMd(inst.rm_eaa,inst.op1.d);
else reg_32(inst.rm_eai)=inst.op1.d;
break;
case S_EdMw: /* Special one 16 to memory, 32 zero extend to reg */
if (inst.rm<0xc0) SaveMw(inst.rm_eaa,inst.op1.w);
else reg_32(inst.rm_eai)=inst.op1.d;
break;
case S_Gd:
reg_32(inst.rm_index)=inst.op1.d;
break;

2
src/cpu/core_full/support.h
View file

@ -100,7 +100,7 @@ enum {
S_C_Eb,
S_Eb,S_Gb,S_EbGb,
S_Ew,S_Gw,S_EwGw,
S_Ed,S_Gd,S_EdGd,
S_Ed,S_Gd,S_EdGd,S_EdMw,
S_REGb,S_REGw,S_REGd,