From bb7bd6c3be314c7ae3f5ad0aa5046c244fbc6b0c Mon Sep 17 00:00:00 2001 From: Sjoerd van der Berg Date: Sun, 13 Apr 2003 18:36:20 +0000 Subject: [PATCH] Changes for new flags Opcodes moved into instructions.h Added support for a load of protected mode related opcodes. Fixed some opcodes. Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@920 --- src/cpu/core_full.cpp | 18 ++- src/cpu/core_full/load.h | 125 ++++++-------- src/cpu/core_full/loadwrite.h | 73 +++++---- src/cpu/core_full/main.h | 0 src/cpu/core_full/op.h | 297 ++++++++++++++++++---------------- src/cpu/core_full/optable.h | 221 +++++++++++++------------ src/cpu/core_full/save.h | 32 ++-- src/cpu/core_full/string.h | 7 +- src/cpu/core_full/support.h | 33 +++- 9 files changed, 423 insertions(+), 383 deletions(-) delete mode 100644 src/cpu/core_full/main.h diff --git a/src/cpu/core_full.cpp b/src/cpu/core_full.cpp index 98aeb613..ec305518 100644 --- a/src/cpu/core_full.cpp +++ b/src/cpu/core_full.cpp @@ -32,6 +32,7 @@ static EAPoint IPPoint; #include "core_full/ea_lookup.h" #include "instructions.h" + static INLINE void DecodeModRM(void) { inst.rm=Fetchb(); inst.rm_index=(inst.rm >> 3) & 7; @@ -41,14 +42,25 @@ static INLINE void DecodeModRM(void) { if (inst.rm<0xc0) inst.rm_eaa=(inst.prefix & PREFIX_ADDR) ? RMAddress_32() : RMAddress_16(); } +#define EXCEPTION(blah) \ + { \ + Bit8u new_num=blah; \ + SaveIP(); \ + Interrupt(new_num); \ + LoadIP(); \ + goto nextopcode; \ + } Bitu Full_DeCode(void) { + LoadIP(); while (CPU_Cycles>0) { #if C_DEBUG cycle_count++; #endif CPU_Cycles--; + inst.entry=cpu.full.entry; + inst.prefix=cpu.full.prefix; restartopcode: inst.entry=(inst.entry & 0xffffff00) | Fetchb(); @@ -56,9 +68,7 @@ restartopcode: #include "core_full/load.h" #include "core_full/op.h" #include "core_full/save.h" -nextopcode: - inst.prefix=0; - inst.entry=0; +nextopcode:; } SaveIP(); return 0; @@ -67,4 +77,4 @@ nextopcode: void CPU_Core_Full_Start(void) { cpudecoder=&Full_DeCode; -} \ No newline at end of file +} diff --git a/src/cpu/core_full/load.h b/src/cpu/core_full/load.h index f547a012..cb2a0347 100644 --- a/src/cpu/core_full/load.h +++ b/src/cpu/core_full/load.h @@ -213,10 +213,8 @@ l_M_Ed: inst.op1.d=reg_32(inst.code.extra); break; case L_FLG: - inst.op1.d= (get_CF() << 0) | (get_PF() << 2) | (get_AF() << 4) | - (get_ZF() << 6) | (get_SF() << 7) | (flags.tf << 8) | - (flags.intf << 9) |(flags.df << 10) | (get_OF() << 11) | - (flags.io << 12) | (flags.nt <<14); + FILLFLAGS; + inst.op1.d = flags.word; break; case L_SEG: inst.op1.d=SegValue((SegNames)inst.code.extra); @@ -263,25 +261,47 @@ l_M_Ed: if (!get_OF()) goto nextopcode; inst.op1.d=4; break; - case L_IRETw: - inst.op1.d=Pop_16(); - inst.op2.d=Pop_16(); - { - Bitu temp=Pop_16(); - Save_Flagsw(temp); - } - break; + case D_IRETw: + CPU_IRET(false); + LoadIP(); + goto nextopcode; + case D_IRETd: + CPU_IRET(true); + LoadIP(); + goto nextopcode; + case D_RETFwIw: + CPU_RET(false,Fetchw()); + LoadIP(); + goto nextopcode; + case D_RETFw: + CPU_RET(false,0); + LoadIP(); + goto nextopcode; + case D_RETFdIw: + CPU_RET(true,Fetchw()); + LoadIP(); + goto nextopcode; + case D_RETFd: + CPU_RET(true,0); + LoadIP(); + goto nextopcode; /* Direct operations */ case L_STRING: #include "string.h" - goto nextopcode; + goto nextopcode; case D_PUSHAw: - Push_16(reg_ax);Push_16(reg_cx);Push_16(reg_dx);Push_16(reg_bx); - Push_16(reg_sp);Push_16(reg_bp);Push_16(reg_si);Push_16(reg_di); + { + Bit16u old_sp=reg_sp; + Push_16(reg_ax);Push_16(reg_cx);Push_16(reg_dx);Push_16(reg_bx); + Push_16(old_sp);Push_16(reg_bp);Push_16(reg_si);Push_16(reg_di); + } goto nextopcode; case D_PUSHAd: - Push_32(reg_eax);Push_32(reg_ecx);Push_32(reg_edx);Push_32(reg_ebx); - Push_32(reg_esp);Push_32(reg_ebp);Push_32(reg_esi);Push_32(reg_edi); + { + Bit32u old_esp=reg_esp; + Push_32(reg_eax);Push_32(reg_ecx);Push_32(reg_edx);Push_32(reg_ebx); + Push_32(old_esp);Push_32(reg_ebp);Push_32(reg_esi);Push_32(reg_edi); + } goto nextopcode; case D_POPAw: reg_di=Pop_16();reg_si=Pop_16();reg_bp=Pop_16();Pop_16();//Don't save SP @@ -310,36 +330,36 @@ l_M_Ed: else reg_edx=0; goto nextopcode; case D_CLI: - flags.intf=false; + SETFLAGBIT(IF,false); goto nextopcode; case D_STI: - flags.intf=true; - if (flags.intf && PIC_IRQCheck) { + SETFLAGBIT(IF,true); + if (PIC_IRQCheck) { SaveIP(); PIC_runIRQs(); LoadIP(); } goto nextopcode; case D_STC: - flags.cf=true; + SETFLAGBIT(CF,true); if (flags.type!=t_CF) flags.prev_type=flags.type; flags.type=t_CF; goto nextopcode; case D_CLC: - flags.cf=false; + SETFLAGBIT(CF,false); if (flags.type!=t_CF) flags.prev_type=flags.type; flags.type=t_CF; goto nextopcode; case D_CMC: - flags.cf=!get_CF(); + SETFLAGBIT(CF,!get_CF()); if (flags.type!=t_CF) flags.prev_type=flags.type; flags.type=t_CF; goto nextopcode; case D_CLD: - flags.df=false; + SETFLAGBIT(DF,false); goto nextopcode; case D_STD: - flags.df=true; + SETFLAGBIT(DF,true); goto nextopcode; case D_NOP: goto nextopcode; @@ -357,63 +377,16 @@ l_M_Ed: reg_bp=Pop_16(); goto nextopcode; case D_DAA: - if (((reg_al & 0x0F)>0x09) || get_AF()) { - reg_al+=0x06; - flags.af=true; - } else { - flags.af=false; - } - flags.cf=get_CF(); - if ((reg_al > 0x9F) || flags.cf) { - reg_al+=0x60; - flags.cf=true; - } else { - flags.cf=false; - } - flags.sf=(reg_al&0x80)>0; - flags.zf=(reg_al==0); - flags.type=t_UNKNOWN; + DAA(); goto nextopcode; case D_DAS: - if (((reg_al & 0x0f) > 9) || get_AF()) { - reg_al-=6; - flags.af=true; - } else { - flags.af=false; - } - if ((reg_al>0x9f) || get_CF()) { - reg_al-=0x60; - flags.cf=true; - } else { - flags.cf=false; - } - flags.type=t_UNKNOWN; + DAS(); goto nextopcode; case D_AAA: - if (get_AF() || ((reg_al & 0xf) > 9)) - { - reg_al += 6; - reg_ah += 1; - flags.af=true; - flags.cf=true; - } else { - flags.af=false; - flags.cf=false; - } - reg_al &= 0x0F; - flags.type=t_UNKNOWN; + AAA(); goto nextopcode; case D_AAS: - if (((reg_al & 0x0f)>9) || get_AF()) { - reg_ah--; - if (reg_al < 6) reg_ah--; - reg_al=(reg_al-6) & 0xF; - flags.af=flags.cf=true; - } else { - flags.af=flags.cf=false; - } - reg_al&=0xf; - flags.type=t_UNKNOWN; + AAS(); goto nextopcode; default: LOG(LOG_CPU|LOG_ERROR,"LOAD:Unhandled code %d opcode %X",inst.code.load,inst.entry); diff --git a/src/cpu/core_full/loadwrite.h b/src/cpu/core_full/loadwrite.h index 914ff2eb..c1e192fb 100644 --- a/src/cpu/core_full/loadwrite.h +++ b/src/cpu/core_full/loadwrite.h @@ -13,7 +13,7 @@ static INLINE Bit8u Fetchb() { IPPoint+=1; return temp; } - + static INLINE Bit16u Fetchw() { Bit16u temp=LoadMw(IPPoint); IPPoint+=2; @@ -37,39 +37,50 @@ static INLINE Bit32s Fetchds() { } static INLINE void Push_16(Bit16u blah) { - reg_sp-=2; - SaveMw(SegBase(ss)+reg_sp,blah); -}; + if (cpu.state & STATE_STACK32) { + reg_esp-=2; + SaveMw(SegBase(ss)+reg_esp,blah); + } else { + reg_sp-=2; + SaveMw(SegBase(ss)+reg_sp,blah); + } +} static INLINE void Push_32(Bit32u blah) { - reg_sp-=4; - SaveMd(SegBase(ss)+reg_sp,blah); -}; - -static INLINE Bit16u Pop_16() { - Bit16u temp=LoadMw(SegBase(ss)+reg_sp); - reg_sp+=2; - return temp; -}; - -static INLINE Bit32u Pop_32() { - Bit32u temp=LoadMd(SegBase(ss)+reg_sp); - reg_sp+=4; - return temp; -}; - - -#define Save_Flagsw(FLAGW) \ -{ \ - flags.type=t_UNKNOWN; \ - flags.cf =(FLAGW & 0x001)>0;flags.pf =(FLAGW & 0x004)>0; \ - flags.af =(FLAGW & 0x010)>0;flags.zf =(FLAGW & 0x040)>0; \ - flags.sf =(FLAGW & 0x080)>0;flags.tf =(FLAGW & 0x100)>0; \ - flags.intf =(FLAGW & 0x200)>0; \ - flags.df =(FLAGW & 0x400)>0;flags.of =(FLAGW & 0x800)>0; \ - flags.io =(FLAGW >> 12) & 0x03; \ - flags.nt =(FLAGW & 0x4000)>0; \ + if (cpu.state & STATE_STACK32) { + reg_esp-=4; + SaveMd(SegBase(ss)+reg_esp,blah); + } else { + reg_sp-=4; + SaveMd(SegBase(ss)+reg_sp,blah); + } } + +static INLINE Bit16u Pop_16(void) { + if (cpu.state & STATE_STACK32) { + Bit16u temp=LoadMw(SegBase(ss)+reg_esp); + reg_esp+=2; + return temp; + } else { + Bit16u temp=LoadMw(SegBase(ss)+reg_sp); + reg_sp+=2; + return temp; + } +} + +static INLINE Bit32u Pop_32(void) { + if (cpu.state & STATE_STACK32) { + Bit32u temp=LoadMd(SegBase(ss)+reg_esp); + reg_esp+=4; + return temp; + } else { + Bit32u temp=LoadMd(SegBase(ss)+reg_sp); + reg_sp+=4; + return temp; + } +} + + #if 0 if (flags.intf && PIC_IRQCheck) { \ SaveIP(); \ diff --git a/src/cpu/core_full/main.h b/src/cpu/core_full/main.h deleted file mode 100644 index e69de29b..00000000 diff --git a/src/cpu/core_full/op.h b/src/cpu/core_full/op.h index 1464bbdc..2c2f24bf 100644 --- a/src/cpu/core_full/op.h +++ b/src/cpu/core_full/op.h @@ -47,12 +47,12 @@ switch (inst.code.op) { flags.type=inst.code.op; break; case t_INCb: case t_INCw: case t_INCd: - flags.cf=get_CF(); + SETFLAGBIT(CF,get_CF()); inst.op1.d=flags.result.d=inst.op1.d+1; flags.type=inst.code.op; break; case t_DECb: case t_DECw: case t_DECd: - flags.cf=get_CF(); + SETFLAGBIT(CF,get_CF()); inst.op1.d=flags.result.d=inst.op1.d-1; flags.type=inst.code.op; break; @@ -170,150 +170,52 @@ switch (inst.code.op) { /* Special instructions */ case O_IMULRw: - inst.op1.ds=inst.op1.ds*inst.op2.ds; - flags.type=t_MUL; - if ((inst.op1.ds> -32768) && (inst.op1.ds<32767)) { - flags.cf=false;flags.of=false; - } else { - flags.cf=true;flags.of=true; - } + DIMULW(inst.op1.ws,inst.op1.ws,inst.op2.ws,LoadD,SaveD); break; case O_IMULRd: - { - Bit64s res=(Bit64s)inst.op1.ds*(Bit64s)inst.op2.ds; - inst.op1.ds=(Bit32s)res; - flags.type=t_MUL; - if ((res>-((Bit64s)(2147483647)+1)) && (res<(Bit64s)2147483647)) { - flags.cf=false;flags.of=false; - } else { - flags.cf=true;flags.of=true; - } - break; - } + DIMULD(inst.op1.ds,inst.op1.ds,inst.op2.ds,LoadD,SaveD); + break; case O_MULb: - flags.type=t_MUL; - reg_ax=reg_al*inst.op1.b; - flags.cf=flags.of=((reg_ax & 0xff00) !=0); + MULB(inst.op1.b,LoadD,0); goto nextopcode; case O_MULw: - { - Bit32u tempu=(Bit32u)reg_ax*(Bit32u)inst.op1.w; - reg_ax=(Bit16u)(tempu); - reg_dx=(Bit16u)(tempu >> 16); - flags.type=t_MUL; - flags.cf=flags.of=(reg_dx !=0); - goto nextopcode; - } + MULW(inst.op1.w,LoadD,0); + goto nextopcode; case O_MULd: - { - Bit64u tempu=(Bit64u)reg_eax*(Bit64u)inst.op1.d; - reg_eax=(Bit32u)(tempu); - reg_edx=(Bit32u)(tempu >> 32); - flags.type=t_MUL; - flags.cf=flags.of=(reg_edx !=0); - goto nextopcode; - } + MULD(inst.op1.d,LoadD,0); + goto nextopcode; case O_IMULb: - flags.type=t_MUL; - reg_ax=((Bit8s)reg_al)*inst.op1.bs; - flags.cf=flags.of=!((reg_ax & 0xff80)==0xff80 || (reg_ax & 0xff80)==0x0000); + IMULB(inst.op1.b,LoadD,0); goto nextopcode; case O_IMULw: - { - Bit32s temps=(Bit16s)reg_ax*inst.op1.ws; - reg_ax=(Bit16s)(temps); - reg_dx=(Bit16s)(temps >> 16); - flags.type=t_MUL; - flags.cf=flags.of=!((temps & 0xffffff80)==0xffffff80 || (temps & 0xffffff80)==0x0000); - goto nextopcode; - } + IMULW(inst.op1.w,LoadD,0); + goto nextopcode; case O_IMULd: - { - Bit64s temps=(Bit64s)((Bit32s)reg_eax)*(Bit64s)inst.op1.ds; - reg_eax=(Bit32u)(temps); - reg_edx=(Bit32u)(temps >> 32); - flags.type=t_MUL; - if ( (reg_edx==0xffffffff) && (reg_eax & 0x80000000) ) { - flags.cf=flags.of=false; - } else if ( (reg_edx==0x00000000) && (reg_eax<0x80000000) ) { - flags.cf=flags.of=false; - } else { - flags.cf=flags.of=true; - } - goto nextopcode; - } + IMULD(inst.op1.d,LoadD,0); + goto nextopcode; case O_DIVb: - { - if (!inst.op1.b) goto doint; - Bitu val=reg_ax;Bitu quo=val/inst.op1.b; - reg_ah=(Bit8u)(val % inst.op1.b); - reg_al=(Bit8u)quo; - if (quo!=reg_al) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + DIVB(inst.op1.b,LoadD,0); + goto nextopcode; case O_DIVw: - { - if (!inst.op1.w) goto doint; - Bitu val=(reg_dx<<16)|reg_ax;Bitu quo=val/inst.op1.w; - reg_dx=(Bit16u)(val % inst.op1.w); - reg_ax=(Bit16u)quo; - if (quo!=reg_ax) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + DIVW(inst.op1.w,LoadD,0); + goto nextopcode; case O_DIVd: - { - if (!inst.op1.d) goto doint; - Bit64u val=(((Bit64u)reg_edx)<<32)|reg_eax; - Bit64u quo=val/inst.op1.d; - reg_edx=(Bit32u)(val % inst.op1.d); - reg_eax=(Bit32u)quo; - if (quo!=(Bit64u)reg_eax) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + DIVD(inst.op1.d,LoadD,0); + goto nextopcode; case O_IDIVb: - { - if (!inst.op1.b) goto doint; - Bits val=(Bit16s)reg_ax;Bits quo=val/inst.op1.bs; - reg_ah=(Bit8s)(val % inst.op1.bs); - reg_al=(Bit8s)quo; - if (quo!=(Bit8s)reg_al) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + IDIVB(inst.op1.b,LoadD,0); + goto nextopcode; case O_IDIVw: - { - if (!inst.op1.w) goto doint; - Bits val=(Bit32s)((reg_dx<<16)|reg_ax);Bits quo=val/inst.op1.ws; - reg_dx=(Bit16u)(val % inst.op1.ws); - reg_ax=(Bit16s)quo; - if (quo!=(Bit16s)reg_ax) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + IDIVW(inst.op1.w,LoadD,0); + goto nextopcode; case O_IDIVd: - { - if (!inst.op1.d) goto doint; - Bit64s val=(((Bit64u)reg_edx)<<32)|reg_eax; - Bit64s quo=val/inst.op1.ds; - reg_edx=(Bit32s)(val % inst.op1.ds); - reg_eax=(Bit32s)(quo); - if (quo!=(Bit64s)((Bit32s)reg_eax)) { inst.op1.b=0;goto doint;} - goto nextopcode; - } + IDIVD(inst.op1.d,LoadD,0); + goto nextopcode; case O_AAM: - reg_ah=reg_al / inst.op1.b; - reg_al=reg_al % inst.op1.b; - flags.type=t_UNKNOWN; - flags.sf=(reg_ah & 0x80) > 0; - flags.zf=(reg_ax == 0); - //TODO PF - flags.pf=0; + AAM(inst.op1.b); goto nextopcode; case O_AAD: - reg_al=reg_ah*inst.op1.b+reg_al; - reg_ah=0; - flags.cf=(reg_al>=0x80); - flags.zf=(reg_al==0); - //TODO PF - flags.type=t_UNKNOWN; + AAD(inst.op1.b); goto nextopcode; case O_C_O: inst.cond=get_OF(); break; @@ -363,19 +265,37 @@ switch (inst.code.op) { case O_SEGGS: inst.code.extra=gs; break; - - + case O_SEGSS: + inst.code.extra=ss; + break; + case O_LOOP: - if (--reg_cx) break; + if (inst.prefix & PREFIX_ADDR) { + if (--reg_ecx) break; + } else { + if (--reg_cx) break; + } goto nextopcode; case O_LOOPZ: - if (--reg_cx && get_ZF()) break; + if (inst.prefix & PREFIX_ADDR) { + if (--reg_ecx && get_ZF()) break; + } else { + if (--reg_cx && get_ZF()) break; + } goto nextopcode; case O_LOOPNZ: - if (--reg_cx && !get_ZF()) break; + if (inst.prefix & PREFIX_ADDR) { + if (--reg_ecx && !get_ZF()) break; + } else { + if (--reg_cx && !get_ZF()) break; + } goto nextopcode; case O_JCXZ: - if (reg_cx) goto nextopcode; + if (inst.prefix & PREFIX_ADDR) { + if (reg_ecx) goto nextopcode; + } else { + if (reg_cx) goto nextopcode; + } break; case O_XCHG_AX: { @@ -391,16 +311,28 @@ switch (inst.code.op) { inst.op1.d=temp; break; } - case O_CALL_N: + case O_CALLNw: SaveIP(); Push_16(reg_ip); break; - case O_CALL_F: - Push_16(SegValue(cs)); + case O_CALLNd: SaveIP(); - Push_16(reg_ip); + Push_32(reg_eip); break; -doint: + case O_CALLFw: + SaveIP(); + CPU_CALL(false,inst.op2.d,inst.op1.d); + LoadIP(); + goto nextopcode; + case O_CALLFd: + SaveIP(); + CPU_CALL(true,inst.op2.d,inst.op1.d); + LoadIP(); + goto nextopcode; + case O_JMPFw: + CPU_JMP(false,inst.op2.d,inst.op1.d); + LoadIP(); + goto nextopcode; case O_INT: SaveIP(); #if C_DEBUG @@ -448,6 +380,95 @@ doint: } else { E_Exit("Too high CallBack Number %d called",inst.op1.d); } + case O_GRP6w: + case O_GRP6d: + switch (inst.rm_index) { + case 0x02: /* LLDT */ + CPU_LLDT(inst.op1.d); + goto nextopcode; /* Else value will saved */ + default: + LOG(LOG_ERROR|LOG_CPU,"Group 6 Illegal subfunction %X",inst.rm_index); + } + break; + case O_GRP7w: + case O_GRP7d: + switch (inst.rm_index) { + case 0: /* SGDT */ + { + Bitu limit,base; + CPU_SGDT(limit,base); + SaveMw(inst.rm_eaa,limit); + SaveMd(inst.rm_eaa+2,base); + break; + } + case 1: /* SIDT */ + { + Bitu limit,base; + CPU_SIDT(limit,base); + SaveMw(inst.rm_eaa,limit); + SaveMd(inst.rm_eaa+2,base); + break; + } + case 2: /* LGDT */ + CPU_LGDT(LoadMw(inst.rm_eaa),LoadMd(inst.rm_eaa+2)&((inst.code.op == O_GRP7w) ? 0xFFFFFF : 0xFFFFFFFF)); + break; + case 3: /* LIDT */ + CPU_LIDT(LoadMw(inst.rm_eaa),LoadMd(inst.rm_eaa+2)&((inst.code.op == O_GRP7w) ? 0xFFFFFF : 0xFFFFFFFF)); + break; + case 4: /* SMSW */ + { + Bitu word;CPU_SMSW(word); + SaveMw(inst.rm_eaa,word); + break; + } + case 6: /* LMSW */ + { + Bitu word=LoadMw(inst.rm_eaa); + CPU_LMSW(word); + break; + } + default: + LOG(LOG_ERROR|LOG_CPU,"Group 7 Illegal subfunction %X",inst.rm_index); + } + break; + case O_M_Cd_Rd: + CPU_SET_CRX(inst.rm_index,inst.op1.d); + break; + case O_M_Rd_Cd: + inst.op1.d=CPU_GET_CRX(inst.rm_index); + break; + case O_LAR: + { + Bitu ar;CPU_LAR(inst.op1.d,ar); + inst.op2.d=ar; + } + break; + case O_BTd: + case O_BTSd: + case O_BTCd: + case O_BTRd: + { + Bitu val;PhysPt read; + Bitu mask=1 << (inst.op1.d & 31); + FILLFLAGS; + if (inst.rm<0xc0) { + read=inst.rm_eaa+4*(inst.op1.d / 32); + val=mem_readd(read); + } else { + val=reg_32(inst.rm_eai); + } + SETFLAGBIT(CF,(val&mask)>0); + if (inst.code.op==O_BTSd) val|=mask; + if (inst.code.op==O_BTRd) val&=~mask; + if (inst.code.op==O_BTCd) val^=mask; + if (inst.code.op==O_BTd) break; + if (inst.rm<0xc0) { + mem_writed(read,val); + } else { + reg_32(inst.rm_eai)=val; + } + } + break; case 0: break; default: diff --git a/src/cpu/core_full/optable.h b/src/cpu/core_full/optable.h index 032d392d..ad76da33 100644 --- a/src/cpu/core_full/optable.h +++ b/src/cpu/core_full/optable.h @@ -80,15 +80,15 @@ static OpCode OpCodeTable[1024]={ /* 0x70 - 0x77 */ -{L_Ibx ,O_C_O ,S_C_ADDIP,0 },{L_Ibx ,O_C_NO ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_B ,S_C_ADDIP,0 },{L_Ibx ,O_C_NB ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_Z ,S_C_ADDIP,0 },{L_Ibx ,O_C_NZ ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_BE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NBE ,S_C_ADDIP,0 }, +{L_Ibx ,O_C_O ,S_C_AIPw,0 },{L_Ibx ,O_C_NO ,S_C_AIPw,0 }, +{L_Ibx ,O_C_B ,S_C_AIPw,0 },{L_Ibx ,O_C_NB ,S_C_AIPw,0 }, +{L_Ibx ,O_C_Z ,S_C_AIPw,0 },{L_Ibx ,O_C_NZ ,S_C_AIPw,0 }, +{L_Ibx ,O_C_BE ,S_C_AIPw,0 },{L_Ibx ,O_C_NBE ,S_C_AIPw,0 }, /* 0x78 - 0x7f */ -{L_Ibx ,O_C_S ,S_C_ADDIP,0 },{L_Ibx ,O_C_NS ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_P ,S_C_ADDIP,0 },{L_Ibx ,O_C_NP ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_L ,S_C_ADDIP,0 },{L_Ibx ,O_C_NL ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_LE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NLE ,S_C_ADDIP,0 }, +{L_Ibx ,O_C_S ,S_C_AIPw,0 },{L_Ibx ,O_C_NS ,S_C_AIPw,0 }, +{L_Ibx ,O_C_P ,S_C_AIPw,0 },{L_Ibx ,O_C_NP ,S_C_AIPw,0 }, +{L_Ibx ,O_C_L ,S_C_AIPw,0 },{L_Ibx ,O_C_NL ,S_C_AIPw,0 }, +{L_Ibx ,O_C_LE ,S_C_AIPw,0 },{L_Ibx ,O_C_NLE ,S_C_AIPw,0 }, /* 0x80 - 0x87 */ @@ -109,7 +109,7 @@ static OpCode OpCodeTable[1024]={ {L_REGw ,O_XCHG_AX ,S_REGw ,REGI_SI},{L_REGw ,O_XCHG_AX ,S_REGw ,REGI_DI}, /* 0x98 - 0x9f */ {D_CBW ,0 ,0 ,0 },{D_CWD ,0 ,0 ,0 }, -{L_Ifw ,O_CALL_F ,S_CSIP ,0 },{L_ERROR ,0 ,0 ,0 }, +{L_Ifw ,O_CALLFw ,0 ,0 },{L_ERROR ,0 ,0 ,0 }, {L_FLG ,0 ,S_PUSHw,0 },{L_POPw ,0 ,S_FLGw ,0 }, {L_REGb ,0 ,S_FLGb ,REGI_AH},{L_FLG ,0 ,S_REGb ,REGI_AH}, @@ -142,9 +142,9 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0 ,S_Eb ,M_Ib },{L_MODRM ,0 ,S_Ew ,M_Iw }, /* 0xc8 - 0xcf */ {D_ENTERw ,0 ,0 ,0 },{D_LEAVEw ,0 ,0 ,0 }, -{L_POPfw ,0 ,S_CSIPIw,0 },{L_POPfw ,0 ,S_CSIP ,0 }, +{D_RETFwIw ,0 ,0 ,0 },{D_RETFw ,0 ,0 ,0 }, {L_VAL ,O_INT ,0 ,3 },{L_Ib ,O_INT ,0 ,0 }, -{L_INTO ,O_INT ,0 ,0 },{L_IRETw ,0 ,S_CSIP ,0 }, +{L_INTO ,O_INT ,0 ,0 },{D_IRETw ,0 ,0 ,0 }, /* 0xd0 - 0xd7 */ {L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,6 ,0 ,M_GRP_1 }, @@ -159,13 +159,13 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 }, /* 0xe0 - 0xe7 */ -{L_Ibx ,O_LOOPNZ ,S_ADDIP,0 },{L_Ibx ,O_LOOPZ ,S_ADDIP,0 }, -{L_Ibx ,O_LOOP ,S_ADDIP,0 },{L_Ibx ,O_JCXZ ,S_ADDIP,0 }, +{L_Ibx ,O_LOOPNZ ,S_AIPw ,0 },{L_Ibx ,O_LOOPZ ,S_AIPw ,0 }, +{L_Ibx ,O_LOOP ,S_AIPw ,0 },{L_Ibx ,O_JCXZ ,S_AIPw ,0 }, {L_Ib ,O_INb ,0 ,0 },{L_Ib ,O_INw ,0 ,0 }, {L_Ib ,O_OUTb ,0 ,0 },{L_Ib ,O_OUTw ,0 ,0 }, /* 0xe8 - 0xef */ -{L_Iw ,O_CALL_N ,S_ADDIP,0 },{L_Iwx ,0 ,S_ADDIP,0 }, -{L_Ifw ,0 ,S_CSIP ,0 },{L_Ibx ,0 ,S_ADDIP,0 }, +{L_Iw ,O_CALLNw ,S_AIPw ,0 },{L_Iwx ,0 ,S_AIPw ,0 }, +{L_Ifw ,O_JMPFw ,0 ,0 },{L_Ibx ,0 ,S_AIPw ,0 }, {L_REGw ,O_INb ,0 ,REGI_DX},{L_REGw ,O_INw ,0 ,REGI_DX}, {L_REGw ,O_OUTb ,0 ,REGI_DX},{L_REGw ,O_OUTw ,0 ,REGI_DX}, @@ -181,7 +181,7 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0xb ,0 ,M_GRP },{L_MODRM ,0xc ,0 ,M_GRP }, /* 0x100 - 0x107 */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_GRP6w ,0 ,0 },{L_MODRM ,O_GRP7w ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, @@ -203,8 +203,8 @@ static OpCode OpCodeTable[1024]={ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, /* 0x120 - 0x127 */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_M_Rd_Cd ,S_Ed ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_M_Cd_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, @@ -271,15 +271,15 @@ static OpCode OpCodeTable[1024]={ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, /* 0x180 - 0x187 */ -{L_Iwx ,O_C_O ,S_C_ADDIP,0 },{L_Iwx ,O_C_NO ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_B ,S_C_ADDIP,0 },{L_Iwx ,O_C_NB ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_Z ,S_C_ADDIP,0 },{L_Iwx ,O_C_NZ ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_BE ,S_C_ADDIP,0 },{L_Iwx ,O_C_NBE ,S_C_ADDIP,0 }, +{L_Iwx ,O_C_O ,S_C_AIPw,0 },{L_Iwx ,O_C_NO ,S_C_AIPw,0 }, +{L_Iwx ,O_C_B ,S_C_AIPw,0 },{L_Iwx ,O_C_NB ,S_C_AIPw,0 }, +{L_Iwx ,O_C_Z ,S_C_AIPw,0 },{L_Iwx ,O_C_NZ ,S_C_AIPw,0 }, +{L_Iwx ,O_C_BE ,S_C_AIPw,0 },{L_Iwx ,O_C_NBE ,S_C_AIPw,0 }, /* 0x188 - 0x18f */ -{L_Iwx ,O_C_S ,S_C_ADDIP,0 },{L_Iwx ,O_C_NS ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_P ,S_C_ADDIP,0 },{L_Iwx ,O_C_NP ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_L ,S_C_ADDIP,0 },{L_Iwx ,O_C_NL ,S_C_ADDIP,0 }, -{L_Iwx ,O_C_LE ,S_C_ADDIP,0 },{L_Iwx ,O_C_NLE ,S_C_ADDIP,0 }, +{L_Iwx ,O_C_S ,S_C_AIPw,0 },{L_Iwx ,O_C_NS ,S_C_AIPw,0 }, +{L_Iwx ,O_C_P ,S_C_AIPw,0 },{L_Iwx ,O_C_NP ,S_C_AIPw,0 }, +{L_Iwx ,O_C_L ,S_C_AIPw,0 },{L_Iwx ,O_C_NL ,S_C_AIPw,0 }, +{L_Iwx ,O_C_LE ,S_C_AIPw,0 },{L_Iwx ,O_C_NLE ,S_C_AIPw,0 }, /* 0x190 - 0x197 */ {L_MODRM ,O_C_O ,S_C_Eb,0 },{L_MODRM ,O_C_NO ,S_C_Eb,0 }, @@ -294,23 +294,23 @@ static OpCode OpCodeTable[1024]={ /* 0x1a0 - 0x1a7 */ {L_SEG ,0 ,S_PUSHw ,fs },{L_POPw ,0 ,S_SEGI ,fs }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_BTw ,0 ,0 }, {L_MODRM ,O_DSHLw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHLw ,S_Ew ,M_EwGwCL }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, /* 0x1a8 - 0x1af */ {L_SEG ,0 ,S_PUSHw ,gs },{L_POPw ,0 ,S_SEGI ,gs }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_BTSw ,0 ,0 }, {L_MODRM ,O_DSHRw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHRw ,S_Ew ,M_EwGwCL }, {0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRw ,S_Gw ,M_EwxGwx }, /* 0x1b0 - 0x1b7 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_SEGSS ,S_SEGGw,M_Efw },{L_MODRM ,O_BTRw ,0 ,0 }, {L_MODRM ,O_SEGFS ,S_SEGGw,M_Efw },{L_MODRM ,O_SEGGS ,S_SEGGw,M_Efw }, {L_MODRM ,0 ,S_Gw ,M_Eb },{L_MODRM ,0 ,S_Gw ,M_Ew }, /* 0x1b8 - 0x1bf */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,0xe ,0 ,M_GRP },{L_MODRM ,O_BTCw ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {L_MODRM ,0 ,S_Gw ,M_Ebx },{L_MODRM ,0 ,S_Gw ,M_Ewx }, @@ -429,8 +429,7 @@ static OpCode OpCodeTable[1024]={ {D_PUSHAd ,0 ,0 ,0 },{D_POPAd ,0 ,0 ,0 }, {L_MODRM ,O_BOUNDd ,0 ,0 },{0 ,0 ,0 ,0 }, {L_PRESEG ,0 ,0 ,fs },{L_PRESEG ,0 ,0 ,gs }, -//TODO check ox66 0x66 prefix -{0 ,0 ,0 ,0 },{L_PREADD ,0 ,0 ,0 }, +{L_PREOP ,0 ,0 ,0 },{L_PREADD ,0 ,0 ,0 }, /* 0x268 - 0x26f */ {L_Id ,0 ,S_PUSHd,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdId}, {L_Ibx ,0 ,S_PUSHd,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdIbx}, @@ -438,15 +437,15 @@ static OpCode OpCodeTable[1024]={ {L_STRING ,R_OUTSB ,0 ,0 },{L_STRING ,R_OUTSD ,0 ,0 }, /* 0x270 - 0x277 */ -{L_Ibx ,O_C_O ,S_C_ADDIP,0 },{L_Ibx ,O_C_NO ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_B ,S_C_ADDIP,0 },{L_Ibx ,O_C_NB ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_Z ,S_C_ADDIP,0 },{L_Ibx ,O_C_NZ ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_BE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NBE ,S_C_ADDIP,0 }, +{L_Ibx ,O_C_O ,S_C_AIPd,0 },{L_Ibx ,O_C_NO ,S_C_AIPd,0 }, +{L_Ibx ,O_C_B ,S_C_AIPd,0 },{L_Ibx ,O_C_NB ,S_C_AIPd,0 }, +{L_Ibx ,O_C_Z ,S_C_AIPd,0 },{L_Ibx ,O_C_NZ ,S_C_AIPd,0 }, +{L_Ibx ,O_C_BE ,S_C_AIPd,0 },{L_Ibx ,O_C_NBE ,S_C_AIPd,0 }, /* 0x278 - 0x27f */ -{L_Ibx ,O_C_S ,S_C_ADDIP,0 },{L_Ibx ,O_C_NS ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_P ,S_C_ADDIP,0 },{L_Ibx ,O_C_NP ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_L ,S_C_ADDIP,0 },{L_Ibx ,O_C_NL ,S_C_ADDIP,0 }, -{L_Ibx ,O_C_LE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NLE ,S_C_ADDIP,0 }, +{L_Ibx ,O_C_S ,S_C_AIPd,0 },{L_Ibx ,O_C_NS ,S_C_AIPd,0 }, +{L_Ibx ,O_C_P ,S_C_AIPd,0 },{L_Ibx ,O_C_NP ,S_C_AIPd,0 }, +{L_Ibx ,O_C_L ,S_C_AIPd,0 },{L_Ibx ,O_C_NL ,S_C_AIPd,0 }, +{L_Ibx ,O_C_LE ,S_C_AIPd,0 },{L_Ibx ,O_C_NLE ,S_C_AIPd,0 }, /* 0x280 - 0x287 */ {L_MODRM ,0 ,0 ,M_GRP },{L_MODRM ,2 ,0 ,M_GRP }, @@ -467,7 +466,7 @@ static OpCode OpCodeTable[1024]={ {L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_SI},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_DI}, /* 0x298 - 0x29f */ {D_CBW ,0 ,0 ,0 },{D_CDQ ,0 ,0 ,0 }, -{L_Ifd ,O_CALL_F ,S_CSIP ,0 },{L_ERROR ,0 ,0 ,0 }, +{L_Ifd ,O_CALLFd ,0 ,0 },{L_ERROR ,0 ,0 ,0 }, {L_FLG ,0 ,S_PUSHd,0 },{L_POPd ,0 ,S_FLGd ,0 }, {L_REGb ,0 ,S_FLGb ,REGI_AH},{L_FLG ,0 ,S_REGb ,REGI_AH}, @@ -500,9 +499,9 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0 ,S_Eb ,M_Ib },{L_MODRM ,0 ,S_Ed ,M_Id }, /* 0x2c8 - 0x2cf */ {D_ENTERd ,0 ,0 ,0 },{D_LEAVEd ,0 ,0 ,0 }, -{L_POPfd ,0 ,S_CSIPIw,0 },{L_POPfd ,0 ,S_CSIP ,0 }, +{D_RETFdIw ,0 ,0 ,0 },{D_RETFd ,0 ,0 ,0 }, {L_VAL ,O_INT ,0 ,3 },{L_Ib ,O_INT ,0 ,0 }, -{L_INTO ,O_INT ,0 ,0 },{L_IRETd ,0 ,S_CSIP ,0 }, +{L_INTO ,O_INT ,0 ,0 },{D_IRETd ,0 ,0 ,0 }, /* 0x2d0 - 0x2d7 */ {L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,7 ,0 ,M_GRP_1 }, @@ -516,13 +515,13 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 }, /* 0x2e0 - 0x2e7 */ -{L_Ibx ,O_LOOPNZ ,S_ADDIP,0 },{L_Ibx ,O_LOOPZ ,S_ADDIP,0 }, -{L_Ibx ,O_LOOP ,S_ADDIP,0 },{L_Ibx ,O_JCXZ ,S_ADDIP,0 }, +{L_Ibx ,O_LOOPNZ ,S_AIPd ,0 },{L_Ibx ,O_LOOPZ ,S_AIPd ,0 }, +{L_Ibx ,O_LOOP ,S_AIPd ,0 },{L_Ibx ,O_JCXZ ,S_AIPd ,0 }, {L_Ib ,O_INb ,0 ,0 },{L_Ib ,O_INd ,0 ,0 }, {L_Ib ,O_OUTb ,0 ,0 },{L_Ib ,O_OUTd ,0 ,0 }, /* 0x2e8 - 0x2ef */ -{L_Id ,O_CALL_N ,S_ADDIP,0 },{L_Idx ,0 ,S_ADDIP,0 }, -{L_Ifd ,0 ,S_CSIP ,0 },{L_Ibx ,0 ,S_ADDIP,0 }, +{L_Id ,O_CALLNd ,S_AIPd ,0 },{L_Idx ,0 ,S_AIPd ,0 }, +{L_Ifd ,O_JMPFd ,0 ,0 },{L_Ibx ,0 ,S_AIPd ,0 }, {L_REGw ,O_INb ,0 ,REGI_DX},{L_REGw ,O_INd ,0 ,REGI_DX}, {L_REGw ,O_OUTb ,0 ,REGI_DX},{L_REGw ,O_OUTd ,0 ,REGI_DX}, @@ -538,179 +537,179 @@ static OpCode OpCodeTable[1024]={ {L_MODRM ,0xb ,0 ,M_GRP },{L_MODRM ,0xd ,0 ,M_GRP }, -/* 0x200 - 0x207 */ +/* 0x300 - 0x307 */ +{L_MODRM ,O_GRP6d ,S_Ew ,M_Ew },{L_MODRM ,O_GRP7d ,0 ,0 }, +{L_MODRM ,O_LAR ,S_Gw ,M_Ew },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x208 - 0x20f */ +/* 0x308 - 0x30f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x210 - 0x217 */ +/* 0x310 - 0x317 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x218 - 0x21f */ +/* 0x318 - 0x31f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x220 - 0x227 */ +/* 0x320 - 0x327 */ +{L_MODRM ,O_M_Rd_Cd ,S_Ed ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,O_M_Cd_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, + +/* 0x328 - 0x32f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x228 - 0x22f */ +/* 0x330 - 0x337 */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x338 - 0x33f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x230 - 0x237 */ +/* 0x340 - 0x347 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x238 - 0x23f */ +/* 0x348 - 0x34f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x240 - 0x247 */ +/* 0x350 - 0x357 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x248 - 0x24f */ +/* 0x358 - 0x35f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x250 - 0x257 */ +/* 0x360 - 0x367 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x258 - 0x25f */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, - -/* 0x260 - 0x267 */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x268 - 0x26f */ +/* 0x368 - 0x36f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x270 - 0x277 */ +/* 0x370 - 0x377 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x278 - 0x27f */ +/* 0x378 - 0x37f */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x280 - 0x287 */ -{L_Idx ,O_C_O ,S_C_ADDIP,0 },{L_Idx ,O_C_NO ,S_C_ADDIP,0 }, -{L_Idx ,O_C_B ,S_C_ADDIP,0 },{L_Idx ,O_C_NB ,S_C_ADDIP,0 }, -{L_Idx ,O_C_Z ,S_C_ADDIP,0 },{L_Idx ,O_C_NZ ,S_C_ADDIP,0 }, -{L_Idx ,O_C_BE ,S_C_ADDIP,0 },{L_Idx ,O_C_NBE ,S_C_ADDIP,0 }, -/* 0x288 - 0x28f */ -{L_Idx ,O_C_S ,S_C_ADDIP,0 },{L_Idx ,O_C_NS ,S_C_ADDIP,0 }, -{L_Idx ,O_C_P ,S_C_ADDIP,0 },{L_Idx ,O_C_NP ,S_C_ADDIP,0 }, -{L_Idx ,O_C_L ,S_C_ADDIP,0 },{L_Idx ,O_C_NL ,S_C_ADDIP,0 }, -{L_Idx ,O_C_LE ,S_C_ADDIP,0 },{L_Idx ,O_C_NLE ,S_C_ADDIP,0 }, +/* 0x380 - 0x387 */ +{L_Idx ,O_C_O ,S_C_AIPd,0 },{L_Idx ,O_C_NO ,S_C_AIPd,0 }, +{L_Idx ,O_C_B ,S_C_AIPd,0 },{L_Idx ,O_C_NB ,S_C_AIPd,0 }, +{L_Idx ,O_C_Z ,S_C_AIPd,0 },{L_Idx ,O_C_NZ ,S_C_AIPd,0 }, +{L_Idx ,O_C_BE ,S_C_AIPd,0 },{L_Idx ,O_C_NBE ,S_C_AIPd,0 }, +/* 0x388 - 0x38f */ +{L_Idx ,O_C_S ,S_C_AIPd,0 },{L_Idx ,O_C_NS ,S_C_AIPd,0 }, +{L_Idx ,O_C_P ,S_C_AIPd,0 },{L_Idx ,O_C_NP ,S_C_AIPd,0 }, +{L_Idx ,O_C_L ,S_C_AIPd,0 },{L_Idx ,O_C_NL ,S_C_AIPd,0 }, +{L_Idx ,O_C_LE ,S_C_AIPd,0 },{L_Idx ,O_C_NLE ,S_C_AIPd,0 }, -/* 0x290 - 0x297 */ +/* 0x390 - 0x397 */ {L_MODRM ,O_C_O ,S_C_Eb,0 },{L_MODRM ,O_C_NO ,S_C_Eb,0 }, {L_MODRM ,O_C_B ,S_C_Eb,0 },{L_MODRM ,O_C_NB ,S_C_Eb,0 }, {L_MODRM ,O_C_Z ,S_C_Eb,0 },{L_MODRM ,O_C_NZ ,S_C_Eb,0 }, {L_MODRM ,O_C_BE ,S_C_Eb,0 },{L_MODRM ,O_C_NBE ,S_C_Eb,0 }, -/* 0x298 - 0x29f */ +/* 0x398 - 0x39f */ {L_MODRM ,O_C_S ,S_C_Eb,0 },{L_MODRM ,O_C_NS ,S_C_Eb,0 }, {L_MODRM ,O_C_P ,S_C_Eb,0 },{L_MODRM ,O_C_NP ,S_C_Eb,0 }, {L_MODRM ,O_C_L ,S_C_Eb,0 },{L_MODRM ,O_C_NL ,S_C_Eb,0 }, {L_MODRM ,O_C_LE ,S_C_Eb,0 },{L_MODRM ,O_C_NLE ,S_C_Eb,0 }, -/* 0x2a0 - 0x2a7 */ +/* 0x3a0 - 0x3a7 */ {L_SEG ,0 ,S_PUSHd ,fs },{L_POPd ,0 ,S_SEGI ,fs }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_BTd ,0 ,0 }, {L_MODRM ,O_DSHLd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHLd ,S_Ed ,M_EdGdCL }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2a8 - 0x2af */ +/* 0x3a8 - 0x3af */ {L_SEG ,0 ,S_PUSHd ,gs },{L_POPd ,0 ,S_SEGI ,gs }, -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_BTSd ,0 ,0 }, {L_MODRM ,O_DSHRd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHRd ,S_Ed ,M_EdGdCL }, {0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdxGdx }, -/* 0x2b0 - 0x2b7 */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x3b0 - 0x3b7 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{L_MODRM ,O_BTRd ,0 ,0 }, {L_MODRM ,O_SEGFS ,S_SEGGd,M_Efd },{L_MODRM ,O_SEGGS ,S_SEGGd,M_Efd }, {L_MODRM ,0 ,S_Gd ,M_Eb },{L_MODRM ,0 ,S_Gd ,M_Ew }, -/* 0x2b8 - 0x2bf */ -{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +/* 0x3b8 - 0x3bf */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{L_MODRM ,0xf ,0 ,M_GRP },{L_MODRM ,O_BTCd ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {L_MODRM ,0 ,S_Gd ,M_Ebx },{L_MODRM ,0 ,S_Gd ,M_Ewx }, -/* 0x2c0 - 0x2cc */ +/* 0x3c0 - 0x3cc */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2c8 - 0x2cf */ +/* 0x3c8 - 0x3cf */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2d0 - 0x2d7 */ +/* 0x3d0 - 0x3d7 */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2d8 - 0x2df */ +/* 0x3d8 - 0x3df */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2e0 - 0x2ee */ +/* 0x3e0 - 0x3ee */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2e8 - 0x2ef */ +/* 0x3e8 - 0x3ef */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2f0 - 0x2fc */ +/* 0x3f0 - 0x3fc */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, -/* 0x2f8 - 0x2ff */ +/* 0x3f8 - 0x3ff */ {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, {0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, @@ -785,16 +784,26 @@ static OpCode Groups[16][8]={ {0 ,0 ,0 ,0 },{0 ,O_CBACK ,0 ,M_Iw }, },{ /* 0x0c Group 5 Ew */ {0 ,t_INCw ,S_Ew ,M_Ew },{0 ,t_DECw ,S_Ew ,M_Ew }, -{0 ,O_CALL_N ,S_IP ,M_Ew },{0 ,O_CALL_F ,S_CSIP ,M_Efw }, -{0 ,0 ,S_IP ,M_Ew },{0 ,0 ,S_CSIP ,M_Efw }, +{0 ,O_CALLNw ,S_IP ,M_Ew },{0 ,O_CALLFw ,0 ,M_Efw }, +{0 ,0 ,S_IP ,M_Ew },{0 ,O_JMPFw ,0 ,M_Efw }, {0 ,0 ,S_PUSHw,M_Ew },{0 ,0 ,0 ,0 }, },{ /* 0x0d Group 5 Ed */ {0 ,t_INCd ,S_Ed ,M_Ed },{0 ,t_DECd ,S_Ed ,M_Ed }, -{0 ,O_CALL_N ,S_IP ,M_Ed },{0 ,O_CALL_F ,S_CSIP ,M_Efd }, -{0 ,0 ,S_IP ,M_Ed },{0 ,0 ,S_CSIP ,M_Efd }, +{0 ,O_CALLNd ,S_IP ,M_Ed },{0 ,O_CALLFd ,0 ,M_Efd }, +{0 ,0 ,S_IP ,M_Ed },{0 ,O_JMPFd ,0 ,M_Efd }, {0 ,0 ,S_PUSHd,M_Ed },{0 ,0 ,0 ,0 }, +},{ /* 0x0e Group 8 Ew */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,O_BTw ,0 ,M_Ib },{0 ,O_BTSw ,0 ,M_Ib }, +{0 ,O_BTRw ,0 ,M_Ib },{0 ,O_BTCw ,0 ,M_Ib }, +},{ /* 0x0f Group 8 Ed */ +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 }, +{0 ,O_BTd ,0 ,M_Ib },{0 ,O_BTSd ,0 ,M_Ib }, +{0 ,O_BTRd ,0 ,M_Ib },{0 ,O_BTCd ,0 ,M_Ib }, diff --git a/src/cpu/core_full/save.h b/src/cpu/core_full/save.h index a7c4b2b8..fba9ed5f 100644 --- a/src/cpu/core_full/save.h +++ b/src/cpu/core_full/save.h @@ -52,14 +52,14 @@ switch (inst.code.save) { reg_32(inst.code.extra)=inst.op1.d; break; case S_SEGI: - SegSet16(inst.code.extra,inst.op1.w); + CPU_SetSegGeneral((SegNames)inst.code.extra,inst.op1.w); break; case S_SEGm: - SegSet16(inst.rm_index,inst.op1.w); + CPU_SetSegGeneral((SegNames)inst.rm_index,inst.op1.w); break; case S_SEGGw: reg_16(inst.rm_index)=inst.op1.w; - SegSet16(inst.code.extra,inst.op2.w); + CPU_SetSegGeneral((SegNames)inst.code.extra,inst.op2.w); break; case S_PUSHw: Push_16(inst.op1.w); @@ -68,19 +68,19 @@ switch (inst.code.save) { Push_32(inst.op1.d); break; - case S_C_ADDIP: + case S_C_AIPw: if (!inst.cond) goto nextopcode; - case S_ADDIP: + case S_AIPw: SaveIP(); reg_eip+=inst.op1.d; reg_eip&=0xffff; LoadIP(); break; - case S_CSIPIw: - reg_esp+=Fetchw(); - case S_CSIP: - reg_eip=inst.op1.d; - SegSet16(cs,inst.op2.w); + case S_C_AIPd: + if (!inst.cond) goto nextopcode; + case S_AIPd: + SaveIP(); + reg_eip+=inst.op1.d; LoadIP(); break; case S_IPIw: @@ -91,15 +91,13 @@ switch (inst.code.save) { LoadIP(); break; case S_FLGb: - flags.of =get_OF(); - flags.type=t_UNKNOWN; - flags.cf =(inst.op1.d & 0x001)>0;flags.pf =(inst.op1.d & 0x004)>0; - flags.af =(inst.op1.d & 0x010)>0;flags.zf =(inst.op1.d & 0x040)>0; - flags.sf =(inst.op1.d & 0x080)>0; + SETFLAGSb(inst.op1.d); break; case S_FLGw: - case S_FLGd: //TODO Check full 32bit flags one day - Save_Flagsw(inst.op1.w); + SETFLAGSw(inst.op1.d); + break; + case S_FLGd: + SETFLAGSd(inst.op1.d); break; case 0: break; diff --git a/src/cpu/core_full/string.h b/src/cpu/core_full/string.h index f70a39f4..b1079e85 100644 --- a/src/cpu/core_full/string.h +++ b/src/cpu/core_full/string.h @@ -10,8 +10,9 @@ else si_base=SegBase(ds); di_base=SegBase(es); if (inst.prefix & PREFIX_ADDR) { - add_mask=0; - si_index=reg_esi;di_index=reg_edi; + add_mask=0xFFFFFFFF; + si_index=reg_esi; + di_index=reg_edi; count=reg_ecx; } else { add_mask=0xFFFF; @@ -23,7 +24,7 @@ count=1; } - add_index=flags.df ? -1 : 1; + add_index=GETFLAG(DF) ? -1 : 1; if (count) switch (inst.code.op) { case R_OUTSB: for (;count>0;count--) { diff --git a/src/cpu/core_full/support.h b/src/cpu/core_full/support.h index 6df98558..166f90e7 100644 --- a/src/cpu/core_full/support.h +++ b/src/cpu/core_full/support.h @@ -25,8 +25,8 @@ enum { L_PREOP,L_PREADD,L_PREREP,L_PREREPNE, L_STRING, - L_IRETw,L_IRETd, /* Direct ones */ + D_IRETw,D_IRETd, D_PUSHAw,D_PUSHAd, D_POPAw,D_POPAd, D_DAA,D_DAS, @@ -39,6 +39,9 @@ enum { D_ENTERw,D_ENTERd, D_LEAVEw,D_LEAVEd, L_ERROR, + + D_RETFw,D_RETFd, + D_RETFwIw,D_RETFdIw, }; @@ -48,12 +51,15 @@ enum { O_XCHG_AX,O_XCHG_EAX, O_IMULRw,O_IMULRd, O_BOUNDw,O_BOUNDd, - O_CALL_N,O_CALL_F, + O_CALLNw,O_CALLNd, + O_CALLFw,O_CALLFd, + O_JMPFw,O_JMPFd, + O_OPAL,O_ALOP, O_OPAX,O_AXOP, O_OPEAX,O_EAXOP, O_INT, - O_SEGDS,O_SEGES,O_SEGFS,O_SEGGS, + O_SEGDS,O_SEGES,O_SEGFS,O_SEGGS,O_SEGSS, O_LOOP,O_LOOPZ,O_LOOPNZ,O_JCXZ, O_INb,O_INw,O_INd, O_OUTb,O_OUTw,O_OUTd, @@ -70,6 +76,18 @@ enum { O_DSHRw,O_DSHRd, O_C_O ,O_C_NO ,O_C_B ,O_C_NB ,O_C_Z ,O_C_NZ ,O_C_BE ,O_C_NBE, O_C_S ,O_C_NS ,O_C_P ,O_C_NP ,O_C_L ,O_C_NL ,O_C_LE ,O_C_NLE, + + O_GRP6w,O_GRP6d, + O_GRP7w,O_GRP7d, + O_M_Cd_Rd,O_M_Rd_Cd, + O_LAR, + + O_BTw,O_BTSw,O_BTRw,O_BTCw, + O_BTd,O_BTSd,O_BTRd,O_BTCd, + O_BSFw,O_BSRw, + + + }; enum { @@ -87,12 +105,11 @@ enum { S_SEGGw,S_SEGGd, - S_ADDIP,S_C_ADDIP, + S_AIPw,S_C_AIPw, + S_AIPd,S_C_AIPd, S_FLGb,S_FLGw,S_FLGd, S_IP,S_IPIw, - S_CSIP,S_CSIPIw, - }; enum { @@ -134,7 +151,7 @@ struct OpCode { static struct { Bitu entry; Bitu entry_default; - Bit8u rm; + Bitu rm; EAPoint rm_eaa; Bitu rm_off; Bitu rm_eai; @@ -150,7 +167,7 @@ static struct { struct { EAPoint base; } seg; - bool cond; + Bitu cond; bool repz; Bitu prefix; } inst;