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add TRx handling opcodes (fixes JetFighter2, thanks to vasyl)

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2700
This commit is contained in:
Sebastian Strohhäcker 2006-09-17 13:38:30 +00:00
parent acce481653
commit bd65320c7e
6 changed files with 78 additions and 6 deletions
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4
include/cpu.h
View file

@ -81,6 +81,9 @@ bool CPU_READ_CRX(Bitu cr,Bit32u & retvalue);
bool CPU_WRITE_DRX(Bitu dr,Bitu value);
bool CPU_READ_DRX(Bitu dr,Bit32u & retvalue);
bool CPU_WRITE_TRX(Bitu dr,Bitu value);
bool CPU_READ_TRX(Bitu dr,Bit32u & retvalue);
void CPU_SMSW(Bitu & word);
Bitu CPU_LMSW(Bitu word);
@ -442,6 +445,7 @@ struct CPUBlock {
} exception;
Bits direction;
Bit32u drx[8];
Bit32u trx[8];
};
extern CPUBlock cpu;

6
src/cpu/core_full/op.h
View file

@ -472,6 +472,12 @@ switch (inst.code.op) {
case O_M_Rd_DRx:
if (CPU_READ_DRX(inst.rm_index,inst_op1_d)) RunException();
break;
case O_M_TRx_Rd:
if (CPU_WRITE_TRX(inst.rm_index,inst_op1_d)) RunException();
break;
case O_M_Rd_TRx:
if (CPU_READ_TRX(inst.rm_index,inst_op1_d)) RunException();
break;
case O_LAR:
{
if ((reg_flags & FLAG_VM) || (!cpu.pmode)) goto illegalopcode;

8
src/cpu/core_full/optable.h
View file

@ -206,8 +206,8 @@ static OpCode OpCodeTable[1024]={
/* 0x120 - 0x127 */
{L_MODRM ,O_M_Rd_CRx ,S_Ed ,0 },{L_MODRM ,O_M_Rd_DRx ,S_Ed ,0 },
{L_MODRM ,O_M_CRx_Rd ,0 ,M_Ed },{L_MODRM ,O_M_DRx_Rd ,0 ,M_Ed },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{L_MODRM ,O_M_Rd_TRx ,S_Ed ,0 },{0 ,0 ,0 ,0 },
{L_MODRM ,O_M_TRx_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 },
/* 0x128 - 0x12f */
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
@ -562,8 +562,8 @@ static OpCode OpCodeTable[1024]={
/* 0x320 - 0x327 */
{L_MODRM ,O_M_Rd_CRx ,S_Ed ,0 },{L_MODRM ,O_M_Rd_DRx ,S_Ed ,0 },
{L_MODRM ,O_M_CRx_Rd ,0 ,M_Ed },{L_MODRM ,O_M_DRx_Rd ,0 ,M_Ed },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{L_MODRM ,O_M_Rd_TRx ,S_Ed ,0 },{0 ,0 ,0 ,0 },
{L_MODRM ,O_M_TRx_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 },
/* 0x328 - 0x32f */
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },

1
src/cpu/core_full/support.h
View file

@ -86,6 +86,7 @@ enum {
O_GRP7w,O_GRP7d,
O_M_CRx_Rd,O_M_Rd_CRx,
O_M_DRx_Rd,O_M_Rd_DRx,
O_M_TRx_Rd,O_M_Rd_TRx,
O_LAR,O_LSL,
O_ARPL,

26
src/cpu/core_normal/prefix_0f.h
View file

@ -201,6 +201,32 @@
if (CPU_WRITE_DRX(which,*eard)) RUNEXCEPTION();
}
break;
CASE_0F_B(0x24) /* MOV Rd,TRx */
{
GetRM;
Bitu which=(rm >> 3) & 7;
if (rm < 0xc0 ) {
rm |= 0xc0;
LOG(LOG_CPU,LOG_ERROR)("MOV XXX,TR% with non-register",which);
}
GetEArd;
Bit32u trx_value;
if (CPU_READ_TRX(which,trx_value)) RUNEXCEPTION();
*eard=trx_value;
}
break;
CASE_0F_B(0x26) /* MOV TRx,Rd */
{
GetRM;
Bitu which=(rm >> 3) & 7;
if (rm < 0xc0 ) {
rm |= 0xc0;
LOG(LOG_CPU,LOG_ERROR)("MOV TR%,XXX with non-register",which);
}
GetEArd;
if (CPU_WRITE_TRX(which,*eard)) RUNEXCEPTION();
}
break;
CASE_0F_W(0x80) /* JO */
JumpCond16_w(TFLG_O);break;
CASE_0F_W(0x81) /* JNO */

39
src/cpu/cpu.cpp
View file

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* $Id: cpu.cpp,v 1.84 2006-09-14 18:46:48 qbix79 Exp $ */
/* $Id: cpu.cpp,v 1.85 2006-09-17 13:38:30 c2woody Exp $ */
#include <assert.h>
#include "dosbox.h"
@ -1561,6 +1561,38 @@ bool CPU_READ_DRX(Bitu dr,Bit32u & retvalue) {
return false;
}
bool CPU_WRITE_TRX(Bitu tr,Bitu value) {
/* Check if privileged to access control registers */
if (cpu.pmode && (cpu.cpl>0)) return CPU_PrepareException(EXCEPTION_GP,0);
switch (tr) {
// case 3:
case 6:
case 7:
cpu.trx[tr]=value;
return false;
default:
LOG(LOG_CPU,LOG_ERROR)("Unhandled MOV TR%d,%X",tr,value);
break;
}
return CPU_PrepareException(EXCEPTION_UD,0);
}
bool CPU_READ_TRX(Bitu tr,Bit32u & retvalue) {
/* Check if privileged to access control registers */
if (cpu.pmode && (cpu.cpl>0)) return CPU_PrepareException(EXCEPTION_GP,0);
switch (tr) {
// case 3:
case 6:
case 7:
retvalue=cpu.trx[tr];
return false;
default:
LOG(LOG_CPU,LOG_ERROR)("Unhandled MOV XXX, TR%d",tr);
break;
}
return CPU_PrepareException(EXCEPTION_UD,0);
}
void CPU_SMSW(Bitu & word) {
word=cpu.cr0;
@ -1976,7 +2008,10 @@ public:
cpu.idt.SetBase(0);
cpu.idt.SetLimit(1023);
for (Bitu i=0; i<7; i++) cpu.drx[i]=0;
for (Bitu i=0; i<7; i++) {
cpu.drx[i]=0;
cpu.trx[i]=0;
}
cpu.drx[6]=0xffff1ff0;
cpu.drx[7]=0x00000400;