From e01a04aee94e9a06bbe0d27f60c424392348c4eb Mon Sep 17 00:00:00 2001
From: ripsaw8080 <ripsaw8080@users.sourceforge.net>
Date: Thu, 3 May 2018 17:11:36 +0000
Subject: [PATCH] Flag handling (mostly undocumented behavior) for normal core:
 overflow flag for divide instructions, zero and sign flags for integer
 multiply instructions. Fixes A320 Airbus and Perfect General.

Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@4098
---
 src/cpu/instructions.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/cpu/instructions.h b/src/cpu/instructions.h
index ed6e46bc..f4abed86 100644
--- a/src/cpu/instructions.h
+++ b/src/cpu/instructions.h
@@ -679,6 +679,7 @@
 	if (quo>0xff) EXCEPTION(0);								\
 	reg_ah=rem;												\
 	reg_al=quo8;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 
@@ -693,6 +694,7 @@
 	if (quo!=(Bit32u)quo16) EXCEPTION(0);					\
 	reg_dx=rem;												\
 	reg_ax=quo16;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 #define DIVD(op1,load,save)									\
@@ -706,6 +708,7 @@
 	if (quo!=(Bit64u)quo32) EXCEPTION(0);					\
 	reg_edx=rem;											\
 	reg_eax=quo32;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 
@@ -719,6 +722,7 @@
 	if (quo!=(Bit16s)quo8s) EXCEPTION(0);					\
 	reg_ah=rem;												\
 	reg_al=quo8s;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 
@@ -733,6 +737,7 @@
 	if (quo!=(Bit32s)quo16s) EXCEPTION(0);					\
 	reg_dx=rem;												\
 	reg_ax=quo16s;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 #define IDIVD(op1,load,save)								\
@@ -746,12 +751,15 @@
 	if (quo!=(Bit64s)quo32s) EXCEPTION(0);					\
 	reg_edx=rem;											\
 	reg_eax=quo32s;											\
+	SETFLAGBIT(OF,false);									\
 }
 
 #define IMULB(op1,load,save)								\
 {															\
 	reg_ax=((Bit8s)reg_al) * ((Bit8s)(load(op1)));			\
 	FillFlagsNoCFOF();										\
+	SETFLAGBIT(ZF,reg_al == 0);								\
+	SETFLAGBIT(SF,reg_al & 0x80);							\
 	if ((reg_ax & 0xff80)==0xff80 ||						\
 		(reg_ax & 0xff80)==0x0000) {						\
 		SETFLAGBIT(CF,false);SETFLAGBIT(OF,false);			\
@@ -767,6 +775,8 @@
 	reg_ax=(Bit16s)(temps);									\
 	reg_dx=(Bit16s)(temps >> 16);							\
 	FillFlagsNoCFOF();										\
+	SETFLAGBIT(ZF,reg_ax == 0);								\
+	SETFLAGBIT(SF,reg_ax & 0x8000);							\
 	if (((temps & 0xffff8000)==0xffff8000 ||				\
 		(temps & 0xffff8000)==0x0000)) {					\
 		SETFLAGBIT(CF,false);SETFLAGBIT(OF,false);			\
@@ -782,6 +792,8 @@
 	reg_eax=(Bit32u)(temps);								\
 	reg_edx=(Bit32u)(temps >> 32);							\
 	FillFlagsNoCFOF();										\
+	SETFLAGBIT(ZF,reg_eax == 0);							\
+	SETFLAGBIT(SF,reg_eax & 0x80000000);					\
 	if ((reg_edx==0xffffffff) &&							\
 		(reg_eax & 0x80000000) ) {							\
 		SETFLAGBIT(CF,false);SETFLAGBIT(OF,false);			\