additional svga chipset emulation (tseng, paradise) and small fixes for s3, vasyl
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3075
This commit is contained in:
Sebastian Strohhäcker
parent
2c95419294
commit
e0d88e1d11
17 changed files with 1512 additions and 226 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2002-2007 The DOSBox Team
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* Copyright (C) 2002-2008 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,6 +16,8 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: int10.cpp,v 1.48 2008-01-09 20:34:51 c2woody Exp $ */
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#include "dosbox.h"
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#include "mem.h"
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#include "callback.h"
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@ -480,7 +482,7 @@ graphics_chars:
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}
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break;
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case 0x4f: /* VESA Calls */
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if ((!IS_VGA_ARCH) || (svgaCard==SVGA_None)) break;
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if ((!IS_VGA_ARCH) || (svgaCard!=SVGA_S3Trio)) break;
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switch (reg_al) {
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case 0x00: /* Get SVGA Information */
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reg_al=0x4f;
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2002-2007 The DOSBox Team
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* Copyright (C) 2002-2008 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: int10_modes.cpp,v 1.73 2007-12-27 10:57:51 c2woody Exp $ */
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/* $Id: int10_modes.cpp,v 1.74 2008-01-09 20:34:51 c2woody Exp $ */
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#include <string.h>
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@ -124,6 +124,79 @@ VideoModeBlock ModeList_VGA[]={
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{0xFFFF ,M_ERROR ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0x00000 ,0x0000 ,0 ,0 ,0 ,0 ,0 },
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};
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VideoModeBlock ModeList_VGA_Tseng[]={
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/* mode ,type ,sw ,sh ,tw ,th ,cw,ch ,pt,pstart ,plength,htot,vtot,hde,vde special flags */
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{ 0x000 ,M_TEXT ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK },
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{ 0x001 ,M_TEXT ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK },
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{ 0x002 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x003 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x004 ,M_CGA4 ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x005 ,M_CGA4 ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x006 ,M_CGA2 ,640 ,200 ,80 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x007 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x00D ,M_EGA ,320 ,200 ,40 ,25 ,8 ,8 ,8 ,0xA0000 ,0x2000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE },
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{ 0x00E ,M_EGA ,640 ,200 ,80 ,25 ,8 ,8 ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_EGA_LINE_DOUBLE },
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{ 0x00F ,M_EGA ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0 },/*was EGA_2*/
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{ 0x010 ,M_EGA ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0 },
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{ 0x011 ,M_EGA ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0 },/*was EGA_2 */
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{ 0x012 ,M_EGA ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0 },
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{ 0x013 ,M_VGA ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x018 ,M_TEXT ,1056 ,688, 132,44, 8, 8, 1 ,0xB0000 ,0x4000, 192, 800, 132, 704, 0 },
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{ 0x019 ,M_TEXT ,1056 ,400, 132,25, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 400, 0 },
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{ 0x01A ,M_TEXT ,1056 ,400, 132,28, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 448, 0 },
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{ 0x022 ,M_TEXT ,1056 ,688, 132,44, 8, 8, 1 ,0xB8000 ,0x4000, 192, 800, 132, 704, 0 },
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{ 0x023 ,M_TEXT ,1056 ,400, 132,25, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 400, 0 },
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{ 0x024 ,M_TEXT ,1056 ,400, 132,28, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 448, 0 },
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{ 0x025 ,M_LIN4 ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 , 0 },
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{ 0x029 ,M_LIN4 ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },
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{ 0x02D ,M_LIN8 ,640 ,350 ,80 ,21 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 , 0 },
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{ 0x02E ,M_LIN8 ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , 0 },
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{ 0x02F ,M_LIN8 ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , 0 },/* ET4000 only */
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{ 0x030 ,M_LIN8 ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 , 0 },
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{ 0x036 ,M_LIN4 ,960 , 720,120,45 ,8 ,16 ,1 ,0xA0000 ,0xA000, 120 ,800 ,120,720 , 0 },/* STB only */
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{ 0x037 ,M_LIN4 ,1024, 768,128,48 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,800 ,128,768 , 0 },
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{ 0x038 ,M_LIN8 ,1024 ,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,800 ,128,768 , 0 },/* ET4000 only */
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{ 0x03D ,M_LIN4 ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1152,160,1024, 0 },/* newer ET4000 */
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{ 0x03E ,M_LIN4 ,1280, 960,160,60 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1024,160,960 , 0 },/* Definicon only */
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{ 0x06A ,M_LIN4 ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },/* newer ET4000 */
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{0xFFFF ,M_ERROR ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0x00000 ,0x0000 ,0 ,0 ,0 ,0 ,0 },
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};
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VideoModeBlock ModeList_VGA_Paradise[]={
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/* mode ,type ,sw ,sh ,tw ,th ,cw,ch ,pt,pstart ,plength,htot,vtot,hde,vde special flags */
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{ 0x000 ,M_TEXT ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK },
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{ 0x001 ,M_TEXT ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK },
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{ 0x002 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x003 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x004 ,M_CGA4 ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x005 ,M_CGA4 ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x006 ,M_CGA2 ,640 ,200 ,80 ,25 ,8 ,8 ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE},
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{ 0x007 ,M_TEXT ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x00D ,M_EGA ,320 ,200 ,40 ,25 ,8 ,8 ,8 ,0xA0000 ,0x2000 ,50 ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _EGA_LINE_DOUBLE },
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{ 0x00E ,M_EGA ,640 ,200 ,80 ,25 ,8 ,8 ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_EGA_LINE_DOUBLE },
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{ 0x00F ,M_EGA ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0 },/*was EGA_2*/
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{ 0x010 ,M_EGA ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0 },
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{ 0x011 ,M_EGA ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0 },/*was EGA_2 */
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{ 0x012 ,M_EGA ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0 },
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{ 0x013 ,M_VGA ,320 ,200 ,40 ,25 ,8 ,8 ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,0 },
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{ 0x054 ,M_TEXT ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
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{ 0x055 ,M_TEXT ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
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{ 0x056 ,M_TEXT ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
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{ 0x057 ,M_TEXT ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
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{ 0x058 ,M_LIN4 ,800 , 600, 100,37, 8, 16,1, 0xA0000, 0xA000, 128 ,663 ,100,600, 0 },
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{ 0x05D ,M_LIN4 ,1024, 768, 128,48 ,8, 16,1, 0xA0000, 0x10000,128 ,800 ,128,768 ,0 }, // documented only on C00 upwards
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{ 0x05E ,M_LIN8 ,640 , 400, 80 ,25, 8, 16,1, 0xA0000, 0x10000,100 ,449 ,80 ,400, 0 },
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{ 0x05F ,M_LIN8 ,640 , 480, 80 ,30, 8, 16,1, 0xA0000, 0x10000,100 ,525 ,80 ,480, 0 },
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{0xFFFF ,M_ERROR ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0x00000 ,0x0000 ,0 ,0 ,0 ,0 ,0 },
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};
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VideoModeBlock ModeList_EGA[]={
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/* mode ,type ,sw ,sh ,tw ,th ,cw,ch ,pt,pstart ,plength,htot,vtot,hde,vde special flags */
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{ 0x000 ,M_TEXT ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50 ,366 ,40 ,350 ,_EGA_HALF_CLOCK },
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@ -510,9 +583,29 @@ bool INT10_SetVideoMode(Bitu mode) {
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Bit8u modeset_ctl,video_ctl,vga_switches;
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if (IS_VGA_ARCH) {
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if (!SetCurMode(ModeList_VGA,mode)){
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LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
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return false;
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if (svga.accepts_mode) {
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if (!svga.accepts_mode(mode)) return false;
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}
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switch(svgaCard) {
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case SVGA_TsengET4K:
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case SVGA_TsengET3K:
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if (!SetCurMode(ModeList_VGA_Tseng,mode)){
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LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
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return false;
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}
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break;
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case SVGA_ParadisePVGA1A:
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if (!SetCurMode(ModeList_VGA_Paradise,mode)){
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LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
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return false;
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}
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break;
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default:
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if (!SetCurMode(ModeList_VGA,mode)){
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LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
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return false;
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}
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}
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} else {
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if (!SetCurMode(ModeList_EGA,mode)){
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@ -534,7 +627,7 @@ bool INT10_SetVideoMode(Bitu mode) {
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else crtc_base=0x3d4;
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// Disable MMIO here so we can read / write memory
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if (IS_VGA_ARCH) IO_Write(crtc_base,0x53);IO_Write(crtc_base+1,0x0);
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if (IS_VGA_ARCH && svgaCard == SVGA_S3Trio) IO_Write(crtc_base,0x53);IO_Write(crtc_base+1,0x0);
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/* Setup MISC Output Register */
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Bit8u misc_output=0x2 | (mono_mode ? 0x0 : 0x1);
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@ -744,10 +837,14 @@ bool INT10_SetVideoMode(Bitu mode) {
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/* OverFlow */
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IO_Write(crtc_base,0x07);IO_Write(crtc_base+1,overflow);
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/* Extended Horizontal Overflow */
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IO_Write(crtc_base,0x5d);IO_Write(crtc_base+1,hor_overflow);
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/* Extended Vertical Overflow */
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IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1,ver_overflow);
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if (svgaCard == SVGA_S3Trio) {
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/* Extended Horizontal Overflow */
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IO_Write(crtc_base,0x5d);IO_Write(crtc_base+1,hor_overflow);
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/* Extended Vertical Overflow */
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IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1,ver_overflow);
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}
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/* Offset Register */
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Bitu offset;
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switch (CurMode->type) {
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@ -766,15 +863,18 @@ bool INT10_SetVideoMode(Bitu mode) {
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}
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IO_Write(crtc_base,0x13);
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IO_Write(crtc_base + 1,offset & 0xff);
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/* Extended System Control 2 Register */
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/* This register actually has more bits but only use the extended offset ones */
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IO_Write(crtc_base,0x51);
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IO_Write(crtc_base + 1,(offset & 0x300) >> 4);
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/* Clear remaining bits of the display start */
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IO_Write(crtc_base,0x69);
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IO_Write(crtc_base + 1,0);
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/* Extended Vertical Overflow */
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IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1,ver_overflow);
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if (svgaCard == SVGA_S3Trio) {
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/* Extended System Control 2 Register */
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/* This register actually has more bits but only use the extended offset ones */
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IO_Write(crtc_base,0x51);
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IO_Write(crtc_base + 1,(offset & 0x300) >> 4);
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/* Clear remaining bits of the display start */
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IO_Write(crtc_base,0x69);
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IO_Write(crtc_base + 1,0);
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/* Extended Vertical Overflow */
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IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1,ver_overflow);
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}
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/* Mode Control */
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Bit8u mode_control=0;
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@ -815,32 +915,36 @@ bool INT10_SetVideoMode(Bitu mode) {
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/* Renable write protection */
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IO_Write(crtc_base,0x11);
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IO_Write(crtc_base+1,IO_Read(crtc_base+1)|0x80);
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/* Setup the correct clock */
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if (CurMode->mode>=0x100) {
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misc_output|=0xef; //Select clock 3
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Bitu clock=CurMode->vtotal*8*CurMode->htotal*70;
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VGA_SetClock(3,clock/1000);
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if (svgaCard == SVGA_S3Trio) {
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/* Setup the correct clock */
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if (CurMode->mode>=0x100) {
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misc_output|=0xef; //Select clock 3
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Bitu clock=CurMode->vtotal*8*CurMode->htotal*70;
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VGA_SetClock(3,clock/1000);
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}
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Bit8u misc_control_2;
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/* Setup Pixel format */
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switch (CurMode->type) {
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case M_LIN8:
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misc_control_2=0x00;
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break;
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case M_LIN15:
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misc_control_2=0x30;
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break;
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case M_LIN16:
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misc_control_2=0x50;
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break;
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case M_LIN32:
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misc_control_2=0xd0;
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break;
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default:
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misc_control_2=0x0;
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break;
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}
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IO_WriteB(crtc_base,0x67);IO_WriteB(crtc_base+1,misc_control_2);
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}
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Bit8u misc_control_2;
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/* Setup Pixel format */
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switch (CurMode->type) {
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case M_LIN8:
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misc_control_2=0x00;
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break;
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case M_LIN15:
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misc_control_2=0x30;
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break;
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case M_LIN16:
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misc_control_2=0x50;
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break;
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case M_LIN32:
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misc_control_2=0xd0;
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break;
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default:
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misc_control_2=0x0;
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break;
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}
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IO_WriteB(crtc_base,0x67);IO_WriteB(crtc_base+1,misc_control_2);
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/* Write Misc Output */
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IO_Write(0x3c2,misc_output);
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/* Program Graphics controller */
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@ -1073,78 +1177,90 @@ dac_text16:
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}
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// disabled, has to be set in bios.cpp exclusively
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// real_writeb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE,feature);
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/* Setup the CPU Window */
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IO_Write(crtc_base,0x6a);
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IO_Write(crtc_base+1,0);
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/* Setup the linear frame buffer */
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IO_Write(crtc_base,0x59);
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IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
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IO_Write(crtc_base,0x5a);
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IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 16));
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IO_Write(crtc_base,0x6b); // BIOS scratchpad
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IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
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/* Setup some remaining S3 registers */
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IO_Write(crtc_base,0x41); // BIOS scratchpad
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IO_Write(crtc_base+1,0x88);
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IO_Write(crtc_base,0x52); // extended BIOS scratchpad
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IO_Write(crtc_base+1,0x80);
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IO_Write(0x3c4,0x15);
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IO_Write(0x3c5,0x03);
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if (svgaCard == SVGA_S3Trio) {
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/* Setup the CPU Window */
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IO_Write(crtc_base,0x6a);
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IO_Write(crtc_base+1,0);
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/* Setup the linear frame buffer */
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IO_Write(crtc_base,0x59);
|
||||
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
|
||||
IO_Write(crtc_base,0x5a);
|
||||
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 16));
|
||||
IO_Write(crtc_base,0x6b); // BIOS scratchpad
|
||||
IO_Write(crtc_base+1,(Bit8u)(S3_LFB_BASE >> 24));
|
||||
|
||||
/* Setup some remaining S3 registers */
|
||||
IO_Write(crtc_base,0x41); // BIOS scratchpad
|
||||
IO_Write(crtc_base+1,0x88);
|
||||
IO_Write(crtc_base,0x52); // extended BIOS scratchpad
|
||||
IO_Write(crtc_base+1,0x80);
|
||||
|
||||
// Accellerator setup
|
||||
Bitu reg_50=0;
|
||||
switch (CurMode->type) {
|
||||
case M_LIN15:
|
||||
case M_LIN16: reg_50|=0x10; break;
|
||||
case M_LIN32: reg_50|=0x30; break;
|
||||
}
|
||||
switch(CurMode->swidth)
|
||||
{
|
||||
case 640: reg_50|=0x40; break;
|
||||
case 800: reg_50|=0x80; break;
|
||||
case 1024: break;
|
||||
case 1152: reg_50|=0x01; break;
|
||||
case 1280: reg_50|=0xc1; break;
|
||||
}
|
||||
IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1,reg_50);
|
||||
IO_Write(0x3c4,0x15);
|
||||
IO_Write(0x3c5,0x03);
|
||||
|
||||
Bitu reg_31, reg_3a;
|
||||
switch (CurMode->type) {
|
||||
// Accellerator setup
|
||||
Bitu reg_50=0;
|
||||
switch (CurMode->type) {
|
||||
case M_LIN15:
|
||||
case M_LIN16: reg_50|=0x10; break;
|
||||
case M_LIN32: reg_50|=0x30; break;
|
||||
}
|
||||
switch(CurMode->swidth) {
|
||||
case 640: reg_50|=0x40; break;
|
||||
case 800: reg_50|=0x80; break;
|
||||
case 1024: break;
|
||||
case 1152: reg_50|=0x01; break;
|
||||
case 1280: reg_50|=0xc1; break;
|
||||
}
|
||||
IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1,reg_50);
|
||||
|
||||
Bitu reg_31, reg_3a;
|
||||
switch (CurMode->type) {
|
||||
case M_LIN15:
|
||||
case M_LIN16:
|
||||
case M_LIN32:
|
||||
reg_3a=0x15;
|
||||
break;
|
||||
case M_LIN8:
|
||||
// S3VBE20 does it this way. The other double pixel bit does not
|
||||
// seem to have an effect on the Trio64.
|
||||
if(CurMode->special&_VGA_PIXEL_DOUBLE) reg_3a=0x5;
|
||||
else reg_3a=0x15;
|
||||
break;
|
||||
default:
|
||||
reg_3a=5;
|
||||
break;
|
||||
};
|
||||
|
||||
switch (CurMode->type) {
|
||||
case M_LIN4: // <- Theres a discrepance with real hardware on this
|
||||
case M_LIN8:
|
||||
case M_LIN15:
|
||||
case M_LIN16:
|
||||
case M_LIN32:
|
||||
reg_3a=0x15;
|
||||
break;
|
||||
case M_LIN8:
|
||||
// S3VBE20 does it this way. The other double pixel bit does not
|
||||
// seem to have an effect on the Trio64.
|
||||
if(CurMode->special&_VGA_PIXEL_DOUBLE) reg_3a=0x5;
|
||||
else reg_3a=0x15;
|
||||
reg_31 = 9;
|
||||
break;
|
||||
default:
|
||||
reg_3a=5;
|
||||
};
|
||||
|
||||
switch (CurMode->type) {
|
||||
case M_LIN4: // <- Theres a discrepance with real hardware on this
|
||||
case M_LIN8:
|
||||
case M_LIN15:
|
||||
case M_LIN16:
|
||||
case M_LIN32:
|
||||
reg_31 = 9;
|
||||
break;
|
||||
default:
|
||||
reg_31 = 5;
|
||||
break;
|
||||
}
|
||||
IO_Write(crtc_base,0x3a);IO_Write(crtc_base+1,reg_3a);
|
||||
IO_Write(crtc_base,0x31);IO_Write(crtc_base+1,reg_31); //Enable banked memory and 256k+ access
|
||||
IO_Write(crtc_base,0x58);IO_Write(crtc_base+1,0x3); //Enable 8 mb of linear addressing
|
||||
reg_31 = 5;
|
||||
break;
|
||||
}
|
||||
IO_Write(crtc_base,0x3a);IO_Write(crtc_base+1,reg_3a);
|
||||
IO_Write(crtc_base,0x31);IO_Write(crtc_base+1,reg_31); //Enable banked memory and 256k+ access
|
||||
IO_Write(crtc_base,0x58);IO_Write(crtc_base+1,0x3); //Enable 8 mb of linear addressing
|
||||
|
||||
IO_Write(crtc_base,0x38);IO_Write(crtc_base+1,0x48); //Register lock 1
|
||||
IO_Write(crtc_base,0x39);IO_Write(crtc_base+1,0xa5); //Register lock 2
|
||||
IO_Write(crtc_base,0x38);IO_Write(crtc_base+1,0x48); //Register lock 1
|
||||
IO_Write(crtc_base,0x39);IO_Write(crtc_base+1,0xa5); //Register lock 2
|
||||
} else if (svga.set_video_mode) {
|
||||
VGA_ModeExtraData modeData;
|
||||
modeData.ver_overflow = ver_overflow;
|
||||
modeData.hor_overflow = hor_overflow;
|
||||
modeData.offset = offset;
|
||||
modeData.modeNo = CurMode->mode;
|
||||
modeData.htotal = CurMode->htotal;
|
||||
modeData.vtotal = CurMode->vtotal;
|
||||
svga.set_video_mode(crtc_base, &modeData);
|
||||
}
|
||||
|
||||
FinishSetMode(clearmem);
|
||||
/* Load text mode font */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue