Changed the TOP system.
Added support for 80 bits loading and saving Added support BCD saving Added FPREM Adden FXAM Fixed bug when comparing zero to an nonzero number. Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1138
This commit is contained in:
Peter Veenstra
parent
4e62907e37
commit
e2f947a1c1
3 changed files with 246 additions and 152 deletions
211
src/fpu/fpu.cpp
211
src/fpu/fpu.cpp
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@ -27,6 +27,9 @@
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typedef PhysPt EAPoint;
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#define TOP fpu.top
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#define ST(i) ( (fpu.top+ (i) ) & 7 )
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#define LoadMb(off) mem_readb(off)
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#define LoadMw(off) mem_readw(off)
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#define LoadMd(off) mem_readd(off)
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@ -99,37 +102,39 @@ INLINE Bitu FPU_GET_C3(void){
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#include "fpu_instructions.h"
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/* TODO : ESC6normal => esc4normal+pop or a define as well
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: Make a smarter top system. won't matter that much in speed though.
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: #define ST fpu.top #define ST(i) (fpu.top+(i))&7 maybe*/
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*/
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/* WATCHIT : ALWAYS UPDATE REGISTERS BEFORE AND AFTER USING THEM
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STATUS WORD => FPU_SET_TOP(TOP) BEFORE a read
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TOP=FPU_GET_TOP() after a write;
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*/
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static void EATREE(Bitu _rm){
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Bitu group=(_rm >> 3) & 7;
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Bitu top = FPU_GET_TOP();
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/* data will allready be put in register 8 by caller */
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switch(group){
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case 0x00: /* FIADD */
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FPU_FADD(top, 8);
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FPU_FADD(TOP, 8);
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break;
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case 0x01: /* FIMUL */
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FPU_FMUL(top, 8);
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FPU_FMUL(TOP, 8);
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break;
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case 0x02: /* FICOM */
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FPU_FCOM(top,8);
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FPU_FCOM(TOP,8);
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break;
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case 0x03: /* FICOMP */
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FPU_FCOM(top,8);
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FPU_FCOM(TOP,8);
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FPU_FPOP();
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break;
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case 0x04: /* FISUB */
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FPU_FSUB(top,8);
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FPU_FSUB(TOP,8);
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break;
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case 0x05: /* FISUBR */
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FPU_FSUBR(top,8);
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FPU_FSUBR(TOP,8);
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case 0x06: /* FIDIV */
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FPU_FDIV(top, 8);
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FPU_FDIV(TOP, 8);
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break;
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case 0x07: /* FIDIVR */
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FPU_FDIVR(top,8);
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FPU_FDIVR(TOP,8);
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break;
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default:
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break;
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@ -138,10 +143,7 @@ static void EATREE(Bitu _rm){
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}
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void FPU_ESC0_EA(Bitu rm,PhysPt addr) {
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/* REGULAR TREE WITH 32 BITS REALS ? float ? */
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//THIS SHOULD GO ALLRIGHT !?!
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// LOG(LOG_FPU, LOG_WARN)("ESC 0 EA used (check the result!)");
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/* REGULAR TREE WITH 32 BITS REALS -> float */
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union {
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float f;
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Bit32u l;
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@ -154,32 +156,31 @@ void FPU_ESC0_EA(Bitu rm,PhysPt addr) {
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void FPU_ESC0_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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Bitu top = FPU_GET_TOP();
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switch (group){
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case 0x00: /* FADD ST,STi */
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FPU_FADD(top,(top+sub)&7);
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FPU_FADD(TOP,ST(sub));
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break;
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case 0x01: /* FMUL ST,STi */
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FPU_FMUL(top,(top+sub)&7);
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FPU_FMUL(TOP,ST(sub));
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break;
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case 0x02: /* FCOM STi */
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FPU_FCOM(top,(top+sub)&7);
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FPU_FCOM(TOP,ST(sub));
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break;
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case 0x03: /* FCOMP STi */
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FPU_FCOM(top,(top+sub)&7);
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FPU_FCOM(TOP,ST(sub));
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FPU_FPOP();
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break;
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case 0x04: /* FSUB ST,STi */
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FPU_FSUB(top,(top+sub)&7);
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FPU_FSUB(TOP,ST(sub));
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break;
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case 0x05: /* FSUBR ST,STi */
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FPU_FSUBR(top,(top+sub)&7);
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FPU_FSUBR(TOP,ST(sub));
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break;
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case 0x06: /* FDIV ST,STi */
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FPU_FDIV(top,(top+sub)&7);
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FPU_FDIV(TOP,ST(sub));
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break;
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case 0x07: /* FDIVR ST,STi */
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FPU_FDIVR(top,(top+sub)&7);
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FPU_FDIVR(TOP,ST(sub));
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break;
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default:
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break;
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@ -192,7 +193,7 @@ void FPU_ESC1_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x00: /* FLD */
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case 0x00: /* FLD float*/
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{
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union {
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float f;
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@ -206,25 +207,25 @@ void FPU_ESC1_EA(Bitu rm,PhysPt addr) {
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case 0x01: /* UNKNOWN */
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LOG(LOG_FPU,LOG_WARN)("ESC EA 1:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x02: /* FST */
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case 0x02: /* FST float*/
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{
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union {
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float f;
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Bit32u l;
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} blah;
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//should depend on rounding method
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blah.f = static_cast<float>(fpu.regs[FPU_GET_TOP()].d);
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blah.f = static_cast<float>(fpu.regs[TOP].d);
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mem_writed(addr,blah.l);
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}
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break;
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case 0x03: /* FSTP */
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case 0x03: /* FSTP float*/
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{
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union {
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float f;
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Bit32u l;
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} blah;
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blah.f = static_cast<float>(fpu.regs[FPU_GET_TOP()].d);
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blah.f = static_cast<float>(fpu.regs[TOP].d);
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mem_writed(addr,blah.l);
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}
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FPU_FPOP();
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@ -250,42 +251,30 @@ void FPU_ESC1_Normal(Bitu rm) {
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Bitu sub=(rm & 7);
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switch (group){
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case 0x00: /* FLD STi */
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{
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Bitu top = FPU_GET_TOP();
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FPU_PUSH(fpu.regs[(top+sub)&7].d);
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}
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FPU_PUSH(fpu.regs[ST(sub)].d);
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break;
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case 0x01: /* FXCH STi */
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{
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Bitu top = FPU_GET_TOP();
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FPU_FXCH(top,(top+sub)&7);
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}
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FPU_FXCH(TOP,ST(sub));
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break;
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case 0x04:
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switch(sub){
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case 0x00: /* FCHS */
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{
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Bitu top = FPU_GET_TOP();
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fpu.regs[top].d = -1.0*(fpu.regs[top].d);
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}
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fpu.regs[TOP].d = -1.0*(fpu.regs[TOP].d);
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break;
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case 0x01: /* FABS */
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{
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Bitu top = FPU_GET_TOP();
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fpu.regs[top].d = fabs(fpu.regs[top].d);
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}
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fpu.regs[TOP].d = fabs(fpu.regs[TOP].d);
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break;
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case 0x02: /* UNKNOWN */
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case 0x03: /* ILLEGAL */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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case 0x04: /* FTST */
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{ Bitu top = FPU_GET_TOP();
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fpu.regs[8].d=0.0;
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FPU_FCOM(top,8);
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}
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fpu.regs[8].d=0.0;
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FPU_FCOM(TOP,8);
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break;
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case 0x05: /* FXAM */
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FPU_FXAM();
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break;
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case 0x06: /* FTSTP (cyrix)*/
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case 0x07: /* UNKNOWN */
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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@ -335,7 +324,9 @@ void FPU_ESC1_Normal(Bitu rm) {
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break;
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case 0x07:
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switch(sub){
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case 0x00: /* FPREM */
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FPU_FPREM();
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break;
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case 0x02: /* FSQRT */
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FPU_FSQRT();
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break;
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@ -344,9 +335,9 @@ void FPU_ESC1_Normal(Bitu rm) {
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break;
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case 0x04: /* FRNDINT */
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{
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Bitu top = FPU_GET_TOP();
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Bit32s temp= static_cast<Bit32s>(FROUND(fpu.regs[top].d));
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fpu.regs[top].d=static_cast<double>(temp);
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//TODO
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Bit64s temp= static_cast<Bit64s>(FROUND(fpu.regs[TOP].d));
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fpu.regs[TOP].d=static_cast<double>(temp);
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}
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//TODO
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break;
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@ -356,6 +347,7 @@ void FPU_ESC1_Normal(Bitu rm) {
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case 0x07: /* FCOS */
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FPU_FCOS();
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break;
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case 0x01: /* FYL2XP1 */
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 1:Unhandled group %X subfunction %X",group,sub);
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break;
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@ -398,15 +390,18 @@ void FPU_ESC3_EA(Bitu rm,PhysPt addr) {
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break;
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case 0x02: /* FIST */
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{ Bitu top = FPU_GET_TOP();
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[top].d)));
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}
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
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break;
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case 0x03: /*FISTP */
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{ Bitu top = FPU_GET_TOP();
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[top].d)));
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FPU_FPOP();
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}
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mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
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FPU_FPOP();
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break;
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case 0x05: /* FLD 80 Bits Real */
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FPU_FLD80(addr);
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break;
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case 0x07: /* FSTP 80 Bits Real */
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FPU_ST80(addr);
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FPU_FPOP();
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break;
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default:
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LOG(LOG_FPU,LOG_WARN)("ESC 3 EA:Unhandled group %d subfunction %d",group,sub);
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@ -458,32 +453,31 @@ void FPU_ESC4_Normal(Bitu rm) {
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//LOOKS LIKE number 6 without popping*/
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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Bitu top = FPU_GET_TOP();
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switch(group){
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case 0x00: /*FADDP STi,ST*/
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FPU_FADD((top+sub)&7,top);
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FPU_FADD(ST(sub),TOP);
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break;
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case 0x01: /* FMULP STi,ST*/
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FPU_FMUL((top+sub)&7,top);
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FPU_FMUL(ST(sub),TOP);
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break;
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case 0x02: /* FCOM*/
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FPU_FCOM(top,(top+sub)&7);
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FPU_FCOM(TOP,ST(sub));
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break; /* TODO IS THIS ALLRIGHT ????????? (maybe reverse operators) */
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case 0x03: /* FCOMP*/
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FPU_FCOM(top,(top+sub)&7);
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FPU_FCOM(TOP,ST(sub));
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FPU_FPOP();
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break;
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case 0x04: /* FSUBRP STi,ST*/
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FPU_FSUBR((top+sub)&7,top);
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FPU_FSUBR(ST(sub),TOP);
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break;
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case 0x05: /* FSUBP STi,ST*/
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FPU_FSUB((top+sub)&7,top);
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FPU_FSUB(ST(sub),TOP);
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break;
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case 0x06: /* FDIVRP STi,ST*/
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FPU_FDIVR((top+sub)&7,top);
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FPU_FDIVR(ST(sub),TOP);
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break;
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case 0x07: /* FDIVP STi,ST*/
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FPU_FDIV((top+sub)&7,top);
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FPU_FDIV(ST(sub),TOP);
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break;
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default:
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break;
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@ -494,7 +488,7 @@ void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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switch(group){
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case 0x00: /* FLD */
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case 0x00: /* FLD double real*/
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{
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FPU_Reg blah;
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blah.l.lower=mem_readd(addr);
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@ -502,24 +496,21 @@ void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
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FPU_PUSH(blah.d);
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}
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break;
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case 0x01: /* FISTTP */
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case 0x01: /* FISTTP longint*/
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LOG(LOG_FPU,LOG_WARN)("ESC 5 EA:Unhandled group %d subfunction %d",group,sub);
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break;
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case 0x02: /* FIST */
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{ Bitu top = FPU_GET_TOP();
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mem_writed(addr,fpu.regs[top].l.lower);
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mem_writed(addr+4,fpu.regs[top].l.upper);
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}
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case 0x02: /* FIST double real*/
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mem_writed(addr,fpu.regs[TOP].l.lower);
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mem_writed(addr+4,fpu.regs[TOP].l.upper);
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break;
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case 0x03: /*FISTP */
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{ Bitu top = FPU_GET_TOP();
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mem_writed(addr,fpu.regs[top].l.lower);
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mem_writed(addr+4,fpu.regs[top].l.upper);
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FPU_FPOP();
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}
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case 0x03: /*FISTP double real*/
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mem_writed(addr,fpu.regs[TOP].l.lower);
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mem_writed(addr+4,fpu.regs[TOP].l.upper);
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FPU_FPOP();
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break;
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case 0x07: /*FNSTSW NG DISAGREES ON THIS*/
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FPU_SET_TOP(TOP);
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mem_writew(addr,fpu.sw);
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//seems to break all dos4gw games :)
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break;
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@ -531,26 +522,25 @@ void FPU_ESC5_EA(Bitu rm,PhysPt addr) {
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void FPU_ESC5_Normal(Bitu rm) {
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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Bitu top = FPU_GET_TOP();
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switch(group){
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case 0x00: /* FFREE STi */
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fpu.tags[(top+sub)&7]=TAG_Empty;
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fpu.tags[ST(sub)]=TAG_Empty;
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break;
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case 0x01: /* FXCH STi*/
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FPU_FXCH(top,(top+sub)&7);
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FPU_FXCH(TOP,ST(sub));
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break;
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case 0x02: /* FST STi */
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FPU_FST(top,(top+sub)&7);
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FPU_FST(TOP,ST(sub));
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break;
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case 0x03: /* FSTP STi*/
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FPU_FST(top,(top+sub)&7);
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FPU_FST(TOP,ST(sub));
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FPU_FPOP();
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break;
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case 0x04: /* FUCOM STi */
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FPU_FUCOM(top,(top+sub)&7);
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FPU_FUCOM(TOP,ST(sub));
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break;
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case 0x05:
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FPU_FUCOM(top,(top+sub)&7);
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case 0x05: /*FUCOMP STi */
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FPU_FUCOM(TOP,ST(sub));
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FPU_FPOP();
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break;
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default:
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@ -572,36 +562,36 @@ void FPU_ESC6_Normal(Bitu rm) {
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/* get top before switch and pop afterwards */
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Bitu group=(rm >> 3) & 7;
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Bitu sub=(rm & 7);
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Bitu top = FPU_GET_TOP();
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switch(group){
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case 0x00: /*FADDP STi,ST*/
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FPU_FADD((top+sub)&7,top);
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FPU_FADD(ST(sub),TOP);
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break;
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case 0x01: /* FMULP STi,ST*/
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FPU_FMUL((top+sub)&7,top);
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FPU_FMUL(ST(sub),TOP);
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break;
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case 0x02: /* FCOMP5*/
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FPU_FCOM(top,(top+sub)&7);
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FPU_FCOM(TOP,ST(sub));
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break; /* TODO IS THIS ALLRIGHT ????????? */
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case 0x03: /* weird*/ /*FCOMPP*/
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if(sub != 1){
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LOG(LOG_FPU,LOG_WARN)("ESC 6:Unhandled group %d subfunction %d",group,sub);
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;
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break;
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}
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FPU_FCOM(top,(top+sub)&7);
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FPU_FPOP();
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FPU_FCOM(TOP,ST(1));
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FPU_FPOP(); /* extra pop at the bottom*/
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break;
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case 0x04: /* FSUBRP STi,ST*/
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FPU_FSUBR((top+sub)&7,top);
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FPU_FSUBR(ST(sub),TOP);
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break;
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case 0x05: /* FSUBP STi,ST*/
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FPU_FSUB((top+sub)&7,top);
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FPU_FSUB(ST(sub),TOP);
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break;
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case 0x06: /* FDIVRP STi,ST*/
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FPU_FDIVR((top+sub)&7,top);
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FPU_FDIVR(ST(sub),TOP);
|
||||
break;
|
||||
case 0x07: /* FDIVP STi,ST*/
|
||||
FPU_FDIV((top+sub)&7,top);
|
||||
FPU_FDIV(ST(sub),TOP);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -627,15 +617,11 @@ void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
|
|||
break;
|
||||
|
||||
case 0x02: /* FIST Bit16s */
|
||||
{ Bitu top = FPU_GET_TOP();
|
||||
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[top].d)));
|
||||
}
|
||||
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[TOP].d)));
|
||||
break;
|
||||
case 0x03: /* FISTP Bit16s */
|
||||
{ Bitu top = FPU_GET_TOP();
|
||||
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[top].d)));
|
||||
FPU_FPOP();
|
||||
}
|
||||
mem_writew(addr,static_cast<Bit16s>(FROUND(fpu.regs[TOP].d)));
|
||||
FPU_FPOP();
|
||||
break;
|
||||
case 0x05: /* FILD Bit32s */
|
||||
{
|
||||
|
|
@ -643,11 +629,13 @@ void FPU_ESC7_EA(Bitu rm,PhysPt addr) {
|
|||
FPU_PUSH( static_cast<double>(blah));
|
||||
}
|
||||
break;
|
||||
case 0x06: /* FBSTP packed BCD */
|
||||
FPU_FBST(addr);
|
||||
FPU_FPOP();
|
||||
break;
|
||||
case 0x07: /* FISTP Bit32s */
|
||||
{ Bitu top = FPU_GET_TOP();
|
||||
mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[top].d)));
|
||||
FPU_FPOP();
|
||||
}
|
||||
mem_writed(addr,static_cast<Bit32s>(FROUND(fpu.regs[TOP].d)));
|
||||
FPU_FPOP();
|
||||
break;
|
||||
default:
|
||||
LOG(LOG_FPU,LOG_WARN)("ESC 7 EA:Unhandled group %d subfunction %d",group,sub);
|
||||
|
|
@ -661,6 +649,7 @@ void FPU_ESC7_Normal(Bitu rm) {
|
|||
case 0x04:
|
||||
switch(sub){
|
||||
case 0x00: /* FNSTSW AX*/
|
||||
FPU_SET_TOP(TOP);
|
||||
reg_ax = fpu.sw;
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue