From e92e17addd702efceeb5db86de74edc38032c685 Mon Sep 17 00:00:00 2001
From: Sjoerd van der Berg <harekiet@users.sourceforge.net>
Date: Sun, 26 Oct 2003 18:58:46 +0000
Subject: [PATCH] New lazy flag header file

Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1377
---
 include/cpu.h  |  3 +--
 include/regs.h | 33 +++++++--------------------------
 2 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/include/cpu.h b/include/cpu.h
index 40ea13f0..3aeeae1d 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -88,13 +88,12 @@ void CPU_Push32(Bitu value);
 
 void CPU_SetFlags(Bitu word);
 
-
 INLINE void CPU_SetFlagsd(Bit32u word) {
 	CPU_SetFlags(word);
 };
 
 INLINE void CPU_SetFlagsw(Bit16u word) {
-	CPU_SetFlags((flags.word&0xffff0000)|word);
+	CPU_SetFlags((cpu_regs.flags&0xffff0000)|word);
 };
 
 
diff --git a/include/regs.h b/include/regs.h
index a3a266f0..35981184 100644
--- a/include/regs.h
+++ b/include/regs.h
@@ -21,19 +21,6 @@
 
 #include <mem.h>
 
-struct Flag_Info {
-    union {
-		Bit8u b;
-		Bit16u w;
-		Bit32u d;
-	} var1,var2,result;
-	Bitu type;
-	Bitu prev_type;
-	Bitu oldcf;
-	Bitu word;
-};
-
-
 #define FLAG_CF		0x00000001
 #define FLAG_PF		0x00000004
 #define FLAG_AF		0x00000010
@@ -50,11 +37,10 @@ struct Flag_Info {
 #define FLAG_NT		0x00004000
 #define FLAG_VM		0x00020000
 
+#define SETFLAGBIT(TYPE,TEST) if (TEST) reg_flags|=FLAG_ ## TYPE; else reg_flags&=~FLAG_ ## TYPE
 
-#define SETFLAGBIT(TYPE,TEST) if (TEST) flags.word|=FLAG_ ## TYPE; else flags.word&=~FLAG_ ## TYPE
-
-#define GETFLAG(TYPE) (flags.word & FLAG_ ## TYPE)
-#define GETFLAGBOOL(TYPE) ((flags.word & FLAG_ ## TYPE) ? true : false )
+#define GETFLAG(TYPE) (reg_flags & FLAG_ ## TYPE)
+#define GETFLAGBOOL(TYPE) ((reg_flags & FLAG_ ## TYPE) ? true : false )
 
 struct Segment {
 	Bit16u val;
@@ -91,17 +77,13 @@ union GenReg32 {
 #endif
 
 struct CPU_Regs {
-	 GenReg32 regs[8],ip;
+	GenReg32 regs[8],ip;
+	Bitu flags;
 };
 
 extern Segments Segs;
-extern Flag_Info flags;
 extern CPU_Regs cpu_regs;
 
-
-//#define SegPhys(index) Segs[index].phys
-//#define SegValue(index) Segs[index].val
-
 INLINE PhysPt SegPhys(SegNames index) {
 	return Segs.phys[index];
 }
@@ -109,7 +91,6 @@ INLINE PhysPt SegPhys(SegNames index) {
 INLINE Bit16u SegValue(SegNames index) {
 	return Segs.val[index];
 }
-
 	
 INLINE RealPt RealMakeSeg(SegNames index,Bit16u off) {
 	return RealMake(SegValue(index),off);	
@@ -121,7 +102,6 @@ INLINE void SegSet16(Bitu index,Bit16u val) {
 	Segs.phys[index]=val << 4;
 }
 
-
 enum {
 	REGI_AX, REGI_CX, REGI_DX, REGI_BX,
 	REGI_SP, REGI_BP, REGI_SI, REGI_DI
@@ -140,7 +120,6 @@ enum {
 #define reg_16(reg) (cpu_regs.regs[(reg)].word[W_INDEX])
 #define reg_32(reg) (cpu_regs.regs[(reg)].dword[DW_INDEX])
 
-
 #define reg_al cpu_regs.regs[REGI_AX].byte[BL_INDEX]
 #define reg_ah cpu_regs.regs[REGI_AX].byte[BH_INDEX]
 #define reg_ax cpu_regs.regs[REGI_AX].word[W_INDEX]
@@ -176,5 +155,7 @@ enum {
 #define reg_ip cpu_regs.ip.word[W_INDEX]
 #define reg_eip cpu_regs.ip.dword[DW_INDEX]
 
+#define reg_flags cpu_regs.flags
+
 #endif