Enable NEON SIMD for corresponding ARM platforms
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5 changed files with 60 additions and 5 deletions
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# GCC flags for generically identified AArch64
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# Note: Advanced SIMD (aka NEON) is mandatory for AArch64 and implied
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cflags_release+=(-mcpu=native -mstrict-align)
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# Note: NEON SIMD instructions for floating-point operations are
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# not generated by GCC’s auto-vectorization pass unless
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# -funsafe-math-optimizations is also specified. This is because
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# NEON hardware does not fully implement the IEEE 754 standard for
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# some floating-point arithmetic operations, specifically
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# "denormal" values are treated as zero, so in these corner-cases,
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# the use of NEON instructions may lead to a loss of precision.
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# For our purposes, we expect to perform normal calculations and
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# thus accept this risk for release builds.
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cflags_release+=(-mcpu=native -funsafe-math-optimizations -mstrict-align)
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# GCC flags for generically identified ARMv7 MALI SBCs
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cflags_release+=(-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=hard)
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# Note: NEON SIMD instructions for floating-point operations are
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# not generated by GCC’s auto-vectorization pass unless
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# -funsafe-math-optimizations is also specified. This is because
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# NEON hardware does not fully implement the IEEE 754 standard for
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# some floating-point arithmetic operations, specifically
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# "denormal" values are treated as zero, so in these corner-cases,
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# the use of NEON instructions may lead to a loss of precision.
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# For our purposes, we expect to perform normal calculations and
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# thus accept this risk for release builds.
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cflags_release+=(-march=armv7-a -funsafe-math-optimizations -mfpu=neon-vfpv4 -mfloat-abi=hard)
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# GCC flags specific to the Raspberry Pi 2 series of SBC
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cflags_release+=(-mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard)
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# Note: NEON SIMD instructions for floating-point operations are
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# not generated by GCC’s auto-vectorization pass unless
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# -funsafe-math-optimizations is also specified. This is because
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# NEON hardware does not fully implement the IEEE 754 standard for
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# some floating-point arithmetic operations, specifically
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# "denormal" values are treated as zero, so in these corner-cases,
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# the use of NEON instructions may lead to a loss of precision.
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# For our purposes, we expect to perform normal calculations and
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# thus accept this risk for release builds.
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cflags_release+=(-mcpu=cortex-a7 -funsafe-math-optimizations -mfpu=neon-vfpv4 -mfloat-abi=hard)
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# GCC flags specific to the Raspberry Pi 3 series of SBC
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cflags_release+=(-march=armv8-a+crc -mtune=cortex-a53
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# Note: NEON SIMD instructions for floating-point operations are
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# not generated by GCC’s auto-vectorization pass unless
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# -funsafe-math-optimizations is also specified. This is because
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# NEON hardware does not fully implement the IEEE 754 standard for
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# some floating-point arithmetic operations, specifically
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# "denormal" values are treated as zero, so in these corner-cases,
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# the use of NEON instructions may lead to a loss of precision.
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# For our purposes, we expect to perform normal calculations and
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# thus accept this risk for release builds.
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cflags_release+=(-march=armv8-a+crc -mtune=cortex-a53 -funsafe-math-optimizations
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-mfpu=neon-fp-armv8 -mfloat-abi=hard)
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# GCC flags specific to the Raspberry Pi 4 series of SBC
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cflags_release+=(-march=armv8-a+crc -mtune=cortex-a72
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# Note: NEON SIMD instructions for floating-point operations are
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# not generated by GCC’s auto-vectorization pass unless
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# -funsafe-math-optimizations is also specified. This is because
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# NEON hardware does not fully implement the IEEE 754 standard for
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# some floating-point arithmetic operations, specifically
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# "denormal" values are treated as zero, so in these corner-cases,
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# the use of NEON instructions may lead to a loss of precision.
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# For our purposes, we expect to perform normal calculations and
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# thus accept this risk for release builds.
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cflags_release+=(-march=armv8-a+crc -mtune=cortex-a72 -funsafe-math-optimizations
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-mfpu=neon-fp-armv8 -mfloat-abi=hard)
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