Implemented 16-bit DMA support
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1398
This commit is contained in:
Dean Beeler
parent
9d8d93a7dd
commit
ed4d000c14
2 changed files with 513 additions and 251 deletions
333
include/dma.h
333
include/dma.h
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@ -16,14 +16,347 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __DMA_H
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#define __DMA_H
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#include "mem.h"
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#define DMA_MODE_DEMAND 0
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#define DMA_MODE_SINGLE 1
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#define DMA_MODE_BLOCK 2
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#define DMA_MODE_CASCADE 3
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#define DMA_BASEADDR 0
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#define DMA_TRANSCOUNT 1
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#define DMA_PAGEREG 2
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#define DMA_CMDREG 0
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#define DMA_MODEREG 1
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#define DMA_CLEARREG 2
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#define DMA_DMACREG 3
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#define DMA_CLRMASKREG 4
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#define DMA_SINGLEREG 5
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#define DMA_WRITEALLREG 6
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static Bit8u ChannelPorts [3][8] = { 0x00, 0x02, 0x04, 0x06, 0xff, 0xc4, 0xc8, 0xcc,
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0x01, 0x03, 0x05, 0x07, 0xff, 0xc6, 0xca, 0xce,
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0x87, 0x83, 0x81, 0x82, 0xff, 0x8b, 0x89, 0x8a };
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static Bit8u ControllerPorts [2][7] = { 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, 0xf,
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0xd0, 0xd6, 0xd8, 0xda, 0xdc, 0xd4, 0xde };
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typedef void (* DMA_EnableCallBack)(bool enable);
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typedef void (* DMA_NewCallBack)(void *useChannel, bool tc);
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void DMA_SetEnableCallBack(Bitu channel,DMA_EnableCallBack callback);
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void DMA_CheckEnabled(void * usechan);
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Bitu DMA_8_Read(Bitu channel,Bit8u * buffer,Bitu count);
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Bitu DMA_8_Write(Bitu dmachan,Bit8u * buffer,Bitu count);
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Bitu DMA_16_Read(Bitu channel,Bit8u * buffer,Bitu count);
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Bitu DMA_16_Write(Bitu dmachan,Bit8u * buffer,Bitu count);
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extern Bit8u read_dmaB(Bit32u port);
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extern Bit16u read_dmaW(Bit32u port);
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extern void write_dmaB(Bit32u port,Bit8u val);
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extern void write_dmaW(Bit32u port,Bit16u val);
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class DmaController {
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public:
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bool flipflop;
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Bit8u ctrlnum;
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public:
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DmaController(Bit8u num) {
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int i;
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for(i=0;i<7;i++) {
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IO_RegisterReadBHandler(ControllerPorts[num][i],read_dmaB);
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IO_RegisterReadWHandler(ControllerPorts[num][i],read_dmaW);
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IO_RegisterWriteBHandler(ControllerPorts[num][i],write_dmaB);
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IO_RegisterWriteWHandler(ControllerPorts[num][i],write_dmaW);
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}
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flipflop = true;
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ctrlnum = num;
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}
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Bit16u portRead(Bit32u port, bool eightbit);
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void portWrite(Bit32u port, Bit16u val, bool eightbit);
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};
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#define ff myController->flipflop
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class DmaChannel {
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public:
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Bit8u channum;
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Bit16u baseaddr;
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Bit16u current_addr;
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Bit16u pageaddr;
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PhysPt physaddr;
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PhysPt curraddr;
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Bit32s transcnt;
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Bit32s currcnt;
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DmaController *myController;
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bool DMA16;
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public:
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Bit8u dmamode;
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bool dir;
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bool autoinit;
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Bit8u trantype;
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bool masked;
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bool enabled;
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DMA_EnableCallBack enable_callback;
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DMA_NewCallBack newcallback;
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DmaChannel(Bit8u num, DmaController *useController, bool sb) {
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int i;
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masked = true;
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enabled = false;
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enable_callback = NULL;
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newcallback = NULL;
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if(num == 4) return;
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for(i=0;i<3;i++) {
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IO_RegisterReadBHandler(ChannelPorts[i][num],read_dmaB);
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IO_RegisterReadWHandler(ChannelPorts[i][num],read_dmaW);
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IO_RegisterWriteBHandler(ChannelPorts[i][num],write_dmaB);
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IO_RegisterWriteWHandler(ChannelPorts[i][num],write_dmaW);
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}
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myController = useController;
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channum = num;
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DMA16 = sb;
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baseaddr = 0;
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pageaddr = 0;
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physaddr = 0;
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curraddr = 0;
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transcnt = 0;
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currcnt = 0;
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dir = false;
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autoinit = false;
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}
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void RegisterCallback(DMA_NewCallBack useCallBack) { newcallback = useCallBack; }
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void reset(void) {
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curraddr = physaddr;
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currcnt = transcnt+1;
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current_addr = baseaddr;
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//LOG(LOG_DMA,LOG_NORMAL)("Setup at address %X:%X count %X",pageaddr,baseaddr,currcnt);
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}
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void MakeCallback(bool tc) {
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if (newcallback != NULL) {
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if(tc) {
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(*newcallback)(this, true);
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} else {
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if ((enabled) && (!masked) && (transcnt!=0)) {
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(*newcallback)(this, false);
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}
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}
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}
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}
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Bit32u Read(Bit32s requestsize, Bit8u * buffer) {
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Bit32s bytesread;
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bytesread = 0;
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if(autoinit) {
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while(requestsize>0) {
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if(currcnt>=requestsize) {
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MEM_BlockRead(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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bytesread+=requestsize;
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requestsize=0;
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break;
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} else {
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MEM_BlockRead(curraddr,buffer,currcnt);
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bytesread+=currcnt;
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buffer+=currcnt;
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requestsize-=currcnt;
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reset();
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MakeCallback(true);
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}
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}
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if(currcnt==0) {
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reset();
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MakeCallback(true);
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}
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return bytesread;
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} else {
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if(currcnt>=requestsize) {
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MEM_BlockRead(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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bytesread+=requestsize;
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} else {
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MEM_BlockRead(curraddr,buffer,currcnt);
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buffer+=currcnt;
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requestsize-=currcnt;
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bytesread+=currcnt;
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currcnt=0;
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}
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}
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if(currcnt==0) MakeCallback(true);
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return bytesread;
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}
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Bit32u Write(Bit32s requestsize, Bit8u * buffer) {
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Bit32s byteswrite;
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byteswrite = 0;
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if(autoinit) {
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while(requestsize>0) {
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if(currcnt>=requestsize) {
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MEM_BlockWrite(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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byteswrite+=requestsize;
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requestsize=0;
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break;
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} else {
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MEM_BlockWrite(curraddr,buffer,currcnt);
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byteswrite+=currcnt;
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buffer+=currcnt;
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requestsize-=currcnt;
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reset();
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MakeCallback(true);
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}
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}
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if(currcnt==0) {
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reset();
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MakeCallback(true);
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}
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return byteswrite;
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} else {
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if(currcnt>=requestsize) {
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MEM_BlockWrite(curraddr,buffer,requestsize);
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curraddr+=requestsize;
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buffer+=requestsize;
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currcnt-=requestsize;
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byteswrite+=requestsize;
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} else {
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MEM_BlockWrite(curraddr,buffer,currcnt);
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buffer+=currcnt;
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requestsize-=currcnt;
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byteswrite+=currcnt;
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currcnt=0;
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}
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}
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if(currcnt==0) MakeCallback(true);
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return byteswrite;
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}
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void calcPhys(void) {
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if (DMA16) {
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physaddr = (baseaddr << 1) | ((pageaddr >> 1) << 17);
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} else {
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physaddr = (baseaddr) | (pageaddr << 16);
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}
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curraddr = physaddr;
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current_addr = baseaddr;
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}
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Bit16u portRead(Bit32u port, bool eightbit) {
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if (port == ChannelPorts[DMA_BASEADDR][channum]) {
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if(eightbit) {
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if(ff) {
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ff = !ff;
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return current_addr & 0xff;
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} else {
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ff = !ff;
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return current_addr >> 8;
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}
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} else {
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return current_addr;
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}
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}
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if (port == ChannelPorts[DMA_TRANSCOUNT][channum]) {
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if(eightbit) {
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if(ff) {
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ff = !ff;
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return (Bit8u)(currcnt & 0xff);
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} else {
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ff = !ff;
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return (Bit8u)(currcnt >> 8);
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}
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} else {
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return (Bit16u)currcnt;
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}
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}
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if (port == ChannelPorts[DMA_PAGEREG][channum]) return pageaddr;
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return 0xffff;
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}
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void portWrite(Bit32u port, Bit16u val, bool eightbit) {
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if (port == ChannelPorts[DMA_BASEADDR][channum]) {
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if(eightbit) {
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if(ff) {
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baseaddr = (baseaddr & 0xff00) | (Bit8u)val;
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} else {
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baseaddr = (baseaddr & 0xff) | (val << 8);
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}
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ff = !ff;
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} else {
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baseaddr = val;
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}
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calcPhys();
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reset();
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}
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if (port == ChannelPorts[DMA_TRANSCOUNT][channum]) {
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if(eightbit) {
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if(ff) {
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transcnt = (transcnt & 0xff00) | (Bit8u)val;
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} else {
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transcnt = (transcnt & 0xff) | (val << 8);
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}
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ff = !ff;
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} else {
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transcnt = val;
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}
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currcnt = transcnt+1;
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reset();
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DMA_CheckEnabled(this);
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MakeCallback(false);
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}
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if (port == ChannelPorts[DMA_PAGEREG][channum]) {
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pageaddr = val;
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calcPhys();
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reset();
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}
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}
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// Notify channel when mask changes
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void Notify(void) {
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if(!masked) {
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DMA_CheckEnabled(this);
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MakeCallback(false);
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}
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}
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};
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#undef ff
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extern DmaChannel *DmaChannels[8];
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extern DmaController *DmaControllers[2];
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#endif
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@ -20,11 +20,6 @@
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Based the port handling from the bochs dma code.
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*/
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/*
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TODO
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Implement 16-bit dma
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*/
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#include <string.h>
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#include "dosbox.h"
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#include "mem.h"
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@ -32,259 +27,193 @@
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#include "dma.h"
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#include "pic.h"
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#define DMA_MODE_DEMAND 0
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#define DMA_MODE_SINGLE 1
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#define DMA_MODE_BLOCK 2
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#define DMA_MODE_CASCADE 3
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struct DMA_CHANNEL {
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struct {
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Bit8u mode_type;
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bool address_decrement;
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bool autoinit_enable;
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Bit8u transfer_type;
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} mode;
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Bit16u base_address;
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Bit16u base_count;
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Bit16u current_address;
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Bitu current_count;
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Bit8u page;
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bool masked;
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PhysPt address;
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bool addr_changed;
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bool enabled;
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DMA_EnableCallBack enable_callback;
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};
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DmaChannel *DmaChannels[8];
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DmaController *DmaControllers[2];
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struct DMA_CONTROLLER {
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bool flipflop;
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Bit8u status_reg;
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Bit8u command_reg;
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DMA_CHANNEL chan[4];
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};
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Bit16u DmaController::portRead(Bit32u port, bool eightbit) {
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LOG_MSG("Reading DMA controller at %x", port);
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return 0xffff;
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}
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static DMA_CONTROLLER dma[2];
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void DMA_CheckEnabled(DMA_CHANNEL * chan);
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void DMA_SetEnabled(DMA_CHANNEL * chan,bool enabled);
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static Bit8u read_dma(Bit32u port) {
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/* only use first dma for now */
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DMA_CONTROLLER * cont=&dma[0];
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DMA_CHANNEL * chan=&cont->chan[port>>1];
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Bit8u ret;
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switch (port) {
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case 0x00:case 0x02:case 0x04:case 0x06:
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if (cont->flipflop) {
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ret=chan->current_address & 0xff;
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} else {
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ret=(chan->current_address>>8)&0xff;
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}
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cont->flipflop=!cont->flipflop;
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break;
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case 0x01:case 0x03:case 0x05:case 0x07:
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if (cont->flipflop) {
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ret=(Bit8u)((chan->current_count-1) & 0xff);
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} else {
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ret=(Bit8u)(((chan->current_count-1)>>8)&0xff);
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}
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cont->flipflop=!cont->flipflop;
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break;
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case 0x08: /* Read Status */
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ret=cont->status_reg;
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cont->status_reg&=~0xf; /* Clear lower 4 bits on read */
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break;
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case 0x0a:
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case 0x0e:
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/* Seem to return 0 on a real controller */
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ret=0x0;
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break;
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default:
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LOG(LOG_DMA,LOG_ERROR)("DMA:Unhandled read from %X",port);
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void DmaController::portWrite(Bit32u port, Bit16u val, bool eightbit) {
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bool found;
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found = false;
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if(port == ControllerPorts[ctrlnum][DMA_CLRMASKREG]) {
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found = true;
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flipflop = true;
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// Disable DMA requests
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// Clear command and status registers
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}
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// LOG_MSG("DMA Read port %x result %x",port,ret);
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return ret;
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}
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static void write_dma(Bit32u port,Bit8u val) {
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/* only use first dma for now */
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DMA_CONTROLLER * cont=&dma[0];
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DMA_CHANNEL * chan;
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switch (port) {
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case 0x00:case 0x02:case 0x04:case 0x06:
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chan=&cont->chan[port>>1];
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if (cont->flipflop) {
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chan->base_address=(chan->base_address & 0xff00) | val;
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} else {
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chan->base_address=(chan->base_address & 0x00ff) | (val<<8);
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}
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cont->flipflop=!cont->flipflop;
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chan->addr_changed=true;
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break;
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case 0x01:case 0x03:case 0x05:case 0x07:
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chan=&cont->chan[port>>1];
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if (cont->flipflop) {
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chan->base_count=(chan->base_count & 0xff00) | val;
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} else {
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chan->base_count=(chan->base_count & 0x00ff) | (val<<8);
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}
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cont->flipflop=!cont->flipflop;
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chan->addr_changed=true;
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DMA_CheckEnabled(chan);
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break;
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case 0x08: /* Command Register */
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if (val != 4) LOG(LOG_DMA,LOG_ERROR)("DMA1:Illegal command %2X",val);
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cont->command_reg=val;
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break;
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case 0x09: /* Request Register */
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if (val&4) {
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/* Set Request bit */
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Bitu channel = val & 0x03;
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cont->status_reg |= (1 << (channel+4));
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} else {
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Bitu channel = val & 0x03;
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cont->status_reg &= ~(1 << (channel+4));
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}
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break;
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case 0x0a: /* single mask bit register */
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chan=&cont->chan[val & 0x3];
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if ((val & 4)>0) {
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DMA_SetEnabled(chan,false);
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chan->masked=(val & 4)>0; //Set it later
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} else {
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chan->masked=(val & 4)>0;
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DMA_CheckEnabled(chan);
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}
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break;
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case 0x0b: /* mode register */
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chan=&cont->chan[val & 0x3];
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chan->mode.mode_type = (val >> 6) & 0x03;
|
||||
chan->mode.address_decrement = (val & 0x20) > 0;
|
||||
chan->mode.autoinit_enable = (val & 0x10) > 0;
|
||||
chan->mode.transfer_type = (val >> 2) & 0x03;
|
||||
if (chan->mode.address_decrement) {
|
||||
LOG(LOG_DMA,LOG_ERROR)("DMA:Address Decrease not supported yet");
|
||||
}
|
||||
DMA_CheckEnabled(chan);
|
||||
break;
|
||||
case 0x0c: /* Clear Flip/Flip */
|
||||
cont->flipflop=true;
|
||||
break;
|
||||
default:
|
||||
LOG(LOG_DMA,LOG_ERROR)("DMA:Unhandled write %X to %X",static_cast<Bit32u>(val),port);
|
||||
};
|
||||
};
|
||||
|
||||
void write_dma_page(Bit32u port,Bit8u val) {
|
||||
Bitu channel;
|
||||
switch (port) {
|
||||
case 0x81: /* dma0 page register, channel 2 */
|
||||
channel=2;break;
|
||||
case 0x82: /* dma0 page register, channel 3 */
|
||||
channel=3;break;
|
||||
case 0x83: /* dma0 page register, channel 1 */
|
||||
channel=1;break;
|
||||
case 0x87: /* dma0 page register, channel 0 */
|
||||
channel=0;break;
|
||||
if(port == ControllerPorts[ctrlnum][DMA_SINGLEREG]) {
|
||||
found = true;
|
||||
int dmachan;
|
||||
dmachan = (ctrlnum * 2) + (val & 0x3);
|
||||
DmaChannels[dmachan]->masked = ((val & 0x4) == 0x4);
|
||||
DmaChannels[dmachan]->Notify();
|
||||
}
|
||||
dma[0].chan[channel].page=val;
|
||||
dma[0].chan[channel].addr_changed=true;
|
||||
}
|
||||
|
||||
Bit8u read_dma_page(Bit32u port) {
|
||||
Bitu channel;
|
||||
switch (port) {
|
||||
case 0x81: /* dma0 page register, channel 2 */
|
||||
channel=2;break;
|
||||
case 0x82: /* dma0 page register, channel 3 */
|
||||
channel=3;break;
|
||||
case 0x83: /* dma0 page register, channel 1 */
|
||||
channel=1;break;
|
||||
case 0x87: /* dma0 page register, channel 0 */
|
||||
channel=0;break;
|
||||
if(port == ControllerPorts[ctrlnum][DMA_WRITEALLREG]) {
|
||||
found = true;
|
||||
int dmachan,i,r;
|
||||
dmachan = (ctrlnum * 2);
|
||||
r = 0;
|
||||
for(i=dmachan;i<dmachan+4;i++) {
|
||||
DmaChannels[i]->masked = (((val >> r) & 0x1) == 0x1);
|
||||
DmaChannels[i]->Notify();
|
||||
r++;
|
||||
}
|
||||
}
|
||||
return dma[0].chan[channel].page;
|
||||
if(port == ControllerPorts[ctrlnum][DMA_CLEARREG]) {
|
||||
found = true;
|
||||
flipflop = true;
|
||||
}
|
||||
if(port == ControllerPorts[ctrlnum][DMA_MODEREG]) {
|
||||
found = true;
|
||||
int dmachan;
|
||||
dmachan = (ctrlnum * 2) + (val & 0x3);
|
||||
DmaChannels[dmachan]->trantype = (val >> 2) & 0x3;
|
||||
DmaChannels[dmachan]->autoinit = ((val & 0x10) == 0x10);
|
||||
DmaChannels[dmachan]->dir = ((val & 0x20) == 0x20);
|
||||
DmaChannels[dmachan]->dmamode = (val >> 6) & 0x3;
|
||||
DMA_CheckEnabled(DmaChannels[dmachan]);
|
||||
}
|
||||
if(!found) LOG_MSG("Write to DMA port %x with %x", port, val);
|
||||
|
||||
}
|
||||
|
||||
INLINE void ResetDMA8(DMA_CHANNEL * chan) {
|
||||
chan->addr_changed=false;
|
||||
chan->address=(chan->page << 16)+chan->base_address;
|
||||
chan->current_count=chan->base_count+1;
|
||||
chan->current_address=chan->base_address;
|
||||
LOG(LOG_DMA,LOG_NORMAL)("Setup at address %X:%X count %X",chan->page<<12,chan->base_address,chan->current_count);
|
||||
|
||||
static Bit16u readDMAPorts(Bit32u port, bool eightbit) {
|
||||
int i,j;
|
||||
|
||||
// Check for controller access
|
||||
for(i=0;i<2;i++) {
|
||||
for(j=0;j<7;j++) {
|
||||
if(ControllerPorts[i][j] == port) {
|
||||
return DmaControllers[i]->portRead(port, eightbit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Check for DMA access
|
||||
for(i=0;i<8;i++) {
|
||||
for(j=0;j<3;j++) {
|
||||
if(ChannelPorts[j][i] == port) {
|
||||
return DmaChannels[i]->portRead(port, eightbit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
LOG_MSG("Unmatched read port %x", port);
|
||||
|
||||
return 0xffff;
|
||||
|
||||
}
|
||||
|
||||
static void writeDMAPorts(Bit32u port, Bit16u val, bool eightbit) {
|
||||
int i,j;
|
||||
|
||||
// Check for controller access
|
||||
for(i=0;i<2;i++) {
|
||||
for(j=0;j<7;j++) {
|
||||
if(ControllerPorts[i][j] == port) {
|
||||
DmaControllers[i]->portWrite(port,val,eightbit);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Check for DMA access
|
||||
for(i=0;i<8;i++) {
|
||||
for(j=0;j<3;j++) {
|
||||
if(ChannelPorts[j][i] == port) {
|
||||
DmaChannels[i]->portWrite(port,val,eightbit);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
LOG_MSG("Unmatched write port %x - val %x", port, val);
|
||||
|
||||
}
|
||||
|
||||
Bit8u read_dmaB(Bit32u port) { return (Bit8u)readDMAPorts(port,true); }
|
||||
|
||||
Bit16u read_dmaW(Bit32u port) { return readDMAPorts(port,false); }
|
||||
|
||||
void write_dmaB(Bit32u port,Bit8u val) { writeDMAPorts(port,val,true); }
|
||||
|
||||
void write_dmaW(Bit32u port,Bit16u val) { writeDMAPorts(port,val,false); }
|
||||
|
||||
|
||||
// Deprecated DMA read/write routines -- Keep compatibility with Sound Blaster
|
||||
Bitu DMA_8_Read(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
DMA_CHANNEL * chan=&dma[0].chan[dmachan];
|
||||
DmaChannel *chan=DmaChannels[dmachan];
|
||||
|
||||
if (chan->masked) return 0;
|
||||
if (!count) return 0;
|
||||
if (chan->addr_changed) ResetDMA8(chan);
|
||||
if (chan->current_count>count) {
|
||||
MEM_BlockRead(chan->address,buffer,count);
|
||||
chan->address+=count;
|
||||
chan->current_address+=count;
|
||||
chan->current_count-=count;
|
||||
if (chan->currcnt>count) {
|
||||
MEM_BlockRead(chan->curraddr,buffer,count);
|
||||
chan->curraddr+=count;
|
||||
chan->current_addr+=count;
|
||||
chan->currcnt-=count;
|
||||
return count;
|
||||
} else {
|
||||
/* Copy remaining piece of first buffer */
|
||||
MEM_BlockRead(chan->address,buffer,chan->current_count);
|
||||
if (!chan->mode.autoinit_enable) {
|
||||
/* Set the end of counter bit */
|
||||
dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->current_count;
|
||||
chan->address+=count;
|
||||
chan->current_count=0;
|
||||
// Copy remaining piece of first buffer
|
||||
MEM_BlockRead(chan->curraddr,buffer,chan->currcnt);
|
||||
if (!chan->autoinit) {
|
||||
// Set the end of counter bit
|
||||
//dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->currcnt;
|
||||
chan->curraddr+=count;
|
||||
chan->current_addr+=count;
|
||||
chan->currcnt=0;
|
||||
chan->enabled=false;
|
||||
LOG(LOG_DMA,LOG_NORMAL)("8-bit Channel %d reached terminal count");
|
||||
return count;
|
||||
} else {
|
||||
buffer+=chan->current_count;
|
||||
Bitu left=count-(Bit16u)chan->current_count;
|
||||
/* Autoinit reset the dma channel */
|
||||
ResetDMA8(chan);
|
||||
/* Copy the rest of the buffer */
|
||||
MEM_BlockRead(chan->address,buffer,left);
|
||||
chan->address+=left;
|
||||
chan->current_address+=left;
|
||||
chan->current_count-=left;
|
||||
buffer+=chan->currcnt;
|
||||
Bitu left=count-(Bit16u)chan->currcnt;
|
||||
// Autoinit reset the dma channel
|
||||
chan->reset();
|
||||
// Copy the rest of the buffer
|
||||
MEM_BlockRead(chan->curraddr,buffer,left);
|
||||
chan->curraddr+=left;
|
||||
chan->current_addr+=left;
|
||||
chan->currcnt-=left;
|
||||
return count;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Bitu DMA_8_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
||||
DMA_CHANNEL * chan=&dma[0].chan[dmachan];
|
||||
DmaChannel *chan=DmaChannels[dmachan];
|
||||
|
||||
if (chan->masked) return 0;
|
||||
if (!count) return 0;
|
||||
if (chan->addr_changed) ResetDMA8(chan);
|
||||
if (chan->current_count>count) {
|
||||
MEM_BlockWrite(chan->address,buffer,count);
|
||||
chan->address+=count;
|
||||
chan->current_address+=count;
|
||||
chan->current_count-=count;
|
||||
if (chan->currcnt>count) {
|
||||
MEM_BlockWrite(chan->curraddr,buffer,count);
|
||||
chan->curraddr+=count;
|
||||
chan->currcnt-=count;
|
||||
return count;
|
||||
} else {
|
||||
/* Copy remaining piece of first buffer */
|
||||
MEM_BlockWrite(chan->address,buffer,chan->current_count);
|
||||
if (!chan->mode.autoinit_enable) {
|
||||
/* Set the end of counter bit */
|
||||
dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->current_count;
|
||||
chan->current_address+=count;;
|
||||
chan->current_count=0;
|
||||
chan->enabled=false;
|
||||
// Copy remaining piece of first buffer
|
||||
MEM_BlockWrite(chan->curraddr,buffer,chan->currcnt);
|
||||
if (!chan->autoinit) {
|
||||
// Set the end of counter bit
|
||||
//dma[0].status_reg|=(1 << dmachan);
|
||||
count=chan->currcnt;
|
||||
chan->curraddr+=count;;
|
||||
chan->currcnt=0;
|
||||
return count;
|
||||
} else {
|
||||
buffer+=chan->current_count;
|
||||
Bitu left=count-(Bit16u)chan->current_count;
|
||||
/* Autoinit reset the dma channel */
|
||||
ResetDMA8(chan);
|
||||
/* Copy the rest of the buffer */
|
||||
MEM_BlockWrite(chan->address,buffer,left);
|
||||
chan->address+=left;
|
||||
chan->current_address+=left;
|
||||
chan->current_count-=left;
|
||||
buffer+=chan->currcnt;
|
||||
Bitu left=count-(Bit16u)chan->currcnt;
|
||||
// Autoinit reset the dma channel
|
||||
chan->reset();
|
||||
// Copy the rest of the buffer
|
||||
MEM_BlockWrite(chan->curraddr,buffer,left);
|
||||
chan->curraddr+=left;
|
||||
chan->currcnt-=left;
|
||||
return count;
|
||||
}
|
||||
}
|
||||
|
|
@ -302,18 +231,21 @@ Bitu DMA_16_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
void DMA_SetEnabled(DMA_CHANNEL * chan,bool enabled) {
|
||||
void DMA_SetEnabled(DmaChannel * chan,bool enabled) {
|
||||
if (chan->enabled == enabled) return;
|
||||
chan->enabled=enabled;
|
||||
if (chan->enable_callback) (*chan->enable_callback)(enabled);
|
||||
}
|
||||
|
||||
void DMA_CheckEnabled(DMA_CHANNEL * chan) {
|
||||
void DMA_CheckEnabled(void * usechan) {
|
||||
DmaChannel * chan;
|
||||
chan = (DmaChannel *)usechan;
|
||||
|
||||
bool enabled;
|
||||
if (chan->masked) enabled=false;
|
||||
else {
|
||||
if (chan->mode.autoinit_enable) enabled=true;
|
||||
else if (chan->current_count || chan->addr_changed) enabled=true;
|
||||
if (chan->autoinit) enabled=true;
|
||||
else if (chan->currcnt) enabled=true;
|
||||
else enabled=false;
|
||||
}
|
||||
DMA_SetEnabled(chan,enabled);
|
||||
|
|
@ -321,31 +253,28 @@ void DMA_CheckEnabled(DMA_CHANNEL * chan) {
|
|||
|
||||
|
||||
void DMA_SetEnableCallBack(Bitu channel,DMA_EnableCallBack callback) {
|
||||
DMA_CHANNEL * chan;
|
||||
if (channel<4) {
|
||||
chan=&dma[0].chan[channel];
|
||||
} else if (channel<8) {
|
||||
chan=&dma[1].chan[channel-4];
|
||||
} else return;
|
||||
DmaChannel * chan;
|
||||
chan = DmaChannels[channel];
|
||||
chan->enabled=false;
|
||||
chan->enable_callback=callback;
|
||||
DMA_CheckEnabled(chan);
|
||||
}
|
||||
|
||||
void DMA_Init(Section* sec) {
|
||||
Bitu i;
|
||||
for (i=0;i<0x10;i++) {
|
||||
IO_RegisterWriteHandler(i,write_dma,"DMA1");
|
||||
IO_RegisterReadHandler(i,read_dma,"DMA1");
|
||||
}
|
||||
IO_RegisterWriteHandler(0x81,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x82,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x83,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x87,write_dma_page,"DMA Pages");
|
||||
|
||||
IO_RegisterReadHandler(0x81,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x82,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x83,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x87,read_dma_page,"DMA Pages");
|
||||
void DMA_Init(Section* sec) {
|
||||
|
||||
Bitu i;
|
||||
|
||||
DmaControllers[0] = new DmaController(0);
|
||||
DmaControllers[1] = new DmaController(1);
|
||||
|
||||
for(i=0;i<4;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[0],false);
|
||||
}
|
||||
for(i=4;i<8;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[1],true);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue