Implemented 16-bit DMA support
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1398
This commit is contained in:
Dean Beeler
parent
9d8d93a7dd
commit
ed4d000c14
2 changed files with 513 additions and 251 deletions
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@ -20,11 +20,6 @@
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Based the port handling from the bochs dma code.
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*/
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/*
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TODO
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Implement 16-bit dma
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*/
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#include <string.h>
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#include "dosbox.h"
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#include "mem.h"
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@ -32,259 +27,193 @@
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#include "dma.h"
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#include "pic.h"
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#define DMA_MODE_DEMAND 0
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#define DMA_MODE_SINGLE 1
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#define DMA_MODE_BLOCK 2
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#define DMA_MODE_CASCADE 3
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struct DMA_CHANNEL {
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struct {
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Bit8u mode_type;
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bool address_decrement;
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bool autoinit_enable;
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Bit8u transfer_type;
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} mode;
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Bit16u base_address;
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Bit16u base_count;
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Bit16u current_address;
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Bitu current_count;
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Bit8u page;
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bool masked;
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PhysPt address;
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bool addr_changed;
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bool enabled;
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DMA_EnableCallBack enable_callback;
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};
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DmaChannel *DmaChannels[8];
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DmaController *DmaControllers[2];
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struct DMA_CONTROLLER {
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bool flipflop;
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Bit8u status_reg;
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Bit8u command_reg;
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DMA_CHANNEL chan[4];
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};
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Bit16u DmaController::portRead(Bit32u port, bool eightbit) {
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LOG_MSG("Reading DMA controller at %x", port);
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return 0xffff;
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}
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static DMA_CONTROLLER dma[2];
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void DMA_CheckEnabled(DMA_CHANNEL * chan);
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void DMA_SetEnabled(DMA_CHANNEL * chan,bool enabled);
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static Bit8u read_dma(Bit32u port) {
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/* only use first dma for now */
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DMA_CONTROLLER * cont=&dma[0];
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DMA_CHANNEL * chan=&cont->chan[port>>1];
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Bit8u ret;
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switch (port) {
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case 0x00:case 0x02:case 0x04:case 0x06:
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if (cont->flipflop) {
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ret=chan->current_address & 0xff;
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} else {
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ret=(chan->current_address>>8)&0xff;
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}
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cont->flipflop=!cont->flipflop;
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break;
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case 0x01:case 0x03:case 0x05:case 0x07:
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if (cont->flipflop) {
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ret=(Bit8u)((chan->current_count-1) & 0xff);
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} else {
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ret=(Bit8u)(((chan->current_count-1)>>8)&0xff);
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}
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cont->flipflop=!cont->flipflop;
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break;
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case 0x08: /* Read Status */
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ret=cont->status_reg;
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cont->status_reg&=~0xf; /* Clear lower 4 bits on read */
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break;
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case 0x0a:
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case 0x0e:
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/* Seem to return 0 on a real controller */
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ret=0x0;
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break;
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default:
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LOG(LOG_DMA,LOG_ERROR)("DMA:Unhandled read from %X",port);
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void DmaController::portWrite(Bit32u port, Bit16u val, bool eightbit) {
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bool found;
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found = false;
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if(port == ControllerPorts[ctrlnum][DMA_CLRMASKREG]) {
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found = true;
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flipflop = true;
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// Disable DMA requests
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// Clear command and status registers
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}
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// LOG_MSG("DMA Read port %x result %x",port,ret);
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return ret;
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}
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static void write_dma(Bit32u port,Bit8u val) {
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/* only use first dma for now */
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DMA_CONTROLLER * cont=&dma[0];
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DMA_CHANNEL * chan;
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switch (port) {
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case 0x00:case 0x02:case 0x04:case 0x06:
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chan=&cont->chan[port>>1];
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if (cont->flipflop) {
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chan->base_address=(chan->base_address & 0xff00) | val;
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} else {
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chan->base_address=(chan->base_address & 0x00ff) | (val<<8);
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}
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cont->flipflop=!cont->flipflop;
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chan->addr_changed=true;
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break;
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case 0x01:case 0x03:case 0x05:case 0x07:
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chan=&cont->chan[port>>1];
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if (cont->flipflop) {
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chan->base_count=(chan->base_count & 0xff00) | val;
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} else {
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chan->base_count=(chan->base_count & 0x00ff) | (val<<8);
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}
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cont->flipflop=!cont->flipflop;
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chan->addr_changed=true;
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DMA_CheckEnabled(chan);
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break;
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case 0x08: /* Command Register */
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if (val != 4) LOG(LOG_DMA,LOG_ERROR)("DMA1:Illegal command %2X",val);
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cont->command_reg=val;
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break;
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case 0x09: /* Request Register */
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if (val&4) {
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/* Set Request bit */
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Bitu channel = val & 0x03;
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cont->status_reg |= (1 << (channel+4));
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} else {
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Bitu channel = val & 0x03;
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cont->status_reg &= ~(1 << (channel+4));
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}
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break;
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case 0x0a: /* single mask bit register */
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chan=&cont->chan[val & 0x3];
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if ((val & 4)>0) {
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DMA_SetEnabled(chan,false);
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chan->masked=(val & 4)>0; //Set it later
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} else {
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chan->masked=(val & 4)>0;
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DMA_CheckEnabled(chan);
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}
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break;
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case 0x0b: /* mode register */
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chan=&cont->chan[val & 0x3];
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chan->mode.mode_type = (val >> 6) & 0x03;
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chan->mode.address_decrement = (val & 0x20) > 0;
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chan->mode.autoinit_enable = (val & 0x10) > 0;
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chan->mode.transfer_type = (val >> 2) & 0x03;
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if (chan->mode.address_decrement) {
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LOG(LOG_DMA,LOG_ERROR)("DMA:Address Decrease not supported yet");
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}
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DMA_CheckEnabled(chan);
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break;
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case 0x0c: /* Clear Flip/Flip */
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cont->flipflop=true;
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break;
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default:
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LOG(LOG_DMA,LOG_ERROR)("DMA:Unhandled write %X to %X",static_cast<Bit32u>(val),port);
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};
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};
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void write_dma_page(Bit32u port,Bit8u val) {
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Bitu channel;
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switch (port) {
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case 0x81: /* dma0 page register, channel 2 */
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channel=2;break;
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case 0x82: /* dma0 page register, channel 3 */
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channel=3;break;
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case 0x83: /* dma0 page register, channel 1 */
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channel=1;break;
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case 0x87: /* dma0 page register, channel 0 */
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channel=0;break;
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if(port == ControllerPorts[ctrlnum][DMA_SINGLEREG]) {
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found = true;
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int dmachan;
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dmachan = (ctrlnum * 2) + (val & 0x3);
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DmaChannels[dmachan]->masked = ((val & 0x4) == 0x4);
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DmaChannels[dmachan]->Notify();
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}
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dma[0].chan[channel].page=val;
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dma[0].chan[channel].addr_changed=true;
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}
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Bit8u read_dma_page(Bit32u port) {
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Bitu channel;
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switch (port) {
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case 0x81: /* dma0 page register, channel 2 */
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channel=2;break;
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case 0x82: /* dma0 page register, channel 3 */
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channel=3;break;
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case 0x83: /* dma0 page register, channel 1 */
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channel=1;break;
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case 0x87: /* dma0 page register, channel 0 */
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channel=0;break;
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if(port == ControllerPorts[ctrlnum][DMA_WRITEALLREG]) {
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found = true;
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int dmachan,i,r;
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dmachan = (ctrlnum * 2);
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r = 0;
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for(i=dmachan;i<dmachan+4;i++) {
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DmaChannels[i]->masked = (((val >> r) & 0x1) == 0x1);
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DmaChannels[i]->Notify();
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r++;
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}
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}
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return dma[0].chan[channel].page;
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if(port == ControllerPorts[ctrlnum][DMA_CLEARREG]) {
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found = true;
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flipflop = true;
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}
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if(port == ControllerPorts[ctrlnum][DMA_MODEREG]) {
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found = true;
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int dmachan;
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dmachan = (ctrlnum * 2) + (val & 0x3);
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DmaChannels[dmachan]->trantype = (val >> 2) & 0x3;
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DmaChannels[dmachan]->autoinit = ((val & 0x10) == 0x10);
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DmaChannels[dmachan]->dir = ((val & 0x20) == 0x20);
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DmaChannels[dmachan]->dmamode = (val >> 6) & 0x3;
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DMA_CheckEnabled(DmaChannels[dmachan]);
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}
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if(!found) LOG_MSG("Write to DMA port %x with %x", port, val);
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}
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INLINE void ResetDMA8(DMA_CHANNEL * chan) {
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chan->addr_changed=false;
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chan->address=(chan->page << 16)+chan->base_address;
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chan->current_count=chan->base_count+1;
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chan->current_address=chan->base_address;
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LOG(LOG_DMA,LOG_NORMAL)("Setup at address %X:%X count %X",chan->page<<12,chan->base_address,chan->current_count);
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static Bit16u readDMAPorts(Bit32u port, bool eightbit) {
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int i,j;
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// Check for controller access
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for(i=0;i<2;i++) {
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for(j=0;j<7;j++) {
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if(ControllerPorts[i][j] == port) {
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return DmaControllers[i]->portRead(port, eightbit);
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}
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}
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}
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// Check for DMA access
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for(i=0;i<8;i++) {
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for(j=0;j<3;j++) {
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if(ChannelPorts[j][i] == port) {
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return DmaChannels[i]->portRead(port, eightbit);
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}
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}
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}
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LOG_MSG("Unmatched read port %x", port);
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return 0xffff;
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}
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static void writeDMAPorts(Bit32u port, Bit16u val, bool eightbit) {
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int i,j;
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// Check for controller access
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for(i=0;i<2;i++) {
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for(j=0;j<7;j++) {
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if(ControllerPorts[i][j] == port) {
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DmaControllers[i]->portWrite(port,val,eightbit);
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return;
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}
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}
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}
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// Check for DMA access
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for(i=0;i<8;i++) {
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for(j=0;j<3;j++) {
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if(ChannelPorts[j][i] == port) {
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DmaChannels[i]->portWrite(port,val,eightbit);
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return;
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}
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}
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}
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LOG_MSG("Unmatched write port %x - val %x", port, val);
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}
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Bit8u read_dmaB(Bit32u port) { return (Bit8u)readDMAPorts(port,true); }
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Bit16u read_dmaW(Bit32u port) { return readDMAPorts(port,false); }
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void write_dmaB(Bit32u port,Bit8u val) { writeDMAPorts(port,val,true); }
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void write_dmaW(Bit32u port,Bit16u val) { writeDMAPorts(port,val,false); }
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// Deprecated DMA read/write routines -- Keep compatibility with Sound Blaster
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Bitu DMA_8_Read(Bitu dmachan,Bit8u * buffer,Bitu count) {
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DMA_CHANNEL * chan=&dma[0].chan[dmachan];
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DmaChannel *chan=DmaChannels[dmachan];
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if (chan->masked) return 0;
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if (!count) return 0;
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if (chan->addr_changed) ResetDMA8(chan);
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if (chan->current_count>count) {
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MEM_BlockRead(chan->address,buffer,count);
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chan->address+=count;
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chan->current_address+=count;
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chan->current_count-=count;
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if (chan->currcnt>count) {
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MEM_BlockRead(chan->curraddr,buffer,count);
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chan->curraddr+=count;
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chan->current_addr+=count;
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chan->currcnt-=count;
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return count;
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} else {
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/* Copy remaining piece of first buffer */
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MEM_BlockRead(chan->address,buffer,chan->current_count);
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if (!chan->mode.autoinit_enable) {
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/* Set the end of counter bit */
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dma[0].status_reg|=(1 << dmachan);
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count=chan->current_count;
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chan->address+=count;
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chan->current_count=0;
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// Copy remaining piece of first buffer
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MEM_BlockRead(chan->curraddr,buffer,chan->currcnt);
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if (!chan->autoinit) {
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// Set the end of counter bit
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//dma[0].status_reg|=(1 << dmachan);
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count=chan->currcnt;
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chan->curraddr+=count;
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chan->current_addr+=count;
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chan->currcnt=0;
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chan->enabled=false;
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LOG(LOG_DMA,LOG_NORMAL)("8-bit Channel %d reached terminal count");
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return count;
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} else {
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buffer+=chan->current_count;
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Bitu left=count-(Bit16u)chan->current_count;
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/* Autoinit reset the dma channel */
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ResetDMA8(chan);
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/* Copy the rest of the buffer */
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MEM_BlockRead(chan->address,buffer,left);
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chan->address+=left;
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chan->current_address+=left;
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chan->current_count-=left;
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buffer+=chan->currcnt;
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Bitu left=count-(Bit16u)chan->currcnt;
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// Autoinit reset the dma channel
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chan->reset();
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// Copy the rest of the buffer
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MEM_BlockRead(chan->curraddr,buffer,left);
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chan->curraddr+=left;
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chan->current_addr+=left;
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chan->currcnt-=left;
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return count;
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}
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}
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}
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Bitu DMA_8_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
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DMA_CHANNEL * chan=&dma[0].chan[dmachan];
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DmaChannel *chan=DmaChannels[dmachan];
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if (chan->masked) return 0;
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if (!count) return 0;
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if (chan->addr_changed) ResetDMA8(chan);
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if (chan->current_count>count) {
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MEM_BlockWrite(chan->address,buffer,count);
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chan->address+=count;
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chan->current_address+=count;
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chan->current_count-=count;
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if (chan->currcnt>count) {
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MEM_BlockWrite(chan->curraddr,buffer,count);
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chan->curraddr+=count;
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chan->currcnt-=count;
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return count;
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} else {
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/* Copy remaining piece of first buffer */
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MEM_BlockWrite(chan->address,buffer,chan->current_count);
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if (!chan->mode.autoinit_enable) {
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/* Set the end of counter bit */
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dma[0].status_reg|=(1 << dmachan);
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count=chan->current_count;
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chan->current_address+=count;;
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chan->current_count=0;
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chan->enabled=false;
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// Copy remaining piece of first buffer
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MEM_BlockWrite(chan->curraddr,buffer,chan->currcnt);
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if (!chan->autoinit) {
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// Set the end of counter bit
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//dma[0].status_reg|=(1 << dmachan);
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count=chan->currcnt;
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chan->curraddr+=count;;
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chan->currcnt=0;
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return count;
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} else {
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buffer+=chan->current_count;
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Bitu left=count-(Bit16u)chan->current_count;
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/* Autoinit reset the dma channel */
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ResetDMA8(chan);
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/* Copy the rest of the buffer */
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MEM_BlockWrite(chan->address,buffer,left);
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chan->address+=left;
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chan->current_address+=left;
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chan->current_count-=left;
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buffer+=chan->currcnt;
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Bitu left=count-(Bit16u)chan->currcnt;
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// Autoinit reset the dma channel
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chan->reset();
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// Copy the rest of the buffer
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MEM_BlockWrite(chan->curraddr,buffer,left);
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chan->curraddr+=left;
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chan->currcnt-=left;
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return count;
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}
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}
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@ -302,18 +231,21 @@ Bitu DMA_16_Write(Bitu dmachan,Bit8u * buffer,Bitu count) {
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return 0;
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}
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void DMA_SetEnabled(DMA_CHANNEL * chan,bool enabled) {
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void DMA_SetEnabled(DmaChannel * chan,bool enabled) {
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if (chan->enabled == enabled) return;
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chan->enabled=enabled;
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if (chan->enable_callback) (*chan->enable_callback)(enabled);
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}
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void DMA_CheckEnabled(DMA_CHANNEL * chan) {
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void DMA_CheckEnabled(void * usechan) {
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DmaChannel * chan;
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chan = (DmaChannel *)usechan;
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bool enabled;
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if (chan->masked) enabled=false;
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else {
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if (chan->mode.autoinit_enable) enabled=true;
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else if (chan->current_count || chan->addr_changed) enabled=true;
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if (chan->autoinit) enabled=true;
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else if (chan->currcnt) enabled=true;
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else enabled=false;
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}
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DMA_SetEnabled(chan,enabled);
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@ -321,31 +253,28 @@ void DMA_CheckEnabled(DMA_CHANNEL * chan) {
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void DMA_SetEnableCallBack(Bitu channel,DMA_EnableCallBack callback) {
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||||
DMA_CHANNEL * chan;
|
||||
if (channel<4) {
|
||||
chan=&dma[0].chan[channel];
|
||||
} else if (channel<8) {
|
||||
chan=&dma[1].chan[channel-4];
|
||||
} else return;
|
||||
DmaChannel * chan;
|
||||
chan = DmaChannels[channel];
|
||||
chan->enabled=false;
|
||||
chan->enable_callback=callback;
|
||||
DMA_CheckEnabled(chan);
|
||||
}
|
||||
|
||||
void DMA_Init(Section* sec) {
|
||||
Bitu i;
|
||||
for (i=0;i<0x10;i++) {
|
||||
IO_RegisterWriteHandler(i,write_dma,"DMA1");
|
||||
IO_RegisterReadHandler(i,read_dma,"DMA1");
|
||||
}
|
||||
IO_RegisterWriteHandler(0x81,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x82,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x83,write_dma_page,"DMA Pages");
|
||||
IO_RegisterWriteHandler(0x87,write_dma_page,"DMA Pages");
|
||||
|
||||
IO_RegisterReadHandler(0x81,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x82,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x83,read_dma_page,"DMA Pages");
|
||||
IO_RegisterReadHandler(0x87,read_dma_page,"DMA Pages");
|
||||
void DMA_Init(Section* sec) {
|
||||
|
||||
Bitu i;
|
||||
|
||||
DmaControllers[0] = new DmaController(0);
|
||||
DmaControllers[1] = new DmaController(1);
|
||||
|
||||
for(i=0;i<4;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[0],false);
|
||||
}
|
||||
for(i=4;i<8;i++) {
|
||||
DmaChannels[i] = new DmaChannel(i,DmaControllers[1],true);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue