raise privilege level for cpu-internal supervisor level memory accesses
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3051
This commit is contained in:
Sebastian Strohhäcker
parent
cb37216a20
commit
ee3ead7b27
3 changed files with 57 additions and 29 deletions
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@ -150,6 +150,7 @@ void CPU_SetFlags(Bitu word,Bitu mask);
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#define EXCEPTION_NP 11
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#define EXCEPTION_SS 12
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#define EXCEPTION_GP 13
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#define EXCEPTION_PF 14
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#define CR0_PROTECTION 0x00000001
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#define CR0_MONITORPROCESSOR 0x00000002
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@ -303,16 +304,9 @@ class Descriptor
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public:
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Descriptor() { saved.fill[0]=saved.fill[1]=0; }
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void Load(PhysPt address) {
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Bit32u* data = (Bit32u*)&saved;
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*data = mem_readd(address);
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*(data+1) = mem_readd(address+4);
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}
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void Save(PhysPt address) {
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Bit32u* data = (Bit32u*)&saved;
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mem_writed(address,*data);
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mem_writed(address+4,*(data+1));
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}
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void Load(PhysPt address);
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void Save(PhysPt address);
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PhysPt GetBase (void) {
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return (saved.seg.base_24_31<<24) | (saved.seg.base_16_23<<16) | saved.seg.base_0_15;
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}
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@ -433,6 +427,7 @@ public:
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struct CPUBlock {
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Bitu cpl; /* Current Privilege */
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Bitu mpl;
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Bitu cr0;
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bool pmode; /* Is Protected mode enabled */
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GDTDescriptorTable gdt;
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: cpu.cpp,v 1.103 2007-08-09 19:52:32 c2woody Exp $ */
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/* $Id: cpu.cpp,v 1.104 2007-11-26 00:00:58 c2woody Exp $ */
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#include <assert.h>
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#include <sstream>
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@ -110,6 +110,22 @@ void CPU_Core_Dynrec_Cache_Close(void);
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#endif
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void Descriptor::Load(PhysPt address) {
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cpu.mpl=0;
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Bit32u* data = (Bit32u*)&saved;
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*data = mem_readd(address);
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*(data+1) = mem_readd(address+4);
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cpu.mpl=3;
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}
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void Descriptor:: Save(PhysPt address) {
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cpu.mpl=0;
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Bit32u* data = (Bit32u*)&saved;
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mem_writed(address,*data);
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mem_writed(address+4,*(data+1));
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cpu.mpl=03;
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}
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void CPU_Push16(Bitu value) {
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Bit32u new_esp=(reg_esp&cpu.stack.notmask)|((reg_esp-2)&cpu.stack.mask);
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mem_writew(SegPhys(ss) + (new_esp & cpu.stack.mask) ,value);
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@ -210,12 +226,16 @@ public:
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return valid;
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}
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Bitu Get_back(void) {
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return mem_readw(base);
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cpu.mpl=0;
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Bit16u backlink=mem_readw(base);
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cpu.mpl=3;
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return backlink;
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}
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void SaveSelector(void) {
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cpu.gdt.SetDescriptor(selector,desc);
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}
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void Get_SSx_ESPx(Bitu level,Bitu & _ss,Bitu & _esp) {
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cpu.mpl=0;
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if (is386) {
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PhysPt where=base+offsetof(TSS_32,esp0)+level*8;
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_esp=mem_readd(where);
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@ -225,6 +245,7 @@ public:
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_esp=mem_readw(where);
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_ss=mem_readw(where+2);
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}
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cpu.mpl=3;
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}
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bool SetSelector(Bitu new_sel) {
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valid=false;
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@ -433,6 +454,7 @@ doconforming:
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bool CPU_IO_Exception(Bitu port,Bitu size) {
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if (cpu.pmode && ((GETFLAG_IOPL<cpu.cpl) || GETFLAG(VM))) {
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cpu.mpl=0;
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if (!cpu_tss.is386) goto doexception;
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PhysPt bwhere=cpu_tss.base+0x66;
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Bitu ofs=mem_readw(bwhere);
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@ -441,9 +463,11 @@ bool CPU_IO_Exception(Bitu port,Bitu size) {
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Bitu map=mem_readw(bwhere);
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Bitu mask=(0xffff>>(16-size)) << (port&7);
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if (map & mask) goto doexception;
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cpu.mpl=3;
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}
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return false;
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doexception:
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cpu.mpl=3;
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LOG(LOG_CPU,LOG_NORMAL)("IO Exception port %X",port);
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return CPU_PrepareException(EXCEPTION_GP,0);
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}
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@ -497,8 +521,8 @@ void CPU_Interrupt(Bitu num,Bitu type,Bitu oldeip) {
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return;
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}
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}
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Descriptor gate;
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Descriptor gate;
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if (!cpu.idt.GetDescriptor(num<<3,gate)) {
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// zone66
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CPU_Exception(EXCEPTION_GP,num*8+2+(type&CPU_INT_SOFTWARE)?0:1);
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@ -980,8 +1004,8 @@ void CPU_CALL(bool use32,Bitu selector,Bitu offset,Bitu oldeip) {
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CPU_CHECK_COND((selector & 0xfffc)==0,
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"CALL:CS selector zero",
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EXCEPTION_GP,0)
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Descriptor call;
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Bitu rpl=selector & 3;
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Descriptor call;
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CPU_CHECK_COND(!cpu.gdt.GetDescriptor(selector,call),
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"CALL:CS beyond limits",
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EXCEPTION_GP,selector & 0xfffc)
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@ -1089,6 +1113,7 @@ call_code:
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Bitu o_ss = SegValue(ss);
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PhysPt o_stack = SegPhys(ss)+(reg_esp & cpu.stack.mask);
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// catch pagefaults
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if (call.saved.gate.paramcount&31) {
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if (call.Type()==DESC_386_CALL_GATE) {
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: paging.cpp,v 1.29 2007-11-24 17:26:48 c2woody Exp $ */
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/* $Id: paging.cpp,v 1.30 2007-11-26 00:00:58 c2woody Exp $ */
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#include <stdlib.h>
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#include <assert.h>
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@ -102,6 +102,7 @@ struct PF_Entry {
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Bitu cs;
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Bitu eip;
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Bitu page_addr;
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Bitu mpl;
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};
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#define PF_QUEUESIZE 16
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@ -122,8 +123,10 @@ static Bits PageFaultCore(void) {
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PF_Entry * entry=&pf_queue.entries[pf_queue.used-1];
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X86PageEntry pentry;
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pentry.load=phys_readd(entry->page_addr);
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if (pentry.block.p && entry->cs == SegValue(cs) && entry->eip==reg_eip)
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if (pentry.block.p && entry->cs == SegValue(cs) && entry->eip==reg_eip) {
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cpu.cpl=entry->mpl;
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return -1;
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}
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return 0;
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}
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#if C_DEBUG
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@ -147,8 +150,9 @@ void PAGING_PageFault(PhysPt lin_addr,Bitu page_addr,Bitu faultcode) {
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entry->cs=SegValue(cs);
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entry->eip=reg_eip;
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entry->page_addr=page_addr;
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entry->mpl=cpu.mpl;
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//Caused by a write by default?
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CPU_Exception(14,faultcode);
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CPU_Exception(EXCEPTION_PF,faultcode);
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#if C_DEBUG
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// DEBUG_EnableDebugger();
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#endif
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@ -237,7 +241,8 @@ public:
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table.load=phys_readd(table_addr);
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if (!table.block.p) {
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LOG(LOG_PAGING,LOG_NORMAL)("NP Table");
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PAGING_PageFault(lin_addr,table_addr,(writing?0x02:0x00) | ((cpu.cpl==0)?0x00:0x04));
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PAGING_PageFault(lin_addr,table_addr,
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(writing?0x02:0x00) | (((cpu.cpl&cpu.mpl)==0)?0x00:0x04));
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table.load=phys_readd(table_addr);
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if (!table.block.p)
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E_Exit("Pagefault didn't correct table");
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@ -247,7 +252,8 @@ public:
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entry.load=phys_readd(entry_addr);
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if (!entry.block.p) {
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// LOG(LOG_PAGING,LOG_NORMAL)("NP Page");
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PAGING_PageFault(lin_addr,entry_addr,(writing?0x02:0x00) | ((cpu.cpl==0)?0x00:0x04));
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PAGING_PageFault(lin_addr,entry_addr,
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(writing?0x02:0x00) | (((cpu.cpl&cpu.mpl)==0)?0x00:0x04));
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entry.load=phys_readd(entry_addr);
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if (!entry.block.p)
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E_Exit("Pagefault didn't correct page");
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@ -259,15 +265,16 @@ public:
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Bitu priv_check=0;
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// if ((entry.block.us==0) || (table.block.us==0)) {
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if ((entry.block.us==0) && (table.block.us==0)) {
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if (cpu.cpl==3) priv_check=2;
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if ((cpu.cpl&cpu.mpl)==3) priv_check=2;
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else priv_check=1;
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}
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if ((entry.block.wr==0) || (table.block.wr==0)) {
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priv_check=1;
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if (writing && (cpu.cpl==3)) priv_check=2;
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if (writing && ((cpu.cpl&cpu.mpl)==3)) priv_check=2;
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}
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if (priv_check==2) {
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LOG(LOG_PAGING,LOG_NORMAL)("Page access denied: cpl=%i, %x:%x:%x:%x",cpu.cpl,entry.block.us,table.block.us,entry.block.wr,table.block.wr);
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LOG(LOG_PAGING,LOG_NORMAL)("Page access denied: cpl=%i, %x:%x:%x:%x",
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cpu.cpl,entry.block.us,table.block.us,entry.block.wr,table.block.wr);
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PAGING_PageFault(lin_addr,entry_addr,0x05 | (writing?0x02:0x00));
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}
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@ -307,8 +314,8 @@ public:
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table.load=phys_readd(table_addr);
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if (!table.block.p) {
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paging.cr2=lin_addr;
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cpu.exception.which=14;
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cpu.exception.error=(writing?0x02:0x00) | ((cpu.cpl==0)?0x00:0x04);
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cpu.exception.which=EXCEPTION_PF;
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cpu.exception.error=(writing?0x02:0x00) | (((cpu.cpl&cpu.mpl)==0)?0x00:0x04);
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return false;
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}
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X86PageEntry entry;
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@ -316,18 +323,19 @@ public:
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entry.load=phys_readd(entry_addr);
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if (!entry.block.p) {
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paging.cr2=lin_addr;
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cpu.exception.which=14;
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cpu.exception.error=(writing?0x02:0x00) | ((cpu.cpl==0)?0x00:0x04);
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cpu.exception.which=EXCEPTION_PF;
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cpu.exception.error=(writing?0x02:0x00) | (((cpu.cpl&cpu.mpl)==0)?0x00:0x04);
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return false;
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}
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if (cpu.cpl!=3) return true;
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if ((cpu.cpl&cpu.mpl)!=3) return true;
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// if (((entry.block.us==0) || (table.block.us==0)) || (((entry.block.wr==0) || (table.block.wr==0)) && writing)) {
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if (((entry.block.us==0) && (table.block.us==0)) || (((entry.block.wr==0) || (table.block.wr==0)) && writing)) {
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LOG(LOG_PAGING,LOG_NORMAL)("Page access denied: cpl=%i, %x:%x:%x:%x",cpu.cpl,entry.block.us,table.block.us,entry.block.wr,table.block.wr);
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LOG(LOG_PAGING,LOG_NORMAL)("Page access denied: cpl=%i, %x:%x:%x:%x",
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cpu.cpl,entry.block.us,table.block.us,entry.block.wr,table.block.wr);
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paging.cr2=lin_addr;
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cpu.exception.which=14;
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cpu.exception.which=EXCEPTION_PF;
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cpu.exception.error=0x05 | (writing?0x02:0x00);
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return false;
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}
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