add possibility to close dma controllers;
remove second dma controller when tandy sound is enabled and machine=vga Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2377
This commit is contained in:
Sebastian Strohhäcker
parent
07be3858f1
commit
f22e8d5041
6 changed files with 207 additions and 142 deletions
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: dma.h,v 1.14 2005-03-24 10:18:45 qbix79 Exp $ */
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/* $Id: dma.h,v 1.15 2005-11-16 20:27:39 c2woody Exp $ */
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#ifndef DOSBOX_DMA_H
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#define DOSBOX_DMA_H
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@ -31,19 +31,6 @@ enum DMAEvent {
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class DmaChannel;
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typedef void (* DMA_CallBack)(DmaChannel * chan,DMAEvent event);
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class DmaController {
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public:
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bool flipflop;
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Bit8u ctrlnum;
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Bit8u chanbase;
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public:
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DmaController(Bit8u num) {
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flipflop = false;
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ctrlnum = num;
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chanbase = num * 4;
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}
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};
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class DmaChannel {
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public:
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Bit32u pagebase;
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@ -85,7 +72,37 @@ public:
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Bitu Write(Bitu size, Bit8u * buffer);
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};
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extern DmaChannel *DmaChannels[8];
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extern DmaController *DmaControllers[2];
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class DmaController {
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private:
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Bit8u ctrlnum;
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bool flipflop;
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DmaChannel *DmaChannels[4];
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public:
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IO_ReadHandleObject DMA_ReadHandler[0x11];
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IO_WriteHandleObject DMA_WriteHandler[0x11];
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DmaController(Bit8u num) {
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flipflop = false;
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ctrlnum = num; /* first or second DMA controller */
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for(Bit8u i=0;i<4;i++) {
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DmaChannels[i] = new DmaChannel(i+ctrlnum*4,ctrlnum==1);
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}
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}
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~DmaController(void) {
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for(Bit8u i=0;i<4;i++) {
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delete DmaChannels[i];
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}
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}
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DmaChannel * GetChannel(Bit8u chan) {
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if (chan<4) return DmaChannels[chan];
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else return NULL;
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}
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void WriteControllerReg(Bitu reg,Bitu val,Bitu len);
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Bitu ReadControllerReg(Bitu reg,Bitu len);
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};
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DmaChannel * GetDMAChannel(Bit8u chan);
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void CloseSecondDMAController(void);
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bool SecondDMAControllerAvailable(void);
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#endif
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: dosbox.cpp,v 1.89 2005-11-10 18:05:10 c2woody Exp $ */
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/* $Id: dosbox.cpp,v 1.90 2005-11-16 20:27:39 c2woody Exp $ */
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#include <stdlib.h>
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#include <stdarg.h>
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@ -341,7 +341,7 @@ void DOSBOX_Init(void) {
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MSG_Add("SPEAKER_CONFIGFILE_HELP",
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"pcspeaker -- Enable PC-Speaker emulation.\n"
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"pcrate -- Sample rate of the PC-Speaker sound generation.\n"
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"tandy -- Enable Tandy Sound System emulation (false,true,auto).\n"
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"tandy -- Enable Tandy Sound System emulation (off,on,auto).\n"
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" For auto Tandysound emulation is present only if machine is set to tandy.\n"
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"tandyrate -- Sample rate of the Tandy 3-Voice generation.\n"
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"disney -- Enable Disney Sound Source emulation.\n"
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@ -25,37 +25,100 @@
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#include "paging.h"
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#include "setup.h"
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DmaChannel *DmaChannels[8];
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DmaController *DmaControllers[2];
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/* read a block from physical memory */
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static void DMA_BlockRead(PhysPt pt,void * data,Bitu size) {
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Bit8u * write=(Bit8u *) data;
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for ( ; size ; size--, pt++) {
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Bitu page = pt >> 12;
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if (page < LINK_START)
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if (page < LINK_START) /* cares for EMS pageframe etc. */
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page = paging.firstmb[page];
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*write++=phys_readb(page*4096 + (pt & 4095));
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}
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}
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/* write a block into physical memory */
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static void DMA_BlockWrite(PhysPt pt,void * data,Bitu size) {
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Bit8u * read=(Bit8u *) data;
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for ( ; size ; size--, pt++) {
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Bitu page = pt >> 12;
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if (page < LINK_START)
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if (page < LINK_START) /* cares for EMS pageframe etc. */
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page = paging.firstmb[page];
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phys_writeb(page*4096 + (pt & 4095), *read++);
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}
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}
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static void DMA_WriteControllerReg(DmaController * cont,Bitu reg,Bitu val,Bitu len) {
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DmaChannel * GetDMAChannel(Bit8u chan) {
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if (chan<4) {
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/* channel on first DMA controller */
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if (DmaControllers[0]) return DmaControllers[0]->GetChannel(chan);
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} else if (chan<8) {
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/* channel on second DMA controller */
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if (DmaControllers[1]) return DmaControllers[1]->GetChannel(chan-4);
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}
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return NULL;
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}
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/* remove the second DMA controller (ports are removed automatically) */
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void CloseSecondDMAController(void) {
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if (DmaControllers[1]) {
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delete DmaControllers[1];
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DmaControllers[1]=NULL;
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}
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}
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/* check availability of second DMA controller, needed for SB16 */
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bool SecondDMAControllerAvailable(void) {
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if (DmaControllers[1]) return true;
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else return false;
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}
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static void DMA_Write_Port(Bitu port,Bitu val,Bitu iolen) {
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if (port<0x10) {
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/* write to the first DMA controller (channels 0-3) */
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DmaControllers[0]->WriteControllerReg(port,val,1);
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} else if (port>=0xc0 && port <=0xdf) {
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/* write to the second DMA controller (channels 4-7) */
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DmaControllers[1]->WriteControllerReg((port-0xc0) >> 1,val,1);
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} else switch (port) {
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/* write DMA page register */
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case 0x81:GetDMAChannel(2)->SetPage(val);break;
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case 0x82:GetDMAChannel(3)->SetPage(val);break;
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case 0x83:GetDMAChannel(1)->SetPage(val);break;
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case 0x89:GetDMAChannel(6)->SetPage(val);break;
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case 0x8a:GetDMAChannel(7)->SetPage(val);break;
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case 0x8b:GetDMAChannel(5)->SetPage(val);break;
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}
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}
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static Bitu DMA_Read_Port(Bitu port,Bitu iolen) {
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if (port<0x10) {
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/* read from the first DMA controller (channels 0-3) */
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return DmaControllers[0]->ReadControllerReg(port,iolen);
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} else if (port>=0xc0 && port <=0xdf) {
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/* read from the second DMA controller (channels 4-7) */
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return DmaControllers[1]->ReadControllerReg((port-0xc0) >> 1,iolen);
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} else switch (port) {
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/* read DMA page register */
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case 0x81:return GetDMAChannel(2)->pagenum;
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case 0x82:return GetDMAChannel(3)->pagenum;
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case 0x83:return GetDMAChannel(1)->pagenum;
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case 0x89:return GetDMAChannel(6)->pagenum;
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case 0x8a:return GetDMAChannel(7)->pagenum;
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case 0x8b:return GetDMAChannel(5)->pagenum;
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}
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return 0;
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}
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void DmaController::WriteControllerReg(Bitu reg,Bitu val,Bitu len) {
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DmaChannel * chan;Bitu i;
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Bitu base=cont->chanbase;
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switch (reg) {
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/* set base address of DMA transfer (1st byte low part, 2nd byte high part) */
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan=GetChannel(reg >> 1);
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flipflop=!flipflop;
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if (flipflop) {
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chan->baseaddr=(chan->baseaddr&0xff00)|val;
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chan->curraddr=(chan->curraddr&0xff00)|val;
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} else {
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@ -63,10 +126,11 @@ static void DMA_WriteControllerReg(DmaController * cont,Bitu reg,Bitu val,Bitu l
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chan->curraddr=(chan->curraddr&0x00ff)|(val << 8);
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}
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break;
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/* set DMA transfer count (1st byte low part, 2nd byte high part) */
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan=GetChannel(reg >> 1);
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flipflop=!flipflop;
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if (flipflop) {
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chan->basecnt=(chan->basecnt&0xff00)|val;
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chan->currcnt=(chan->currcnt&0xff00)|val;
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} else {
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@ -80,63 +144,67 @@ static void DMA_WriteControllerReg(DmaController * cont,Bitu reg,Bitu val,Bitu l
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//TODO Warning?
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break;
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case 0xa: /* Mask Register */
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chan=DmaChannels[base+(val & 3 )];
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chan=GetChannel(val & 3);
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chan->SetMask((val & 0x4)>0);
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break;
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case 0xb: /* Mode Register */
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chan=DmaChannels[base+(val & 3 )];
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chan=GetChannel(val & 3);
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chan->autoinit=(val & 0x10) > 0;
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chan->increment=(val & 0x20) > 0;
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//TODO Maybe other bits?
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break;
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case 0xc: /* Clear Flip/Flip */
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cont->flipflop=false;
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flipflop=false;
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break;
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case 0xd: /* Master Clear/Reset */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(true);
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DmaChannels[base+i]->tcount=false;
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chan=GetChannel(i);
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chan->SetMask(true);
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chan->tcount=false;
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}
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cont->flipflop=false;
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flipflop=false;
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break;
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case 0xe: /* Clear Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(false);
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chan=GetChannel(i);
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chan->SetMask(false);
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}
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break;
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case 0xf: /* Multiple Mask register */
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for (i=0;i<4;i++) {
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DmaChannels[base+i]->SetMask(val & 1);
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chan=GetChannel(i);
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chan->SetMask(val & 1);
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val>>=1;
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}
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break;
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}
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}
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static Bitu DMA_ReadControllerReg(DmaController * cont,Bitu reg,Bitu len) {
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Bitu DmaController::ReadControllerReg(Bitu reg,Bitu len) {
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DmaChannel * chan;Bitu i,ret;
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Bitu base=cont->chanbase;
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switch (reg) {
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/* read base address of DMA transfer (1st byte low part, 2nd byte high part) */
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case 0x0:case 0x2:case 0x4:case 0x6:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan=GetChannel(reg >> 1);
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flipflop=!flipflop;
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if (flipflop) {
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return chan->curraddr & 0xff;
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} else {
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return (chan->curraddr >> 8) & 0xff;
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}
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/* read DMA transfer count (1st byte low part, 2nd byte high part) */
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case 0x1:case 0x3:case 0x5:case 0x7:
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chan=DmaChannels[base+(reg >> 1)];
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cont->flipflop=!cont->flipflop;
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if (cont->flipflop) {
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chan=GetChannel(reg >> 1);
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flipflop=!flipflop;
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if (flipflop) {
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return chan->currcnt & 0xff;
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} else {
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return (chan->currcnt >> 8) & 0xff;
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}
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case 0x8:
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case 0x8: /* Status Register */
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ret=0;
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for (i=0;i<4;i++) {
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chan=DmaChannels[base+i];
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chan=GetChannel(i);
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if (chan->tcount) ret|=1 << i;
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chan->tcount=false;
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if (chan->callback) ret|=1 << (i+4);
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@ -149,53 +217,21 @@ static Bitu DMA_ReadControllerReg(DmaController * cont,Bitu reg,Bitu len) {
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return 0xffffffff;
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}
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static void DMA_Write_Port(Bitu port,Bitu val,Bitu iolen) {
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if (port<0x10) {
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DMA_WriteControllerReg(DmaControllers[0],port,val,1);
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} else if (port>=0xc0 && port <=0xdf) {
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DMA_WriteControllerReg(DmaControllers[1],(port-0xc0) >> 1,val,1);
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} else switch (port) {
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case 0x81:DmaChannels[2]->SetPage(val);break;
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case 0x82:DmaChannels[3]->SetPage(val);break;
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case 0x83:DmaChannels[1]->SetPage(val);break;
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case 0x89:DmaChannels[6]->SetPage(val);break;
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case 0x8a:DmaChannels[7]->SetPage(val);break;
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case 0x8b:DmaChannels[5]->SetPage(val);break;
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}
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}
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static Bitu DMA_Read_Port(Bitu port,Bitu iolen) {
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if (port<0x10) {
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return DMA_ReadControllerReg(DmaControllers[0],port,iolen);
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} else if (port>=0xc0 && port <=0xdf) {
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return DMA_ReadControllerReg(DmaControllers[1],(port-0xc0) >> 1,iolen);
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} else switch (port) {
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case 0x81:return DmaChannels[2]->pagenum;
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case 0x82:return DmaChannels[3]->pagenum;
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case 0x83:return DmaChannels[1]->pagenum;
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case 0x89:return DmaChannels[6]->pagenum;
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case 0x8a:return DmaChannels[7]->pagenum;
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case 0x8b:return DmaChannels[5]->pagenum;
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}
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return 0;
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}
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DmaChannel::DmaChannel(Bit8u num, bool dma16) {
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masked = true;
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callback = NULL;
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if(num == 4) return;
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channum = num;
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DMA16 = dma16 ? 0x1 : 0x0;
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pagenum = 0;
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pagebase = 0;
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baseaddr = 0;
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curraddr = 0;
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basecnt = 0;
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currcnt = 0;
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increment = true;
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autoinit = false;
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tcount = false;
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masked = true;
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callback = NULL;
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if(num == 4) return;
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channum = num;
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DMA16 = dma16 ? 0x1 : 0x0;
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pagenum = 0;
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pagebase = 0;
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baseaddr = 0;
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curraddr = 0;
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basecnt = 0;
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currcnt = 0;
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increment = true;
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autoinit = false;
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tcount = false;
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}
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Bitu DmaChannel::Read(Bitu want, Bit8u * buffer) {
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@ -226,6 +262,7 @@ again:
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}
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return done;
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}
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Bitu DmaChannel::Write(Bitu want, Bit8u * buffer) {
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Bitu done=0;
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again:
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@ -256,40 +293,42 @@ again:
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}
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class DMA:public Module_base{
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private:
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IO_ReadHandleObject ReadHandler[0x22];
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IO_WriteHandleObject WriteHandler[0x22];
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public:
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DMA(Section* configuration):Module_base(configuration){
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Bitu i;
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DmaControllers[0] = new DmaController(0);
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DmaControllers[1] = new DmaController(1);
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if (machine==MCH_VGA) DmaControllers[1] = new DmaController(1);
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for(i=0;i<8;i++) {
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DmaChannels[i] = new DmaChannel(i,i>=4);
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}
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for (i=0;i<0x10;i++) {
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Bitu mask=IO_MB;
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if (i<8) mask|=IO_MW;
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WriteHandler[i].Install(i,DMA_Write_Port,mask);
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ReadHandler[i].Install(i,DMA_Read_Port,mask);
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/* install handler for first DMA controller ports */
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DmaControllers[0]->DMA_WriteHandler[i].Install(i,DMA_Write_Port,mask);
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DmaControllers[0]->DMA_ReadHandler[i].Install(i,DMA_Read_Port,mask);
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if (machine==MCH_VGA) {
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WriteHandler[0x10+i].Install(0xc0+i*2,DMA_Write_Port,mask);
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ReadHandler[0x10+i].Install(0xc0+i*2,DMA_Read_Port,mask);
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/* install handler for second DMA controller ports */
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DmaControllers[1]->DMA_WriteHandler[i].Install(0xc0+i*2,DMA_Write_Port,mask);
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DmaControllers[1]->DMA_ReadHandler[i].Install(0xc0+i*2,DMA_Read_Port,mask);
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}
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}
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WriteHandler[0x20].Install(0x81,DMA_Write_Port,IO_MB,3);
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WriteHandler[0x21].Install(0x89,DMA_Write_Port,IO_MB,3);
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ReadHandler[0x20].Install(0x81,DMA_Read_Port,IO_MB,3);
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ReadHandler[0x21].Install(0x89,DMA_Read_Port,IO_MB,3);
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/* install handlers for ports 0x81-0x83 (on the first DMA controller) */
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DmaControllers[0]->DMA_WriteHandler[0x10].Install(0x81,DMA_Write_Port,IO_MB,3);
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DmaControllers[0]->DMA_ReadHandler[0x10].Install(0x81,DMA_Read_Port,IO_MB,3);
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if (machine==MCH_VGA) {
|
||||
/* install handlers for ports 0x81-0x83 (on the second DMA controller) */
|
||||
DmaControllers[1]->DMA_WriteHandler[0x10].Install(0x89,DMA_Write_Port,IO_MB,3);
|
||||
DmaControllers[1]->DMA_ReadHandler[0x10].Install(0x89,DMA_Read_Port,IO_MB,3);
|
||||
}
|
||||
}
|
||||
~DMA(){
|
||||
delete DmaControllers[0];
|
||||
delete DmaControllers[1];
|
||||
for(Bitu i=0;i<8;i++) {
|
||||
delete DmaChannels[i];
|
||||
if (DmaControllers[0]) {
|
||||
delete DmaControllers[0];
|
||||
DmaControllers[0]=NULL;
|
||||
}
|
||||
if (DmaControllers[1]) {
|
||||
delete DmaControllers[1];
|
||||
DmaControllers[1]=NULL;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -83,8 +83,8 @@ struct GFGus {
|
|||
} timers[2];
|
||||
Bit32u rate;
|
||||
Bit16u portbase;
|
||||
Bit16u dma1;
|
||||
Bit16u dma2;
|
||||
Bit8u dma1;
|
||||
Bit8u dma2;
|
||||
|
||||
Bit16u irq1;
|
||||
Bit16u irq2;
|
||||
|
|
@ -568,7 +568,7 @@ static void ExecuteGlobRegister(void) {
|
|||
break;
|
||||
case 0x41: // Dma control register
|
||||
myGUS.DMAControl = (Bit8u)(myGUS.gRegData>>8);
|
||||
DmaChannels[myGUS.dma1]->Register_Callback(
|
||||
GetDMAChannel(myGUS.dma1)->Register_Callback(
|
||||
(myGUS.DMAControl & 0x1) ? GUS_DMA_Callback : 0);
|
||||
break;
|
||||
case 0x42: // Gravis DRAM DMA address register
|
||||
|
|
@ -597,7 +597,7 @@ static void ExecuteGlobRegister(void) {
|
|||
break;
|
||||
case 0x49: // DMA sampling control register
|
||||
myGUS.SampControl = (Bit8u)(myGUS.gRegData>>8);
|
||||
DmaChannels[myGUS.dma1]->Register_Callback(
|
||||
GetDMAChannel(myGUS.dma1)->Register_Callback(
|
||||
(myGUS.SampControl & 0x1) ? GUS_DMA_Callback : 0);
|
||||
break;
|
||||
case 0x4c: // GUS reset register
|
||||
|
|
|
|||
|
|
@ -518,7 +518,7 @@ static void DSP_RaiseIRQEvent(Bitu val) {
|
|||
SB_RaiseIRQ(SB_IRQ_8);
|
||||
}
|
||||
|
||||
static void DSP_DoDMATranfser(DMA_MODES mode,Bitu freq,bool stereo) {
|
||||
static void DSP_DoDMATransfer(DMA_MODES mode,Bitu freq,bool stereo) {
|
||||
char * type;
|
||||
sb.mode=MODE_DMA_MASKED;
|
||||
sb.chan->FillUp();
|
||||
|
|
@ -576,8 +576,8 @@ static void DSP_DoDMATranfser(DMA_MODES mode,Bitu freq,bool stereo) {
|
|||
static void DSP_PrepareDMA_Old(DMA_MODES mode,bool autoinit) {
|
||||
sb.dma.autoinit=autoinit;
|
||||
if (!autoinit) sb.dma.total=1+sb.dsp.in.data[0]+(sb.dsp.in.data[1] << 8);
|
||||
sb.dma.chan=DmaChannels[sb.hw.dma8];
|
||||
DSP_DoDMATranfser(mode,sb.freq / (sb.mixer.stereo ? 2 : 1),sb.mixer.stereo);
|
||||
sb.dma.chan=GetDMAChannel(sb.hw.dma8);
|
||||
DSP_DoDMATransfer(mode,sb.freq / (sb.mixer.stereo ? 2 : 1),sb.mixer.stereo);
|
||||
}
|
||||
|
||||
static void DSP_PrepareDMA_New(DMA_MODES mode,Bitu length,bool autoinit,bool stereo) {
|
||||
|
|
@ -585,14 +585,14 @@ static void DSP_PrepareDMA_New(DMA_MODES mode,Bitu length,bool autoinit,bool ste
|
|||
sb.dma.total=length;
|
||||
sb.dma.autoinit=autoinit;
|
||||
if (mode==DSP_DMA_16) {
|
||||
if (sb.hw.dma16!=0xff) sb.dma.chan=DmaChannels[sb.hw.dma16];
|
||||
if (sb.hw.dma16!=0xff) sb.dma.chan=GetDMAChannel(sb.hw.dma16);
|
||||
else {
|
||||
sb.dma.chan=DmaChannels[sb.hw.dma8];
|
||||
sb.dma.chan=GetDMAChannel(sb.hw.dma8);
|
||||
mode=DSP_DMA_16_ALIASED;
|
||||
freq/=2;
|
||||
}
|
||||
} else sb.dma.chan=DmaChannels[sb.hw.dma8];
|
||||
DSP_DoDMATranfser(mode,freq,stereo);
|
||||
} else sb.dma.chan=GetDMAChannel(sb.hw.dma8);
|
||||
DSP_DoDMATransfer(mode,freq,stereo);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -650,19 +650,21 @@ static void DSP_DoReset(Bit8u val) {
|
|||
static void DSP_E2_DMA_CallBack(DmaChannel * chan, DMAEvent event) {
|
||||
if (event==DMA_UNMASKED) {
|
||||
Bit8u val=sb.e2.value;
|
||||
DmaChannels[sb.hw.dma8]->Register_Callback(0);
|
||||
DmaChannels[sb.hw.dma8]->Write(1,&val);
|
||||
DmaChannel * chan=GetDMAChannel(sb.hw.dma8);
|
||||
chan->Register_Callback(0);
|
||||
chan->Write(1,&val);
|
||||
}
|
||||
}
|
||||
|
||||
static void DSP_ADC_CallBack(DmaChannel * chan, DMAEvent event) {
|
||||
if (event!=DMA_UNMASKED) return;
|
||||
Bit8u val=128;
|
||||
DmaChannel * ch=GetDMAChannel(sb.hw.dma8);
|
||||
while (sb.dma.left--) {
|
||||
DmaChannels[sb.hw.dma8]->Write(1,&val);
|
||||
ch->Write(1,&val);
|
||||
}
|
||||
SB_RaiseIRQ(SB_IRQ_8);
|
||||
DmaChannels[sb.hw.dma8]->Register_Callback(0);
|
||||
ch->Register_Callback(0);
|
||||
}
|
||||
|
||||
Bitu DEBUG_EnableDebugger(void);
|
||||
|
|
@ -684,7 +686,7 @@ static void DSP_DoCommand(void) {
|
|||
case 0x24: /* Singe Cycle 8-Bit DMA ADC */
|
||||
sb.dma.left=sb.dma.total=1+sb.dsp.in.data[0]+(sb.dsp.in.data[1] << 8);
|
||||
LOG(LOG_SB,LOG_ERROR)("DSP:Faked ADC for %d bytes",sb.dma.total);
|
||||
DmaChannels[sb.hw.dma8]->Register_Callback(DSP_ADC_CallBack);
|
||||
GetDMAChannel(sb.hw.dma8)->Register_Callback(DSP_ADC_CallBack);
|
||||
break;
|
||||
case 0x14: /* Singe Cycle 8-Bit DMA DAC */
|
||||
case 0x91: /* Singe Cycle 8-Bit DMA High speed DAC */
|
||||
|
|
@ -794,7 +796,7 @@ static void DSP_DoCommand(void) {
|
|||
if ((sb.dsp.in.data[0] >> i) & 0x01) sb.e2.value += E2_incr_table[sb.e2.count % 4][i];
|
||||
sb.e2.value += E2_incr_table[sb.e2.count % 4][8];
|
||||
sb.e2.count++;
|
||||
DmaChannels[sb.hw.dma8]->Register_Callback(DSP_E2_DMA_CallBack);
|
||||
GetDMAChannel(sb.hw.dma8)->Register_Callback(DSP_E2_DMA_CallBack);
|
||||
}
|
||||
break;
|
||||
case 0xe3: /* DSP Copyright */
|
||||
|
|
@ -1105,12 +1107,14 @@ private:
|
|||
else if (!strcasecmp(sbtype,"sb16")) type=SBT_16;
|
||||
else if (!strcasecmp(sbtype,"none")) type=SBT_NONE;
|
||||
else type=SBT_16;
|
||||
|
||||
if (machine!=MCH_VGA && type==SBT_16) type=SBT_PRO2;
|
||||
|
||||
|
||||
if (type==SBT_16) {
|
||||
if ((machine!=MCH_VGA) || !SecondDMAControllerAvailable()) type=SBT_PRO2;
|
||||
}
|
||||
|
||||
/* OPL/CMS Init */
|
||||
const char * omode=config->Get_string("oplmode");
|
||||
if (!strcasecmp(omode,"none")) opl_mode=OPL_none;
|
||||
if (!strcasecmp(omode,"none")) opl_mode=OPL_none;
|
||||
else if (!strcasecmp(omode,"cms")) opl_mode=OPL_cms;
|
||||
else if (!strcasecmp(omode,"opl2")) opl_mode=OPL_opl2;
|
||||
else if (!strcasecmp(omode,"dualopl2")) opl_mode=OPL_dualopl2;
|
||||
|
|
@ -1186,7 +1190,6 @@ public:
|
|||
}
|
||||
|
||||
~SBLASTER() {
|
||||
Bitu i;
|
||||
Section_prop * section=static_cast<Section_prop *>(m_configuration);
|
||||
OPL_Mode opl_mode;
|
||||
Find_Type_And_Opl(section,sb.type,opl_mode);
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include "mem.h"
|
||||
#include "setup.h"
|
||||
#include "pic.h"
|
||||
#include "dma.h"
|
||||
|
||||
#define DAC_CLOCK 3570000
|
||||
#define MAX_OUTPUT 0x7fff
|
||||
|
|
@ -308,7 +309,7 @@ static void SN76496_set_gain(int gain)
|
|||
|
||||
class TANDYSOUND: public Module_base {
|
||||
private:
|
||||
IO_WriteHandleObject WriteHandler[2];
|
||||
IO_WriteHandleObject WriteHandler[3];
|
||||
MixerObject MixerChan;
|
||||
public:
|
||||
TANDYSOUND(Section* configuration):Module_base(configuration){
|
||||
|
|
@ -318,16 +319,21 @@ public:
|
|||
if (machine==MCH_TANDY) {
|
||||
/* enable tandy sound if tandy=true/auto */
|
||||
if ((strcmp(section->Get_string("tandy"),"true")!=0) &&
|
||||
(strcmp(section->Get_string("tandy"),"on")!=0) &&
|
||||
(strcmp(section->Get_string("tandy"),"auto")!=0)) return;
|
||||
} else {
|
||||
/* only enable tandy sound if tandy=true */
|
||||
if (strcmp(section->Get_string("tandy"),"true")!=0) return;
|
||||
if ((strcmp(section->Get_string("tandy"),"true")!=0) &&
|
||||
(strcmp(section->Get_string("tandy"),"on")!=0)) return;
|
||||
|
||||
/* ports from second DMA controller conflict with tandy ports */
|
||||
CloseSecondDMAController();
|
||||
|
||||
WriteHandler[2].Install(0x1e0,SN76496Write,IO_MB,2);
|
||||
}
|
||||
|
||||
if (machine==MCH_TANDY) {
|
||||
WriteHandler[0].Install(0xc0,SN76496Write,IO_MB,2);
|
||||
WriteHandler[1].Install(0xc4,TandyDACWrite,IO_MB,4);
|
||||
} else WriteHandler[0].Install(0x1e0,SN76496Write,IO_MB,2);
|
||||
WriteHandler[0].Install(0xc0,SN76496Write,IO_MB,2);
|
||||
WriteHandler[1].Install(0xc4,TandyDACWrite,IO_MB,4);
|
||||
|
||||
|
||||
Bit32u sample_rate = section->Get_int("tandyrate");
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue