Add new cpu core simple
Changes for new memory handling Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@1919
This commit is contained in:
Sjoerd van der Berg
parent
dc0be65224
commit
fc8d4d89c2
10 changed files with 420 additions and 393 deletions
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@ -31,43 +31,23 @@
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#include "debug.h"
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#endif
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#define SegBase(c) SegPhys(c)
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#if (!C_CORE_INLINE)
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#define LoadMb(off) mem_readb(off)
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#define LoadMw(off) mem_readw(off)
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#define LoadMd(off) mem_readd(off)
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#define SaveMb(off,val) mem_writeb(off,val)
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#define SaveMw(off,val) mem_writew(off,val)
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#define SaveMd(off,val) mem_writed(off,val)
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#else
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#include "paging.h"
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#define LoadMb(off) mem_readb_inline(off)
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#define LoadMw(off) mem_readw_inline(off)
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#define LoadMd(off) mem_readd_inline(off)
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#define SaveMb(off,val) mem_writeb_inline(off,val)
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#define SaveMw(off,val) mem_writew_inline(off,val)
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#define SaveMd(off,val) mem_writed_inline(off,val)
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#endif
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#define LoadMbs(off) (Bit8s)(LoadMb(off))
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#define LoadMws(off) (Bit16s)(LoadMw(off))
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#define LoadMds(off) (Bit32s)(LoadMd(off))
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#define LoadRb(reg) reg
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#define LoadRw(reg) reg
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#define LoadRd(reg) reg
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#define SaveRb(reg,val) reg=val
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#define SaveRw(reg,val) reg=val
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#define SaveRd(reg,val) reg=val
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extern Bitu cycle_count;
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#if C_FPU
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@ -82,81 +62,88 @@ extern Bitu cycle_count;
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#define OPCODE_SIZE 0x200
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#define PREFIX_ADDR 0x1
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#define PREFIX_SEG 0x2
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#define PREFIX_SEG_ADDR (PREFIX_ADDR|PREFIX_SEG)
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#define PREFIX_REP 0x4
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#define PREFIX_REP 0x2
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#define TEST_PREFIX_SEG (core.prefixes & PREFIX_SEG)
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#define TEST_PREFIX_ADDR (core.prefixes & PREFIX_ADDR)
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#define TEST_PREFIX_REP (core.prefixes & PREFIX_REP)
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#define DO_PREFIX_SEG(_SEG) \
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core.prefixes|=PREFIX_SEG; \
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core.seg_prefix_base=SegBase(_SEG); \
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goto restart_prefix;
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BaseDS=SegBase(_SEG); \
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BaseSS=SegBase(_SEG); \
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goto restart_opcode;
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#define DO_PREFIX_ADDR() \
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core.prefixes=(core.prefixes & ~PREFIX_ADDR) | \
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(cpu.code.big ^ PREFIX_ADDR); \
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goto restart_prefix;
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core.ea_table=&EATable[(core.prefixes&1) * 256]; \
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goto restart_opcode;
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#define DO_PREFIX_REP(_ZERO) \
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core.prefixes|=PREFIX_REP; \
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core.rep_zero=_ZERO; \
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goto restart_prefix;
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goto restart_opcode;
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typedef PhysPt (*GetEATable[256])(void);
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typedef PhysPt (*GetEAHandler)(void);
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static const Bit32u AddrMaskTable[2]={0x0000ffff,0xffffffff};
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static struct {
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Bitu opcode_index;
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PhysPt cseip;
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PhysPt seg_prefix_base;
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PhysPt base_ds,base_ss;
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bool rep_zero;
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Bitu prefixes;
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GetEATable * ea_table;
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GetEAHandler * ea_table;
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struct {
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bool skip;
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} trap;
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} core;
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#define GETIP (core.cseip-SegBase(cs))
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#define SAVEIP reg_eip=GETIP;
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#define LOADIP core.cseip=(SegBase(cs)+reg_eip);
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#define SegBase(c) SegPhys(c)
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#define BaseDS core.base_ds
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#define BaseSS core.base_ss
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static INLINE Bit8u Fetchb() {
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Bit8u temp=LoadMb(core.cseip);
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core.cseip+=1;
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return temp;
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}
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static INLINE Bit16u Fetchw() {
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Bit16u temp=LoadMw(core.cseip);
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core.cseip+=2;
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return temp;
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}
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static INLINE Bit32u Fetchd() {
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Bit32u temp=LoadMd(core.cseip);
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core.cseip+=4;
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return temp;
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}
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#define Push_16 CPU_Push16
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#define Push_32 CPU_Push32
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#define Pop_16 CPU_Pop16
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#define Pop_32 CPU_Pop32
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#include "instructions.h"
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#include "core_normal/support.h"
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#include "core_normal/string.h"
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static GetEATable * EAPrefixTable[8] = {
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&GetEA_NONE,&GetEA_ADDR,&GetEA_SEG,&GetEA_SEG_ADDR,
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&GetEA_NONE,&GetEA_ADDR,&GetEA_SEG,&GetEA_SEG_ADDR,
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};
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#define CASE_W(_WHICH) \
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case (OPCODE_NONE+_WHICH):
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#define CASE_D(_WHICH) \
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case (OPCODE_SIZE+_WHICH):
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#define CASE_B(_WHICH) \
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CASE_W(_WHICH) \
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CASE_D(_WHICH)
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#define CASE_0F_W(_WHICH) \
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case ((OPCODE_0F|OPCODE_NONE)+_WHICH):
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#define CASE_0F_D(_WHICH) \
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case ((OPCODE_0F|OPCODE_SIZE)+_WHICH):
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#define CASE_0F_B(_WHICH) \
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CASE_0F_W(_WHICH) \
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CASE_0F_D(_WHICH)
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#define EALookupTable (*(core.ea_table))
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#define EALookupTable (core.ea_table)
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Bits CPU_Core_Normal_Run(void) {
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while (CPU_Cycles-->0) {
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LOADIP;
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core.opcode_index=cpu.code.big*0x200;
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core.prefixes=cpu.code.big;
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core.ea_table=&EATable[cpu.code.big*256];
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BaseDS=SegBase(ds);
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BaseSS=SegBase(ss);
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#if C_DEBUG
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#if C_HEAVY_DEBUG
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if (DEBUG_HeavyIsBreakpoint()) {
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@ -166,11 +153,8 @@ Bits CPU_Core_Normal_Run(void) {
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#endif
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cycle_count++;
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#endif
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restart_prefix:
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core.ea_table=EAPrefixTable[core.prefixes];
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restart_opcode:
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switch (core.opcode_index+Fetchb()) {
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#include "core_normal/prefix_none.h"
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#include "core_normal/prefix_0f.h"
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#include "core_normal/prefix_66.h"
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@ -141,3 +141,22 @@
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} \
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}
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#define CASE_W(_WHICH) \
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case (OPCODE_NONE+_WHICH):
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#define CASE_D(_WHICH) \
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case (OPCODE_SIZE+_WHICH):
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#define CASE_B(_WHICH) \
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CASE_W(_WHICH) \
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CASE_D(_WHICH)
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#define CASE_0F_W(_WHICH) \
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case ((OPCODE_0F|OPCODE_NONE)+_WHICH):
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#define CASE_0F_D(_WHICH) \
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case ((OPCODE_0F|OPCODE_SIZE)+_WHICH):
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#define CASE_0F_B(_WHICH) \
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CASE_0F_W(_WHICH) \
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CASE_0F_D(_WHICH)
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@ -341,12 +341,12 @@
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CASE_D(0x8d) /* LEA Gd */
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{
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//Little hack to always use segprefixed version
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core.seg_prefix_base=0;
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GetRMrd;
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BaseDS=BaseSS=0;
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if (TEST_PREFIX_ADDR) {
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*rmrd=(Bit32u)(*GetEA_SEG_ADDR[rm])();
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*rmrd=(Bit32u)(*EATable[256+rm])();
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} else {
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*rmrd=(Bit32u)(*GetEA_SEG[rm])();
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*rmrd=(Bit32u)(*EATable[rm])();
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}
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break;
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}
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@ -482,12 +482,12 @@
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CASE_W(0x8d) /* LEA Gw */
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{
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//Little hack to always use segprefixed version
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core.seg_prefix_base=0;
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BaseDS=BaseSS=0;
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GetRMrw;
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if (TEST_PREFIX_ADDR) {
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*rmrw=(Bit16u)(*GetEA_SEG_ADDR[rm])();
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*rmrw=(Bit16u)(*EATable[256+rm])();
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} else {
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*rmrw=(Bit16u)(*GetEA_SEG[rm])();
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*rmrw=(Bit16u)(*EATable[rm])();
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}
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break;
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}
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@ -788,18 +788,10 @@
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reg_al = get_CF() ? 0xFF : 0;
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break;
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CASE_B(0xd7) /* XLAT */
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if (TEST_PREFIX_SEG) {
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if (TEST_PREFIX_ADDR) {
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reg_al=LoadMb(core.seg_prefix_base+(Bit32u)(reg_ebx+reg_al));
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} else {
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reg_al=LoadMb(core.seg_prefix_base+(Bit16u)(reg_bx+reg_al));
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}
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if (TEST_PREFIX_ADDR) {
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reg_al=LoadMb(BaseDS+(Bit32u)(reg_ebx+reg_al));
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} else {
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if (TEST_PREFIX_ADDR) {
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reg_al=LoadMb(SegBase(ds)+(Bit32u)(reg_ebx+reg_al));
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} else {
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reg_al=LoadMb(SegBase(ds)+(Bit16u)(reg_bx+reg_al));
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}
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reg_al=LoadMb(BaseDS+(Bit16u)(reg_bx+reg_al));
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}
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break;
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#ifdef CPU_FPU
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@ -17,10 +17,9 @@ static void DoString(STRING_OP type) {
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Bitu count,count_left;
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Bits add_index;
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if (TEST_PREFIX_SEG) si_base=core.seg_prefix_base;
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else si_base=SegBase(ds);
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si_base=BaseDS;
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di_base=SegBase(es);
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add_mask=AddrMaskTable[core.prefixes& PREFIX_ADDR];
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add_mask=AddrMaskTable[core.prefixes & PREFIX_ADDR];
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si_index=reg_esi & add_mask;
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di_index=reg_edi & add_mask;
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count=reg_ecx & add_mask;
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@ -16,38 +16,18 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#define GETIP (core.cseip-SegBase(cs))
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#define SAVEIP reg_eip=GETIP;
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#define LOADIP core.cseip=(SegBase(cs)+reg_eip);
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#define RUNEXCEPTION() { \
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FillFlags(); \
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CPU_Exception(cpu.exception.which,cpu.exception.error); \
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continue; \
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}
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#define LoadMbs(off) (Bit8s)(LoadMb(off))
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#define LoadMws(off) (Bit16s)(LoadMw(off))
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#define LoadMds(off) (Bit32s)(LoadMd(off))
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#define EXCEPTION(blah) \
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{ \
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CPU_Exception(blah); \
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continue; \
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}
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#define LoadRb(reg) reg
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#define LoadRw(reg) reg
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#define LoadRd(reg) reg
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static INLINE Bit8u Fetchb() {
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Bit8u temp=LoadMb(core.cseip);
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core.cseip+=1;
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return temp;
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}
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static INLINE Bit16u Fetchw() {
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Bit16u temp=LoadMw(core.cseip);
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core.cseip+=2;
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return temp;
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}
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static INLINE Bit32u Fetchd() {
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Bit32u temp=LoadMd(core.cseip);
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core.cseip+=4;
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return temp;
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}
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#define SaveRb(reg,val) reg=val
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#define SaveRw(reg,val) reg=val
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#define SaveRd(reg,val) reg=val
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static INLINE Bit8s Fetchbs() {
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return Fetchb();
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@ -60,10 +40,18 @@ static INLINE Bit32s Fetchds() {
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return Fetchd();
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}
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#define Push_16 CPU_Push16
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#define Push_32 CPU_Push32
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#define Pop_16 CPU_Pop16
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#define Pop_32 CPU_Pop32
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#define RUNEXCEPTION() { \
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FillFlags(); \
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CPU_Exception(cpu.exception.which,cpu.exception.error); \
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continue; \
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}
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#define EXCEPTION(blah) \
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{ \
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CPU_Exception(blah); \
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continue; \
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}
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//TODO Could probably make all byte operands fast?
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#define JumpCond16_b(COND) { \
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@ -16,136 +16,35 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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typedef PhysPt (*GetEATable[256])(void);
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typedef PhysPt (*EA_LookupHandler)(void);
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/* The MOD/RM Decoder for EA for this decoder's addressing modes */
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static PhysPt EA_16_00_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_si); }
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static PhysPt EA_16_01_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_di); }
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static PhysPt EA_16_02_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_si); }
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static PhysPt EA_16_03_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_di); }
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static PhysPt EA_16_04_n(void) { return SegBase(ds)+(Bit16u)(reg_si); }
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static PhysPt EA_16_05_n(void) { return SegBase(ds)+(Bit16u)(reg_di); }
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static PhysPt EA_16_06_n(void) { return SegBase(ds)+(Bit16u)(Fetchw());}
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static PhysPt EA_16_07_n(void) { return SegBase(ds)+(Bit16u)(reg_bx); }
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static PhysPt EA_16_00_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_si); }
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static PhysPt EA_16_01_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_di); }
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static PhysPt EA_16_02_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_si); }
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static PhysPt EA_16_03_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_di); }
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static PhysPt EA_16_04_n(void) { return BaseDS+(Bit16u)(reg_si); }
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static PhysPt EA_16_05_n(void) { return BaseDS+(Bit16u)(reg_di); }
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static PhysPt EA_16_06_n(void) { return BaseDS+(Bit16u)(Fetchw());}
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static PhysPt EA_16_07_n(void) { return BaseDS+(Bit16u)(reg_bx); }
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static PhysPt EA_16_40_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchbs()); }
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static PhysPt EA_16_41_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchbs()); }
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static PhysPt EA_16_42_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchbs()); }
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static PhysPt EA_16_43_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchbs()); }
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static PhysPt EA_16_44_n(void) { return SegBase(ds)+(Bit16u)(reg_si+Fetchbs()); }
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static PhysPt EA_16_45_n(void) { return SegBase(ds)+(Bit16u)(reg_di+Fetchbs()); }
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static PhysPt EA_16_46_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+Fetchbs()); }
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static PhysPt EA_16_47_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+Fetchbs()); }
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static PhysPt EA_16_40_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchbs()); }
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static PhysPt EA_16_41_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchbs()); }
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static PhysPt EA_16_42_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchbs()); }
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static PhysPt EA_16_43_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchbs()); }
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static PhysPt EA_16_44_n(void) { return BaseDS+(Bit16u)(reg_si+Fetchbs()); }
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static PhysPt EA_16_45_n(void) { return BaseDS+(Bit16u)(reg_di+Fetchbs()); }
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static PhysPt EA_16_46_n(void) { return BaseSS+(Bit16u)(reg_bp+Fetchbs()); }
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static PhysPt EA_16_47_n(void) { return BaseDS+(Bit16u)(reg_bx+Fetchbs()); }
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static PhysPt EA_16_80_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchws()); }
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static PhysPt EA_16_81_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchws()); }
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static PhysPt EA_16_82_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchws()); }
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static PhysPt EA_16_83_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchws()); }
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static PhysPt EA_16_84_n(void) { return SegBase(ds)+(Bit16u)(reg_si+Fetchws()); }
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static PhysPt EA_16_85_n(void) { return SegBase(ds)+(Bit16u)(reg_di+Fetchws()); }
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static PhysPt EA_16_86_n(void) { return SegBase(ss)+(Bit16u)(reg_bp+Fetchws()); }
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static PhysPt EA_16_87_n(void) { return SegBase(ds)+(Bit16u)(reg_bx+Fetchws()); }
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static GetEATable GetEA_NONE={
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/* 00 */
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
/* 01 */
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
/* 10 */
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
/* 11 These are illegal so make em 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
|
||||
|
||||
static PhysPt EA_16_00_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_si); }
|
||||
static PhysPt EA_16_01_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_di); }
|
||||
static PhysPt EA_16_02_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_si); }
|
||||
static PhysPt EA_16_03_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_di); }
|
||||
static PhysPt EA_16_04_s(void) { return core.seg_prefix_base+(Bit16u)(reg_si); }
|
||||
static PhysPt EA_16_05_s(void) { return core.seg_prefix_base+(Bit16u)(reg_di); }
|
||||
static PhysPt EA_16_06_s(void) { return core.seg_prefix_base+(Bit16u)(Fetchw()); }
|
||||
static PhysPt EA_16_07_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx); }
|
||||
|
||||
static PhysPt EA_16_40_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchbs()); }
|
||||
static PhysPt EA_16_41_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchbs()); }
|
||||
static PhysPt EA_16_42_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchbs()); }
|
||||
static PhysPt EA_16_43_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchbs()); }
|
||||
static PhysPt EA_16_44_s(void) { return core.seg_prefix_base+(Bit16u)(reg_si+Fetchbs()); }
|
||||
static PhysPt EA_16_45_s(void) { return core.seg_prefix_base+(Bit16u)(reg_di+Fetchbs()); }
|
||||
static PhysPt EA_16_46_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+Fetchbs()); }
|
||||
static PhysPt EA_16_47_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+Fetchbs()); }
|
||||
|
||||
static PhysPt EA_16_80_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_81_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_82_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_83_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_84_s(void) { return core.seg_prefix_base+(Bit16u)(reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_85_s(void) { return core.seg_prefix_base+(Bit16u)(reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_86_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bp+Fetchws()); }
|
||||
static PhysPt EA_16_87_s(void) { return core.seg_prefix_base+(Bit16u)(reg_bx+Fetchws()); }
|
||||
|
||||
static GetEATable GetEA_SEG={
|
||||
/* 00 */
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
EA_16_00_s,EA_16_01_s,EA_16_02_s,EA_16_03_s,EA_16_04_s,EA_16_05_s,EA_16_06_s,EA_16_07_s,
|
||||
/* 01 */
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
EA_16_40_s,EA_16_41_s,EA_16_42_s,EA_16_43_s,EA_16_44_s,EA_16_45_s,EA_16_46_s,EA_16_47_s,
|
||||
/* 10 */
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
EA_16_80_s,EA_16_81_s,EA_16_82_s,EA_16_83_s,EA_16_84_s,EA_16_85_s,EA_16_86_s,EA_16_87_s,
|
||||
/* 11 These are illegal so make em 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
static PhysPt EA_16_80_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_81_n(void) { return BaseDS+(Bit16u)(reg_bx+(Bit16s)reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_82_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_83_n(void) { return BaseSS+(Bit16u)(reg_bp+(Bit16s)reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_84_n(void) { return BaseDS+(Bit16u)(reg_si+Fetchws()); }
|
||||
static PhysPt EA_16_85_n(void) { return BaseDS+(Bit16u)(reg_di+Fetchws()); }
|
||||
static PhysPt EA_16_86_n(void) { return BaseSS+(Bit16u)(reg_bp+Fetchws()); }
|
||||
static PhysPt EA_16_87_n(void) { return BaseDS+(Bit16u)(reg_bx+Fetchws()); }
|
||||
|
||||
static Bit32u SIBZero=0;
|
||||
static Bit32u * SIBIndex[8]= { ®_eax,®_ecx,®_edx,®_ebx,&SIBZero,®_ebp,®_esi,®_edi };
|
||||
|
|
@ -155,61 +54,92 @@ INLINE PhysPt Sib(Bitu mode) {
|
|||
PhysPt base;
|
||||
switch (sib&7) {
|
||||
case 0: /* EAX Base */
|
||||
base=SegBase(ds)+reg_eax;break;
|
||||
base=BaseDS+reg_eax;break;
|
||||
case 1: /* ECX Base */
|
||||
base=SegBase(ds)+reg_ecx;break;
|
||||
base=BaseDS+reg_ecx;break;
|
||||
case 2: /* EDX Base */
|
||||
base=SegBase(ds)+reg_edx;break;
|
||||
base=BaseDS+reg_edx;break;
|
||||
case 3: /* EBX Base */
|
||||
base=SegBase(ds)+reg_ebx;break;
|
||||
base=BaseDS+reg_ebx;break;
|
||||
case 4: /* ESP Base */
|
||||
base=SegBase(ss)+reg_esp;break;
|
||||
base=BaseSS+reg_esp;break;
|
||||
case 5: /* #1 Base */
|
||||
if (!mode) {
|
||||
base=SegBase(ds)+Fetchd();break;
|
||||
base=BaseDS+Fetchd();break;
|
||||
} else {
|
||||
base=SegBase(ss)+reg_ebp;break;
|
||||
base=BaseSS+reg_ebp;break;
|
||||
}
|
||||
case 6: /* ESI Base */
|
||||
base=SegBase(ds)+reg_esi;break;
|
||||
base=BaseDS+reg_esi;break;
|
||||
case 7: /* EDI Base */
|
||||
base=SegBase(ds)+reg_edi;break;
|
||||
base=BaseDS+reg_edi;break;
|
||||
}
|
||||
base+=*SIBIndex[(sib >> 3) &7] << (sib >> 6);
|
||||
return base;
|
||||
};
|
||||
|
||||
|
||||
static PhysPt EA_32_00_n(void) { return SegBase(ds)+reg_eax; }
|
||||
static PhysPt EA_32_01_n(void) { return SegBase(ds)+reg_ecx; }
|
||||
static PhysPt EA_32_02_n(void) { return SegBase(ds)+reg_edx; }
|
||||
static PhysPt EA_32_03_n(void) { return SegBase(ds)+reg_ebx; }
|
||||
static PhysPt EA_32_00_n(void) { return BaseDS+reg_eax; }
|
||||
static PhysPt EA_32_01_n(void) { return BaseDS+reg_ecx; }
|
||||
static PhysPt EA_32_02_n(void) { return BaseDS+reg_edx; }
|
||||
static PhysPt EA_32_03_n(void) { return BaseDS+reg_ebx; }
|
||||
static PhysPt EA_32_04_n(void) { return Sib(0);}
|
||||
static PhysPt EA_32_05_n(void) { return SegBase(ds)+Fetchd(); }
|
||||
static PhysPt EA_32_06_n(void) { return SegBase(ds)+reg_esi; }
|
||||
static PhysPt EA_32_07_n(void) { return SegBase(ds)+reg_edi; }
|
||||
static PhysPt EA_32_05_n(void) { return BaseDS+Fetchd(); }
|
||||
static PhysPt EA_32_06_n(void) { return BaseDS+reg_esi; }
|
||||
static PhysPt EA_32_07_n(void) { return BaseDS+reg_edi; }
|
||||
|
||||
static PhysPt EA_32_40_n(void) { return SegBase(ds)+reg_eax+Fetchbs(); }
|
||||
static PhysPt EA_32_41_n(void) { return SegBase(ds)+reg_ecx+Fetchbs(); }
|
||||
static PhysPt EA_32_42_n(void) { return SegBase(ds)+reg_edx+Fetchbs(); }
|
||||
static PhysPt EA_32_43_n(void) { return SegBase(ds)+reg_ebx+Fetchbs(); }
|
||||
static PhysPt EA_32_40_n(void) { return BaseDS+reg_eax+Fetchbs(); }
|
||||
static PhysPt EA_32_41_n(void) { return BaseDS+reg_ecx+Fetchbs(); }
|
||||
static PhysPt EA_32_42_n(void) { return BaseDS+reg_edx+Fetchbs(); }
|
||||
static PhysPt EA_32_43_n(void) { return BaseDS+reg_ebx+Fetchbs(); }
|
||||
static PhysPt EA_32_44_n(void) { PhysPt temp=Sib(1);return temp+Fetchbs();}
|
||||
//static PhysPt EA_32_44_n(void) { return Sib(1)+Fetchbs();}
|
||||
static PhysPt EA_32_45_n(void) { return SegBase(ss)+reg_ebp+Fetchbs(); }
|
||||
static PhysPt EA_32_46_n(void) { return SegBase(ds)+reg_esi+Fetchbs(); }
|
||||
static PhysPt EA_32_47_n(void) { return SegBase(ds)+reg_edi+Fetchbs(); }
|
||||
static PhysPt EA_32_45_n(void) { return BaseSS+reg_ebp+Fetchbs(); }
|
||||
static PhysPt EA_32_46_n(void) { return BaseDS+reg_esi+Fetchbs(); }
|
||||
static PhysPt EA_32_47_n(void) { return BaseDS+reg_edi+Fetchbs(); }
|
||||
|
||||
static PhysPt EA_32_80_n(void) { return SegBase(ds)+reg_eax+Fetchds(); }
|
||||
static PhysPt EA_32_81_n(void) { return SegBase(ds)+reg_ecx+Fetchds(); }
|
||||
static PhysPt EA_32_82_n(void) { return SegBase(ds)+reg_edx+Fetchds(); }
|
||||
static PhysPt EA_32_83_n(void) { return SegBase(ds)+reg_ebx+Fetchds(); }
|
||||
static PhysPt EA_32_80_n(void) { return BaseDS+reg_eax+Fetchds(); }
|
||||
static PhysPt EA_32_81_n(void) { return BaseDS+reg_ecx+Fetchds(); }
|
||||
static PhysPt EA_32_82_n(void) { return BaseDS+reg_edx+Fetchds(); }
|
||||
static PhysPt EA_32_83_n(void) { return BaseDS+reg_ebx+Fetchds(); }
|
||||
static PhysPt EA_32_84_n(void) { PhysPt temp=Sib(2);return temp+Fetchds();}
|
||||
//static PhysPt EA_32_84_n(void) { return Sib(2)+Fetchds();}
|
||||
static PhysPt EA_32_85_n(void) { return SegBase(ss)+reg_ebp+Fetchds(); }
|
||||
static PhysPt EA_32_86_n(void) { return SegBase(ds)+reg_esi+Fetchds(); }
|
||||
static PhysPt EA_32_87_n(void) { return SegBase(ds)+reg_edi+Fetchds(); }
|
||||
static PhysPt EA_32_85_n(void) { return BaseSS+reg_ebp+Fetchds(); }
|
||||
static PhysPt EA_32_86_n(void) { return BaseDS+reg_esi+Fetchds(); }
|
||||
static PhysPt EA_32_87_n(void) { return BaseDS+reg_edi+Fetchds(); }
|
||||
|
||||
static GetEATable GetEA_ADDR={
|
||||
static GetEAHandler EATable[512]={
|
||||
/* 00 */
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
EA_16_00_n,EA_16_01_n,EA_16_02_n,EA_16_03_n,EA_16_04_n,EA_16_05_n,EA_16_06_n,EA_16_07_n,
|
||||
/* 01 */
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
EA_16_40_n,EA_16_41_n,EA_16_42_n,EA_16_43_n,EA_16_44_n,EA_16_45_n,EA_16_46_n,EA_16_47_n,
|
||||
/* 10 */
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
EA_16_80_n,EA_16_81_n,EA_16_82_n,EA_16_83_n,EA_16_84_n,EA_16_85_n,EA_16_86_n,EA_16_87_n,
|
||||
/* 11 These are illegal so make em 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/* 00 */
|
||||
EA_32_00_n,EA_32_01_n,EA_32_02_n,EA_32_03_n,EA_32_04_n,EA_32_05_n,EA_32_06_n,EA_32_07_n,
|
||||
EA_32_00_n,EA_32_01_n,EA_32_02_n,EA_32_03_n,EA_32_04_n,EA_32_05_n,EA_32_06_n,EA_32_07_n,
|
||||
|
|
@ -244,113 +174,12 @@ static GetEATable GetEA_ADDR={
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
INLINE PhysPt Sib_s(Bitu mode) {
|
||||
Bit8u sib=Fetchb();
|
||||
PhysPt base;
|
||||
switch (sib&7) {
|
||||
case 0: /* EAX Base */
|
||||
base=reg_eax;break;
|
||||
case 1: /* ECX Base */
|
||||
base=reg_ecx;break;
|
||||
case 2: /* EDX Base */
|
||||
base=reg_edx;break;
|
||||
case 3: /* EBX Base */
|
||||
base=reg_ebx;break;
|
||||
case 4: /* ESP Base */
|
||||
base=reg_esp;break;
|
||||
case 5: /* #1 Base */
|
||||
if (!mode) {
|
||||
base=Fetchd();break;
|
||||
} else {
|
||||
base=reg_ebp;break;
|
||||
}
|
||||
case 6: /* ESI Base */
|
||||
base=reg_esi;break;
|
||||
case 7: /* EDI Base */
|
||||
base=reg_edi;break;
|
||||
}
|
||||
base+=*SIBIndex[(sib >> 3) &7] << (sib >> 6);
|
||||
return base;
|
||||
};
|
||||
|
||||
|
||||
static PhysPt EA_32_00_s(void) { return core.seg_prefix_base+(Bit32u)(reg_eax); }
|
||||
static PhysPt EA_32_01_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ecx); }
|
||||
static PhysPt EA_32_02_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edx); }
|
||||
static PhysPt EA_32_03_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ebx); }
|
||||
static PhysPt EA_32_04_s(void) { return core.seg_prefix_base+(Bit32u)(Sib_s(0));}
|
||||
static PhysPt EA_32_05_s(void) { return core.seg_prefix_base+(Bit32u)(Fetchd()); }
|
||||
static PhysPt EA_32_06_s(void) { return core.seg_prefix_base+(Bit32u)(reg_esi); }
|
||||
static PhysPt EA_32_07_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edi); }
|
||||
|
||||
static PhysPt EA_32_40_s(void) { return core.seg_prefix_base+(Bit32u)(reg_eax+Fetchbs()); }
|
||||
static PhysPt EA_32_41_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ecx+Fetchbs()); }
|
||||
static PhysPt EA_32_42_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edx+Fetchbs()); }
|
||||
static PhysPt EA_32_43_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ebx+Fetchbs()); }
|
||||
static PhysPt EA_32_44_s(void) { PhysPt temp=Sib_s(1);return core.seg_prefix_base+(Bit32u)(temp+Fetchbs());}
|
||||
static PhysPt EA_32_45_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ebp+Fetchbs()); }
|
||||
static PhysPt EA_32_46_s(void) { return core.seg_prefix_base+(Bit32u)(reg_esi+Fetchbs()); }
|
||||
static PhysPt EA_32_47_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edi+Fetchbs()); }
|
||||
|
||||
static PhysPt EA_32_80_s(void) { return core.seg_prefix_base+(Bit32u)(reg_eax+Fetchds()); }
|
||||
static PhysPt EA_32_81_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ecx+Fetchds()); }
|
||||
static PhysPt EA_32_82_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edx+Fetchds()); }
|
||||
static PhysPt EA_32_83_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ebx+Fetchds()); }
|
||||
static PhysPt EA_32_84_s(void) { PhysPt temp=Sib_s(2);return core.seg_prefix_base+(Bit32u)(temp+Fetchds());}
|
||||
static PhysPt EA_32_85_s(void) { return core.seg_prefix_base+(Bit32u)(reg_ebp+Fetchds()); }
|
||||
static PhysPt EA_32_86_s(void) { return core.seg_prefix_base+(Bit32u)(reg_esi+Fetchds()); }
|
||||
static PhysPt EA_32_87_s(void) { return core.seg_prefix_base+(Bit32u)(reg_edi+Fetchds()); }
|
||||
|
||||
|
||||
static GetEATable GetEA_SEG_ADDR={
|
||||
/* 00 */
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
EA_32_00_s,EA_32_01_s,EA_32_02_s,EA_32_03_s,EA_32_04_s,EA_32_05_s,EA_32_06_s,EA_32_07_s,
|
||||
/* 01 */
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
EA_32_40_s,EA_32_41_s,EA_32_42_s,EA_32_43_s,EA_32_44_s,EA_32_45_s,EA_32_46_s,EA_32_47_s,
|
||||
/* 10 */
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
EA_32_80_s,EA_32_81_s,EA_32_82_s,EA_32_83_s,EA_32_84_s,EA_32_85_s,EA_32_86_s,EA_32_87_s,
|
||||
/* 11 These are illegal so make em 0 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
#define GetEADirect \
|
||||
PhysPt eaa; \
|
||||
if (TEST_PREFIX_SEG) { \
|
||||
if (TEST_PREFIX_ADDR) { \
|
||||
eaa=core.seg_prefix_base+Fetchd(); \
|
||||
} else { \
|
||||
eaa=core.seg_prefix_base+Fetchw(); \
|
||||
} \
|
||||
} else { \
|
||||
if (TEST_PREFIX_ADDR) { \
|
||||
eaa=SegBase(ds)+Fetchd(); \
|
||||
} else { \
|
||||
eaa=SegBase(ds)+Fetchw(); \
|
||||
} \
|
||||
}
|
||||
#define GetEADirect \
|
||||
PhysPt eaa; \
|
||||
if (TEST_PREFIX_ADDR) { \
|
||||
eaa=BaseDS+Fetchd(); \
|
||||
} else { \
|
||||
eaa=BaseDS+Fetchw(); \
|
||||
} \
|
||||
|
||||
|
||||
|
|
|
|||
203
src/cpu/core_simple.cpp
Normal file
203
src/cpu/core_simple.cpp
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (C) 2002-2004 The DOSBox Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "dosbox.h"
|
||||
#include "mem.h"
|
||||
#include "cpu.h"
|
||||
#include "lazyflags.h"
|
||||
#include "inout.h"
|
||||
#include "callback.h"
|
||||
#include "pic.h"
|
||||
#include "fpu.h"
|
||||
|
||||
#if C_DEBUG
|
||||
#include "debug.h"
|
||||
#endif
|
||||
|
||||
#include "paging.h"
|
||||
#define SegBase(c) SegPhys(c)
|
||||
#define LoadMb(off) mem_readb(off)
|
||||
#define LoadMw(off) mem_readw(off)
|
||||
#define LoadMd(off) mem_readd(off)
|
||||
|
||||
#define SaveMb(off,val) mem_writeb(off,val)
|
||||
#define SaveMw(off,val) mem_writew(off,val)
|
||||
#define SaveMd(off,val) mem_writed(off,val)
|
||||
|
||||
extern Bitu cycle_count;
|
||||
|
||||
#if C_FPU
|
||||
#define CPU_FPU 1 //Enable FPU escape instructions
|
||||
#endif
|
||||
|
||||
#define CPU_PIC_CHECK 1
|
||||
#define CPU_TRAP_CHECK 1
|
||||
|
||||
#define OPCODE_NONE 0x000
|
||||
#define OPCODE_0F 0x100
|
||||
#define OPCODE_SIZE 0x200
|
||||
|
||||
#define PREFIX_ADDR 0x1
|
||||
#define PREFIX_REP 0x2
|
||||
|
||||
#define TEST_PREFIX_ADDR (core.prefixes & PREFIX_ADDR)
|
||||
#define TEST_PREFIX_REP (core.prefixes & PREFIX_REP)
|
||||
|
||||
#define DO_PREFIX_SEG(_SEG) \
|
||||
BaseDS=SegBase(_SEG); \
|
||||
BaseSS=SegBase(_SEG); \
|
||||
goto restart_opcode;
|
||||
|
||||
#define DO_PREFIX_ADDR() \
|
||||
core.prefixes=(core.prefixes & ~PREFIX_ADDR) | \
|
||||
(cpu.code.big ^ PREFIX_ADDR); \
|
||||
core.ea_table=&EATable[(core.prefixes&1) * 256]; \
|
||||
goto restart_opcode;
|
||||
|
||||
#define DO_PREFIX_REP(_ZERO) \
|
||||
core.prefixes|=PREFIX_REP; \
|
||||
core.rep_zero=_ZERO; \
|
||||
goto restart_opcode;
|
||||
|
||||
typedef PhysPt (*GetEAHandler)(void);
|
||||
|
||||
static const Bit32u AddrMaskTable[2]={0x0000ffff,0xffffffff};
|
||||
|
||||
static struct {
|
||||
Bitu opcode_index;
|
||||
HostPt cseip;
|
||||
PhysPt base_ds,base_ss;
|
||||
bool rep_zero;
|
||||
Bitu prefixes;
|
||||
GetEAHandler * ea_table;
|
||||
struct {
|
||||
bool skip;
|
||||
} trap;
|
||||
} core;
|
||||
|
||||
#define GETIP (core.cseip-SegBase(cs)-MemBase)
|
||||
#define SAVEIP reg_eip=GETIP;
|
||||
#define LOADIP core.cseip=(MemBase+SegBase(cs)+reg_eip);
|
||||
|
||||
#define SegBase(c) SegPhys(c)
|
||||
#define BaseDS core.base_ds
|
||||
#define BaseSS core.base_ss
|
||||
|
||||
static INLINE Bit8u Fetchb() {
|
||||
Bit8u temp=host_readb(core.cseip);
|
||||
core.cseip+=1;
|
||||
return temp;
|
||||
}
|
||||
|
||||
static INLINE Bit16u Fetchw() {
|
||||
Bit16u temp=host_readw(core.cseip);
|
||||
core.cseip+=2;
|
||||
return temp;
|
||||
}
|
||||
static INLINE Bit32u Fetchd() {
|
||||
Bit32u temp=host_readd(core.cseip);
|
||||
core.cseip+=4;
|
||||
return temp;
|
||||
}
|
||||
|
||||
#define Push_16 CPU_Push16
|
||||
#define Push_32 CPU_Push32
|
||||
#define Pop_16 CPU_Pop16
|
||||
#define Pop_32 CPU_Pop32
|
||||
|
||||
#include "instructions.h"
|
||||
#include "core_normal/support.h"
|
||||
#include "core_normal/string.h"
|
||||
|
||||
|
||||
#define EALookupTable (core.ea_table)
|
||||
|
||||
Bits CPU_Core_Simple_Run(void) {
|
||||
while (CPU_Cycles-->0) {
|
||||
LOADIP;
|
||||
core.opcode_index=cpu.code.big*0x200;
|
||||
core.prefixes=cpu.code.big;
|
||||
core.ea_table=&EATable[cpu.code.big*256];
|
||||
BaseDS=SegBase(ds);
|
||||
BaseSS=SegBase(ss);
|
||||
#if C_DEBUG
|
||||
#if C_HEAVY_DEBUG
|
||||
if (DEBUG_HeavyIsBreakpoint()) {
|
||||
FillFlags();
|
||||
return debugCallback;
|
||||
};
|
||||
#endif
|
||||
cycle_count++;
|
||||
#endif
|
||||
restart_opcode:
|
||||
switch (core.opcode_index+Fetchb()) {
|
||||
|
||||
#include "core_normal/prefix_none.h"
|
||||
#include "core_normal/prefix_0f.h"
|
||||
#include "core_normal/prefix_66.h"
|
||||
#include "core_normal/prefix_66_0f.h"
|
||||
default:
|
||||
illegal_opcode:
|
||||
#if C_DEBUG
|
||||
{
|
||||
Bitu len=(GETIP-reg_eip);
|
||||
LOADIP;
|
||||
if (len>16) len=16;
|
||||
char tempcode[16*2+1];char * writecode=tempcode;
|
||||
for (;len>0;len--) {
|
||||
// sprintf(writecode,"%X",mem_readb(core.cseip++));
|
||||
writecode+=2;
|
||||
}
|
||||
LOG(LOG_CPU,LOG_ERROR)("Illegal/Unhandled opcode %s",tempcode);
|
||||
}
|
||||
#endif
|
||||
CPU_Exception(6,0);
|
||||
continue;
|
||||
}
|
||||
SAVEIP;
|
||||
}
|
||||
FillFlags();
|
||||
return CBRET_NONE;
|
||||
decode_end:
|
||||
SAVEIP;
|
||||
FillFlags();
|
||||
return CBRET_NONE;
|
||||
}
|
||||
|
||||
Bits CPU_Core_Simple_Trap_Run(void) {
|
||||
|
||||
Bits oldCycles = CPU_Cycles;
|
||||
CPU_Cycles = 1;
|
||||
core.trap.skip=false;
|
||||
|
||||
Bits ret=CPU_Core_Normal_Run();
|
||||
if (!core.trap.skip) CPU_SW_Interrupt(1,reg_eip);
|
||||
CPU_Cycles = oldCycles-1;
|
||||
cpudecoder = &CPU_Core_Normal_Run;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void CPU_Core_Simple_Init(void) {
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* $Id: cpu.cpp,v 1.60 2004-08-04 09:12:51 qbix79 Exp $ */
|
||||
/* $Id: cpu.cpp,v 1.61 2004-08-23 12:17:29 harekiet Exp $ */
|
||||
|
||||
#include <assert.h>
|
||||
#include "dosbox.h"
|
||||
|
|
@ -48,6 +48,7 @@ CPU_Decoder * cpudecoder;
|
|||
|
||||
void CPU_Core_Full_Init(void);
|
||||
void CPU_Core_Normal_Init(void);
|
||||
void CPU_Core_Simple_Init(void);
|
||||
void CPU_Core_Dyn_X86_Init(void);
|
||||
|
||||
void CPU_Push16(Bitu value) {
|
||||
|
|
@ -1346,6 +1347,7 @@ void CPU_Init(Section* sec) {
|
|||
|
||||
/* Init the cpu cores */
|
||||
CPU_Core_Normal_Init();
|
||||
CPU_Core_Simple_Init();
|
||||
CPU_Core_Full_Init();
|
||||
#if (C_DYNAMIC_X86)
|
||||
CPU_Core_Dyn_X86_Init();
|
||||
|
|
@ -1360,6 +1362,8 @@ void CPU_Init(Section* sec) {
|
|||
cpudecoder=&CPU_Core_Normal_Run;
|
||||
if (!strcasecmp(core,"normal")) {
|
||||
cpudecoder=&CPU_Core_Normal_Run;
|
||||
} else if (!strcasecmp(core,"simple")) {
|
||||
cpudecoder=&CPU_Core_Simple_Run;
|
||||
} else if (!strcasecmp(core,"full")) {
|
||||
cpudecoder=&CPU_Core_Full_Run;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static Bits PageFaultCore(void) {
|
|||
if (!pf_queue.used) E_Exit("PF Core without PF");
|
||||
PF_Entry * entry=&pf_queue.entries[pf_queue.used-1];
|
||||
X86PageEntry pentry;
|
||||
pentry.load=MEM_PhysReadD(entry->page_addr);
|
||||
pentry.load=phys_readd(entry->page_addr);
|
||||
if (pentry.block.p && entry->cs == SegValue(cs) && entry->eip==reg_eip)
|
||||
return -1;
|
||||
return 0;
|
||||
|
|
@ -102,6 +102,8 @@ static Bits PageFaultCore(void) {
|
|||
Bitu DEBUG_EnableDebugger(void);
|
||||
#endif
|
||||
|
||||
bool first=false;
|
||||
|
||||
void PAGING_PageFault(PhysPt lin_addr,Bitu page_addr,Bitu type) {
|
||||
/* Save the state of the cpu cores */
|
||||
LazyFlags old_lflags;
|
||||
|
|
@ -112,6 +114,8 @@ void PAGING_PageFault(PhysPt lin_addr,Bitu page_addr,Bitu type) {
|
|||
paging.cr2=lin_addr;
|
||||
PF_Entry * entry=&pf_queue.entries[pf_queue.used++];
|
||||
LOG(LOG_PAGING,LOG_NORMAL)("PageFault at %X type %d queue %d",lin_addr,type,pf_queue.used);
|
||||
// LOG_MSG("EAX:%04X ECX:%04X EDX:%04X EBX:%04X",reg_eax,reg_ecx,reg_edx,reg_ebx);
|
||||
// LOG_MSG("CS:%04X EIP:%08X SS:%04x SP:%08X",SegValue(cs),reg_eip,SegValue(ss),reg_esp);
|
||||
entry->cs=SegValue(cs);
|
||||
entry->eip=reg_eip;
|
||||
entry->page_addr=page_addr;
|
||||
|
|
@ -125,10 +129,9 @@ void PAGING_PageFault(PhysPt lin_addr,Bitu page_addr,Bitu type) {
|
|||
LOG(LOG_PAGING,LOG_NORMAL)("Left PageFault for %x queue %d",lin_addr,pf_queue.used);
|
||||
memcpy(&lflags,&old_lflags,sizeof(LazyFlags));
|
||||
cpudecoder=old_cpudecoder;
|
||||
// LOG_MSG("SS:%04x SP:%08X",SegValue(ss),reg_esp);
|
||||
}
|
||||
|
||||
|
||||
void MEM_PhysWriteD(Bitu addr,Bit32u val);
|
||||
class InitPageHandler : public PageHandler {
|
||||
public:
|
||||
InitPageHandler() {flags=PFLAG_INIT|PFLAG_NOCODE;}
|
||||
|
|
@ -164,28 +167,28 @@ public:
|
|||
Bitu t_index=lin_page & 0x3ff;
|
||||
Bitu table_addr=(paging.base.page<<12)+d_index*4;
|
||||
X86PageEntry table;
|
||||
table.load=MEM_PhysReadD(table_addr);
|
||||
table.load=phys_readd(table_addr);
|
||||
if (!table.block.p) {
|
||||
LOG(LOG_PAGING,LOG_ERROR)("NP Table");
|
||||
PAGING_PageFault(lin_addr,table_addr,0);
|
||||
table.load=MEM_PhysReadD(table_addr);
|
||||
table.load=phys_readd(table_addr);
|
||||
if (!table.block.p)
|
||||
E_Exit("Pagefault didn't correct table");
|
||||
}
|
||||
table.block.a=table.block.d=1; //Set access/Dirty
|
||||
MEM_PhysWriteD(table_addr,table.load);
|
||||
phys_writed(table_addr,table.load);
|
||||
X86PageEntry entry;
|
||||
Bitu entry_addr=(table.block.base<<12)+t_index*4;
|
||||
entry.load=MEM_PhysReadD(entry_addr);
|
||||
entry.load=phys_readd(entry_addr);
|
||||
if (!entry.block.p) {
|
||||
LOG(LOG_PAGING,LOG_ERROR)("NP Page");
|
||||
PAGING_PageFault(lin_addr,entry_addr,0);
|
||||
entry.load=MEM_PhysReadD(entry_addr);
|
||||
entry.load=phys_readd(entry_addr);
|
||||
if (!entry.block.p)
|
||||
E_Exit("Pagefault didn't correct page");
|
||||
}
|
||||
entry.block.a=entry.block.d=1; //Set access/Dirty
|
||||
MEM_PhysWriteD(entry_addr,entry.load);
|
||||
phys_writed(entry_addr,entry.load);
|
||||
phys_page=entry.block.base;
|
||||
} else {
|
||||
if (lin_page<LINK_START) phys_page=mapfirstmb[lin_page];
|
||||
|
|
@ -200,10 +203,10 @@ bool PAGING_MakePhysPage(Bitu & page) {
|
|||
Bitu d_index=page >> 10;
|
||||
Bitu t_index=page & 0x3ff;
|
||||
X86PageEntry table;
|
||||
table.load=MEM_PhysReadD((paging.base.page<<12)+d_index*4);
|
||||
table.load=phys_readd((paging.base.page<<12)+d_index*4);
|
||||
if (!table.block.p) return false;
|
||||
X86PageEntry entry;
|
||||
entry.load=MEM_PhysReadD((table.block.base<<12)+t_index*4);
|
||||
entry.load=phys_readd((table.block.base<<12)+t_index*4);
|
||||
if (!entry.block.p) return false;
|
||||
page=entry.block.base;
|
||||
} else {
|
||||
|
|
@ -281,7 +284,7 @@ void PAGING_SetDirBase(Bitu cr3) {
|
|||
|
||||
paging.base.page=cr3 >> 12;
|
||||
paging.base.addr=cr3 & ~4095;
|
||||
LOG(LOG_PAGING,LOG_NORMAL)("CR3:%X Base %X",cr3,paging.base.page);
|
||||
// LOG(LOG_PAGING,LOG_NORMAL)("CR3:%X Base %X",cr3,paging.base.page);
|
||||
if (paging.enabled) {
|
||||
PAGING_ClearTLB();
|
||||
}
|
||||
|
|
@ -292,9 +295,15 @@ void PAGING_Enable(bool enabled) {
|
|||
if (paging.enabled==enabled) return;
|
||||
paging.enabled=enabled;
|
||||
if (!enabled) {
|
||||
LOG(LOG_PAGING,LOG_NORMAL)("Disabled");
|
||||
// LOG(LOG_PAGING,LOG_NORMAL)("Disabled");
|
||||
} else {
|
||||
LOG(LOG_PAGING,LOG_NORMAL)("Enabled");
|
||||
if (cpudecoder==CPU_Core_Simple_Run) {
|
||||
LOG_MSG("CPU core simple won't run this game,switching to normal");
|
||||
cpudecoder=CPU_Core_Normal_Run;
|
||||
CPU_CycleLeft+=CPU_Cycles;
|
||||
CPU_Cycles=0;
|
||||
}
|
||||
// LOG(LOG_PAGING,LOG_NORMAL)("Enabled");
|
||||
PAGING_SetDirBase(paging.cr3);
|
||||
}
|
||||
PAGING_ClearTLB();
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue