valter/dosbox-staging
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Added 32-bit ENTER and fixed 16-bit one

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Added 32-bit XLAT


Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@962
This commit is contained in:
Sjoerd van der Berg 2003-04-25 08:42:42 +00:00
parent 1651123cbf
commit 1f5dac8c97
3 changed files with 70 additions and 10 deletions
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71
src/cpu/core_full/load.h
View file

@ -317,10 +317,14 @@ l_M_Ed:
case D_SETALC:
reg_al = get_CF() ? 0xFF : 0;
goto nextopcode;
case D_XLAT:
case D_XLATw:
if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_bx+reg_al);
else reg_al=LoadMb(SegBase(ds)+reg_bx+reg_al);
goto nextopcode;
case D_XLATd:
if (inst.prefix & PREFIX_SEG) reg_al=LoadMb(inst.seg.base+reg_ebx+reg_al);
else reg_al=LoadMb(SegBase(ds)+reg_ebx+reg_al);
goto nextopcode;
case D_CBW:
reg_ax=(Bit8s)reg_al;
goto nextopcode;
@ -371,11 +375,66 @@ l_M_Ed:
goto nextopcode;
case D_ENTERw:
{
Bit16u bytes=Fetchw();Bit8u level=Fetchb();
Push_16(reg_bp);reg_bp=reg_sp;reg_sp-=bytes;
EAPoint reader=SegBase(ss)+reg_bp;
for (Bit8u i=1;i<level;i++) {Push_16(LoadMw(reader));reader-=2;}
if (level) Push_16(reg_bp);
Bitu bytes=Fetchw();Bitu level=Fetchb() & 0x1f;
Bitu frame_ptr=reg_esp-2;
if (cpu.state & STATE_STACK32) {
reg_esp-=2;
mem_writew(SegBase(ss)+reg_esp,reg_bp);
for (Bitu i=1;i<level;i++) {
reg_ebp-=2;reg_esp-=2;
mem_writew(SegBase(ss)+reg_esp,mem_readw(SegBase(ss)+reg_ebp));
}
if (level) {
reg_esp-=2;
mem_writew(SegBase(ss)+reg_esp,(Bit16u)frame_ptr);
}
reg_esp-=bytes;
} else {
reg_sp-=2;
mem_writew(SegBase(ss)+reg_sp,reg_bp);
for (Bitu i=1;i<level;i++) {
reg_bp-=2;reg_sp-=2;
mem_writew(SegBase(ss)+reg_sp,mem_readw(SegBase(ss)+reg_bp));
}
if (level) {
reg_sp-=2;
mem_writew(SegBase(ss)+reg_sp,(Bit16u)frame_ptr);
}
reg_sp-=bytes;
}
reg_bp=frame_ptr;
goto nextopcode;
}
case D_ENTERd:
{
Bitu bytes=Fetchw();Bitu level=Fetchb() & 0x1f;
Bitu frame_ptr=reg_esp-4;
if (cpu.state & STATE_STACK32) {
reg_esp-=4;
mem_writed(SegBase(ss)+reg_esp,reg_ebp);
for (Bitu i=1;i<level;i++) {
reg_ebp-=4;reg_esp-=4;
mem_writed(SegBase(ss)+reg_esp,mem_readd(SegBase(ss)+reg_ebp));
}
if (level) {
reg_esp-=4;
mem_writed(SegBase(ss)+reg_esp,(Bit32u)frame_ptr);
}
reg_esp-=bytes;
} else {
reg_sp-=4;
mem_writed(SegBase(ss)+reg_sp,reg_ebp);
for (Bitu i=1;i<level;i++) {
reg_bp-=4;reg_sp-=4;
mem_writed(SegBase(ss)+reg_sp,mem_readd(SegBase(ss)+reg_bp));
}
if (level) {
reg_sp-=4;
mem_writed(SegBase(ss)+reg_sp,(Bit32u)frame_ptr);
}
reg_sp-=bytes;
}
reg_ebp=frame_ptr;
goto nextopcode;
}
case D_LEAVEw:

7
src/cpu/core_full/optable.h
View file

@ -150,7 +150,7 @@ static OpCode OpCodeTable[1024]={
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,6 ,0 ,M_GRP_1 },
{L_MODRM ,5 ,0 ,M_GRP_CL },{L_MODRM ,6 ,0 ,M_GRP_CL },
{L_Ib ,O_AAM ,0 ,0 },{L_Ib ,O_AAD ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLAT ,0 ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLATw ,0 ,0 ,0 },
//TODO FPU
/* 0xd8 - 0xdf */
{L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 },
@ -466,7 +466,8 @@ static OpCode OpCodeTable[1024]={
{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_SI},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_DI},
/* 0x298 - 0x29f */
{D_CWDE ,0 ,0 ,0 },{D_CDQ ,0 ,0 ,0 },
{L_Ifd ,O_CALLFd ,0 ,0 },{L_ERROR ,0 ,0 ,0 },
//TODO Wait shoudn't be nop
{L_Ifd ,O_CALLFd ,0 ,0 },{D_NOP ,0 ,0 ,0 },
{L_FLG ,0 ,S_PUSHd,0 },{L_POPd ,0 ,S_FLGd ,0 },
{L_REGb ,0 ,S_FLGb ,REGI_AH},{L_FLG ,0 ,S_REGb ,REGI_AH},
@ -507,7 +508,7 @@ static OpCode OpCodeTable[1024]={
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,7 ,0 ,M_GRP_1 },
{L_MODRM ,5 ,0 ,M_GRP_CL },{L_MODRM ,7 ,0 ,M_GRP_CL },
{L_Ib ,O_AAM ,0 ,0 },{L_Ib ,O_AAD ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
{D_SETALC ,0 ,0 ,0 },{D_XLATd ,0 ,0 ,0 },
/* 0x2d8 - 0x2df */
{L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 },
{L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 },

2
src/cpu/core_full/support.h
View file

@ -34,7 +34,7 @@ enum {
D_CBW,D_CWDE,
D_CWD,D_CDQ,
D_SETALC,
D_XLAT,
D_XLATw,D_XLATd,
D_CLI,D_STI,D_STC,D_CLC,D_CMC,D_CLD,D_STD,
D_NOP,
D_ENTERw,D_ENTERd,