valter/dosbox-staging
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Merge branch 'svn/trunk' r4333

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Conflict resolutions required some algorithm adjustments.
This commit is contained in:
Patryk Obara 2020-02-25 10:07:58 +01:00
commit 5e41eaf150
6 changed files with 108 additions and 99 deletions
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5
src/cpu/core_dyn_x86/risc_x64.h
View file

@ -611,7 +611,8 @@ static void gen_dop_byte(DualOps op,DynReg * dr1,Bitu di1,DynReg * dr2,Bitu di2)
case DOP_OR: tmp=0x0a; if ((dr1==dr2) && (di1==di2)) goto nochange; break;
case DOP_TEST: tmp=0x84; goto nochange;
case DOP_MOV: if ((dr1==dr2) && (di1==di2)) return; tmp=0x8a; break;
case DOP_XCHG: tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
case DOP_XCHG: if ((dr1==dr2) && (di1==di2)) return;
tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
default:
IllegalOption("gen_dop_byte");
}
@ -789,7 +790,7 @@ static void gen_dop_word(DualOps op,bool dword,DynReg * dr1,DynReg * dr2) {
case DOP_OR: tmp=0x0b; if (dr1==dr2) goto nochange; break;
case DOP_TEST: tmp=0x85; goto nochange;
case DOP_MOV: if (dr1==dr2) return; tmp=0x8b; break;
case DOP_XCHG:
case DOP_XCHG: if (dr1==dr2) return;
dr2->flags|=DYNFLG_CHANGED;
if (dword && !((dr1->flags&DYNFLG_HAS8) ^ (dr2->flags&DYNFLG_HAS8))) {
dr1->genreg=gr2;gr2->dynreg=dr1;

5
src/cpu/core_dyn_x86/risc_x86.h
View file

@ -343,7 +343,8 @@ static void gen_dop_byte(DualOps op,DynReg * dr1,Bit8u di1,DynReg * dr2,Bit8u di
case DOP_OR: tmp=0x0a; if ((dr1==dr2) && (di1==di2)) goto nochange; break;
case DOP_TEST: tmp=0x84; goto nochange;
case DOP_MOV: if ((dr1==dr2) && (di1==di2)) return; tmp=0x8a; break;
case DOP_XCHG: tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
case DOP_XCHG: if ((dr1==dr2) && (di1==di2)) return;
tmp=0x86; dr2->flags|=DYNFLG_CHANGED; break;
default:
IllegalOption("gen_dop_byte");
}
@ -510,7 +511,7 @@ static void gen_dop_word(DualOps op,bool dword,DynReg * dr1,DynReg * dr2) {
case DOP_OR: tmp=0x0b; if (dr1==dr2) goto nochange; break;
case DOP_TEST: tmp=0x85; goto nochange;
case DOP_MOV: if (dr1==dr2) return; tmp=0x8b; break;
case DOP_XCHG:
case DOP_XCHG: if (dr1==dr2) return;
dr2->flags|=DYNFLG_CHANGED;
if (dword && !((dr1->flags&DYNFLG_HAS8) ^ (dr2->flags&DYNFLG_HAS8))) {
dr1->genreg=gr2;dr1->genreg->dynreg=dr1;