fix for virtual pool (vasyl)
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@2668
This commit is contained in:
Sebastian Strohhäcker
parent
ec1c470020
commit
7a842811f0
3 changed files with 44 additions and 26 deletions
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@ -140,8 +140,23 @@ typedef struct {
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Bit8u mc[64][64];
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} VGA_HWCURSOR;
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typedef union {
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Bit32u fullbank;
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#ifndef WORDS_BIGENDIAN
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struct {
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Bit16u lowerbank;
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Bit16u bank;
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} b;
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#else
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struct {
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Bit16u bank;
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Bit16u lowerbank;
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} b;
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#endif
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} VGA_S3_BANK;
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typedef struct {
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Bit8u bank;
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VGA_S3_BANK svga_bank;
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Bit8u reg_lock1;
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Bit8u reg_lock2;
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Bit8u reg_31;
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@ -83,6 +83,7 @@ static struct {
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class VGA_UnchainedRead_Handler : public PageHandler {
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public:
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Bitu readHandler(PhysPt start) {
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start += vga.s3.svga_bank.fullbank;
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vga.latch.d=vga.mem.latched[start].d;
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switch (vga.config.read_mode) {
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case 0:
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@ -253,10 +254,10 @@ public:
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vga.mem.linear[((addr&~3)<<2)|(addr&3)] = val;
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// Linearized version for faster rendering
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vga.mem.linear[512*1024+addr] = val;
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if (addr >= 320) return;
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// And replicate the first line
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if (addr < 320)
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vga.mem.linear[512*1024+addr+64*1024] = val;
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}
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vga.mem.linear[512*1024+addr+64*1024] = val;
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}
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public:
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VGA_ChainedVGA_Handler() {
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flags=PFLAG_NOCODE;
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@ -282,13 +283,13 @@ public:
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class VGA_UnchainedVGA_Handler : public VGA_UnchainedRead_Handler {
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public:
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void writeHandler( PhysPt addr, Bit8u val ) {
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addr += vga.s3.svga_bank.fullbank;
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Bit32u data=ModeOperation(val);
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VGA_Latch pixels;
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pixels.d=vga.mem.latched[addr].d;
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pixels.d&=vga.config.full_not_map_mask;
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pixels.d|=(data & vga.config.full_map_mask);
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vga.mem.latched[addr].d=pixels.d;
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vga.mem.latched[addr+64*1024].d=pixels.d;
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}
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public:
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VGA_UnchainedVGA_Handler() {
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@ -336,11 +337,11 @@ public:
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}
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HostPt GetHostReadPt(Bitu phys_page) {
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phys_page-=vgapages.base;
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return &vga.mem.linear[vga.s3.bank*64*1024+phys_page*4096];
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return &vga.mem.linear[vga.s3.svga_bank.fullbank+phys_page*4096];
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}
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HostPt GetHostWritePt(Bitu phys_page) {
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phys_page-=vgapages.base;
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return &vga.mem.linear[vga.s3.bank*64*1024+phys_page*4096];
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return &vga.mem.linear[vga.s3.svga_bank.fullbank+phys_page*4096];
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}
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};
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@ -392,18 +393,18 @@ public:
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flags=PFLAG_NOCODE;
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}
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void writeb(PhysPt addr,Bitu val) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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writeHandler(addr+0,(Bit8u)(val >> 0));
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}
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void writew(PhysPt addr,Bitu val) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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writeHandler(addr+0,(Bit8u)(val >> 0));
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writeHandler(addr+1,(Bit8u)(val >> 8));
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}
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void writed(PhysPt addr,Bitu val) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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writeHandler(addr+0,(Bit8u)(val >> 0));
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writeHandler(addr+1,(Bit8u)(val >> 8));
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@ -411,19 +412,19 @@ public:
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writeHandler(addr+3,(Bit8u)(val >> 24));
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}
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Bitu readb(PhysPt addr) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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return readHandler(addr);
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}
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Bitu readw(PhysPt addr) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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return
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(readHandler(addr+0) << 0) |
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(readHandler(addr+1) << 8);
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}
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Bitu readd(PhysPt addr) {
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addr = vga.s3.bank*64*1024 + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr = vga.s3.svga_bank.fullbank + (PAGING_GetPhysicalAddress(addr) & 0xffff);
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addr &= (512*1024-1);
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return
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(readHandler(addr+0) << 0) |
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@ -634,12 +635,12 @@ void VGA_SetupHandlers(void) {
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case M_LIN4:
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range_handler=&vgaph.l4banked;
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break;
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case M_LIN8:
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case M_LIN15:
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case M_LIN16:
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case M_LIN32:
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range_handler=&vgaph.map;
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break;
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case M_LIN8:
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case M_VGA:
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if (vga.config.chained) {
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if(vga.config.compatible_chain4)
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@ -727,6 +728,7 @@ void VGA_UnmapMMIO(void) {
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void VGA_SetupMemory() {
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memset((void *)&vga.mem,0,512*1024*4);
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vga.s3.svga_bank.fullbank=0;
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if (machine==MCH_PCJR) {
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/* PCJr does not have dedicated graphics memory but uses
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conventional memory below 128k */
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: vga_s3.cpp,v 1.3 2006-02-14 12:44:38 qbix79 Exp $ */
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/* $Id: vga_s3.cpp,v 1.4 2006-07-08 16:32:26 c2woody Exp $ */
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#include "dosbox.h"
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#include "inout.h"
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@ -26,7 +26,8 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) {
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switch (reg) {
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case 0x31: /* CR31 Memory Configuration */
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//TODO Base address
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vga.s3.reg_31 = val;
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vga.s3.reg_31 = val;
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vga.config.compatible_chain4 = !(val&0x08);
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VGA_DetermineMode();
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break;
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/*
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@ -46,9 +47,9 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) {
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case 0x35: /* CR35 CRT Register Lock */
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if (vga.s3.reg_lock1 != 0x48) return; //Needed for uvconfig detection
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vga.s3.reg_35=val & 0xf0;
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if ((vga.s3.bank & 0xf) ^ (val & 0xf)) {
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vga.s3.bank&=0xf0;
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vga.s3.bank|=val & 0xf;
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if ((vga.s3.svga_bank.b.bank & 0xf) ^ (val & 0xf)) {
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vga.s3.svga_bank.b.bank&=0xf0;
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vga.s3.svga_bank.b.bank|=val & 0xf;
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VGA_SetupHandlers();
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}
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break;
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@ -128,9 +129,9 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) {
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//TODO Display start
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vga.config.display_start&=0xFCFFFF;
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vga.config.display_start|=(val & 3) << 16;
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if ((vga.s3.bank&0xcf) ^ ((val&0xc)<<2)) {
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vga.s3.bank&=0xcf;
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vga.s3.bank|=(val&0xc)<<2;
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if ((vga.s3.svga_bank.b.bank&0xcf) ^ ((val&0xc)<<2)) {
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vga.s3.svga_bank.b.bank&=0xcf;
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vga.s3.svga_bank.b.bank|=(val&0xc)<<2;
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VGA_SetupHandlers();
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}
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if (((val & 0x30) ^ (vga.config.scan_len >> 4)) & 0x30) {
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@ -297,7 +298,7 @@ void SVGA_S3_WriteCRTC(Bitu reg,Bitu val,Bitu iolen) {
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}
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break;
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case 0x6a: /* Extended System Control 4 */
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vga.s3.bank=val & 0x3f;
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vga.s3.svga_bank.b.bank=val & 0x3f;
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VGA_SetupHandlers();
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break;
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default:
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@ -323,7 +324,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) {
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//TODO mix in bits from baseaddress;
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return vga.s3.reg_31;
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case 0x35: /* CR35 CRT Register Lock */
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return vga.s3.reg_35|(vga.s3.bank & 0xf);
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return vga.s3.reg_35|(vga.s3.svga_bank.b.bank & 0xf);
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case 0x36: /* CR36 Reset State Read 1 */
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//return 0x8f;
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return 0x8e; /* PCI version */
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@ -344,7 +345,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) {
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return vga.s3.hgc.curmode;
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case 0x51: /* Extended System Control 2 */
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return ((vga.config.display_start >> 16) & 3 ) |
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((vga.s3.bank & 0x30) >> 2) |
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((vga.s3.svga_bank.b.bank & 0x30) >> 2) |
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((vga.config.scan_len & 0x300) >> 4) |
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vga.s3.reg_51;
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case 0x53:
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@ -366,7 +367,7 @@ Bitu SVGA_S3_ReadCRTC( Bitu reg, Bitu iolen) {
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case 0x69: /* Extended System Control 3 */
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return (Bit8u)((vga.config.display_start & 0x1f0000)>>16);
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case 0x6a: /* Extended System Control 4 */
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return (Bit8u)(vga.s3.bank & 0x3f);
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return (Bit8u)(vga.s3.svga_bank.b.bank & 0x3f);
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default:
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return 0x00;
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}
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