Changes for new flags
Opcodes moved into instructions.h Added support for a load of protected mode related opcodes. Fixed some opcodes. Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@920
This commit is contained in:
Sjoerd van der Berg
parent
4826bf78e0
commit
bb7bd6c3be
9 changed files with 423 additions and 383 deletions
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@ -32,6 +32,7 @@ static EAPoint IPPoint;
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#include "core_full/ea_lookup.h"
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#include "instructions.h"
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static INLINE void DecodeModRM(void) {
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inst.rm=Fetchb();
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inst.rm_index=(inst.rm >> 3) & 7;
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@ -41,14 +42,25 @@ static INLINE void DecodeModRM(void) {
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if (inst.rm<0xc0) inst.rm_eaa=(inst.prefix & PREFIX_ADDR) ? RMAddress_32() : RMAddress_16();
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}
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#define EXCEPTION(blah) \
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{ \
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Bit8u new_num=blah; \
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SaveIP(); \
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Interrupt(new_num); \
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LoadIP(); \
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goto nextopcode; \
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}
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Bitu Full_DeCode(void) {
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LoadIP();
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while (CPU_Cycles>0) {
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#if C_DEBUG
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cycle_count++;
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#endif
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CPU_Cycles--;
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inst.entry=cpu.full.entry;
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inst.prefix=cpu.full.prefix;
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restartopcode:
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inst.entry=(inst.entry & 0xffffff00) | Fetchb();
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@ -56,9 +68,7 @@ restartopcode:
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#include "core_full/load.h"
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#include "core_full/op.h"
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#include "core_full/save.h"
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nextopcode:
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inst.prefix=0;
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inst.entry=0;
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nextopcode:;
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}
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SaveIP();
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return 0;
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@ -67,4 +77,4 @@ nextopcode:
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void CPU_Core_Full_Start(void) {
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cpudecoder=&Full_DeCode;
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}
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}
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@ -213,10 +213,8 @@ l_M_Ed:
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inst.op1.d=reg_32(inst.code.extra);
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break;
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case L_FLG:
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inst.op1.d= (get_CF() << 0) | (get_PF() << 2) | (get_AF() << 4) |
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(get_ZF() << 6) | (get_SF() << 7) | (flags.tf << 8) |
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(flags.intf << 9) |(flags.df << 10) | (get_OF() << 11) |
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(flags.io << 12) | (flags.nt <<14);
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FILLFLAGS;
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inst.op1.d = flags.word;
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break;
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case L_SEG:
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inst.op1.d=SegValue((SegNames)inst.code.extra);
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@ -263,25 +261,47 @@ l_M_Ed:
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if (!get_OF()) goto nextopcode;
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inst.op1.d=4;
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break;
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case L_IRETw:
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inst.op1.d=Pop_16();
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inst.op2.d=Pop_16();
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{
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Bitu temp=Pop_16();
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Save_Flagsw(temp);
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}
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break;
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case D_IRETw:
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CPU_IRET(false);
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LoadIP();
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goto nextopcode;
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case D_IRETd:
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CPU_IRET(true);
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LoadIP();
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goto nextopcode;
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case D_RETFwIw:
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CPU_RET(false,Fetchw());
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LoadIP();
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goto nextopcode;
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case D_RETFw:
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CPU_RET(false,0);
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LoadIP();
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goto nextopcode;
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case D_RETFdIw:
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CPU_RET(true,Fetchw());
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LoadIP();
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goto nextopcode;
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case D_RETFd:
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CPU_RET(true,0);
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LoadIP();
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goto nextopcode;
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/* Direct operations */
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case L_STRING:
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#include "string.h"
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goto nextopcode;
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goto nextopcode;
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case D_PUSHAw:
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Push_16(reg_ax);Push_16(reg_cx);Push_16(reg_dx);Push_16(reg_bx);
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Push_16(reg_sp);Push_16(reg_bp);Push_16(reg_si);Push_16(reg_di);
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{
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Bit16u old_sp=reg_sp;
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Push_16(reg_ax);Push_16(reg_cx);Push_16(reg_dx);Push_16(reg_bx);
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Push_16(old_sp);Push_16(reg_bp);Push_16(reg_si);Push_16(reg_di);
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}
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goto nextopcode;
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case D_PUSHAd:
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Push_32(reg_eax);Push_32(reg_ecx);Push_32(reg_edx);Push_32(reg_ebx);
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Push_32(reg_esp);Push_32(reg_ebp);Push_32(reg_esi);Push_32(reg_edi);
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{
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Bit32u old_esp=reg_esp;
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Push_32(reg_eax);Push_32(reg_ecx);Push_32(reg_edx);Push_32(reg_ebx);
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Push_32(old_esp);Push_32(reg_ebp);Push_32(reg_esi);Push_32(reg_edi);
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}
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goto nextopcode;
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case D_POPAw:
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reg_di=Pop_16();reg_si=Pop_16();reg_bp=Pop_16();Pop_16();//Don't save SP
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@ -310,36 +330,36 @@ l_M_Ed:
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else reg_edx=0;
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goto nextopcode;
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case D_CLI:
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flags.intf=false;
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SETFLAGBIT(IF,false);
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goto nextopcode;
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case D_STI:
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flags.intf=true;
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if (flags.intf && PIC_IRQCheck) {
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SETFLAGBIT(IF,true);
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if (PIC_IRQCheck) {
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SaveIP();
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PIC_runIRQs();
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LoadIP();
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}
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goto nextopcode;
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case D_STC:
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flags.cf=true;
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SETFLAGBIT(CF,true);
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if (flags.type!=t_CF) flags.prev_type=flags.type;
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flags.type=t_CF;
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goto nextopcode;
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case D_CLC:
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flags.cf=false;
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SETFLAGBIT(CF,false);
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if (flags.type!=t_CF) flags.prev_type=flags.type;
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flags.type=t_CF;
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goto nextopcode;
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case D_CMC:
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flags.cf=!get_CF();
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SETFLAGBIT(CF,!get_CF());
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if (flags.type!=t_CF) flags.prev_type=flags.type;
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flags.type=t_CF;
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goto nextopcode;
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case D_CLD:
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flags.df=false;
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SETFLAGBIT(DF,false);
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goto nextopcode;
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case D_STD:
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flags.df=true;
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SETFLAGBIT(DF,true);
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goto nextopcode;
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case D_NOP:
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goto nextopcode;
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@ -357,63 +377,16 @@ l_M_Ed:
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reg_bp=Pop_16();
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goto nextopcode;
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case D_DAA:
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if (((reg_al & 0x0F)>0x09) || get_AF()) {
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reg_al+=0x06;
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flags.af=true;
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} else {
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flags.af=false;
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}
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flags.cf=get_CF();
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if ((reg_al > 0x9F) || flags.cf) {
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reg_al+=0x60;
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flags.cf=true;
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} else {
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flags.cf=false;
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}
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flags.sf=(reg_al&0x80)>0;
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flags.zf=(reg_al==0);
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flags.type=t_UNKNOWN;
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DAA();
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goto nextopcode;
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case D_DAS:
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if (((reg_al & 0x0f) > 9) || get_AF()) {
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reg_al-=6;
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flags.af=true;
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} else {
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flags.af=false;
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}
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if ((reg_al>0x9f) || get_CF()) {
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reg_al-=0x60;
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flags.cf=true;
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} else {
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flags.cf=false;
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}
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flags.type=t_UNKNOWN;
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DAS();
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goto nextopcode;
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case D_AAA:
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if (get_AF() || ((reg_al & 0xf) > 9))
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{
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reg_al += 6;
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reg_ah += 1;
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flags.af=true;
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flags.cf=true;
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} else {
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flags.af=false;
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flags.cf=false;
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}
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reg_al &= 0x0F;
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flags.type=t_UNKNOWN;
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AAA();
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goto nextopcode;
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case D_AAS:
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if (((reg_al & 0x0f)>9) || get_AF()) {
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reg_ah--;
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if (reg_al < 6) reg_ah--;
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reg_al=(reg_al-6) & 0xF;
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flags.af=flags.cf=true;
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} else {
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flags.af=flags.cf=false;
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}
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reg_al&=0xf;
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flags.type=t_UNKNOWN;
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AAS();
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goto nextopcode;
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default:
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LOG(LOG_CPU|LOG_ERROR,"LOAD:Unhandled code %d opcode %X",inst.code.load,inst.entry);
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@ -13,7 +13,7 @@ static INLINE Bit8u Fetchb() {
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IPPoint+=1;
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return temp;
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}
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static INLINE Bit16u Fetchw() {
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Bit16u temp=LoadMw(IPPoint);
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IPPoint+=2;
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@ -37,39 +37,50 @@ static INLINE Bit32s Fetchds() {
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}
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static INLINE void Push_16(Bit16u blah) {
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reg_sp-=2;
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SaveMw(SegBase(ss)+reg_sp,blah);
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};
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if (cpu.state & STATE_STACK32) {
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reg_esp-=2;
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SaveMw(SegBase(ss)+reg_esp,blah);
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} else {
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reg_sp-=2;
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SaveMw(SegBase(ss)+reg_sp,blah);
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}
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}
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static INLINE void Push_32(Bit32u blah) {
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reg_sp-=4;
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SaveMd(SegBase(ss)+reg_sp,blah);
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};
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static INLINE Bit16u Pop_16() {
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Bit16u temp=LoadMw(SegBase(ss)+reg_sp);
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reg_sp+=2;
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return temp;
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};
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static INLINE Bit32u Pop_32() {
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Bit32u temp=LoadMd(SegBase(ss)+reg_sp);
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reg_sp+=4;
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return temp;
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};
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#define Save_Flagsw(FLAGW) \
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{ \
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flags.type=t_UNKNOWN; \
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flags.cf =(FLAGW & 0x001)>0;flags.pf =(FLAGW & 0x004)>0; \
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flags.af =(FLAGW & 0x010)>0;flags.zf =(FLAGW & 0x040)>0; \
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flags.sf =(FLAGW & 0x080)>0;flags.tf =(FLAGW & 0x100)>0; \
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flags.intf =(FLAGW & 0x200)>0; \
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flags.df =(FLAGW & 0x400)>0;flags.of =(FLAGW & 0x800)>0; \
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flags.io =(FLAGW >> 12) & 0x03; \
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flags.nt =(FLAGW & 0x4000)>0; \
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if (cpu.state & STATE_STACK32) {
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reg_esp-=4;
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SaveMd(SegBase(ss)+reg_esp,blah);
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} else {
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reg_sp-=4;
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SaveMd(SegBase(ss)+reg_sp,blah);
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}
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}
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static INLINE Bit16u Pop_16(void) {
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if (cpu.state & STATE_STACK32) {
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Bit16u temp=LoadMw(SegBase(ss)+reg_esp);
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reg_esp+=2;
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return temp;
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} else {
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Bit16u temp=LoadMw(SegBase(ss)+reg_sp);
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reg_sp+=2;
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return temp;
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}
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}
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static INLINE Bit32u Pop_32(void) {
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if (cpu.state & STATE_STACK32) {
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Bit32u temp=LoadMd(SegBase(ss)+reg_esp);
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reg_esp+=4;
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return temp;
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} else {
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Bit32u temp=LoadMd(SegBase(ss)+reg_sp);
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reg_sp+=4;
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return temp;
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}
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}
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#if 0
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if (flags.intf && PIC_IRQCheck) { \
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SaveIP(); \
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@ -47,12 +47,12 @@ switch (inst.code.op) {
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flags.type=inst.code.op;
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break;
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case t_INCb: case t_INCw: case t_INCd:
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flags.cf=get_CF();
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SETFLAGBIT(CF,get_CF());
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inst.op1.d=flags.result.d=inst.op1.d+1;
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flags.type=inst.code.op;
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break;
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case t_DECb: case t_DECw: case t_DECd:
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flags.cf=get_CF();
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SETFLAGBIT(CF,get_CF());
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inst.op1.d=flags.result.d=inst.op1.d-1;
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flags.type=inst.code.op;
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break;
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@ -170,150 +170,52 @@ switch (inst.code.op) {
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/* Special instructions */
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case O_IMULRw:
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inst.op1.ds=inst.op1.ds*inst.op2.ds;
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flags.type=t_MUL;
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if ((inst.op1.ds> -32768) && (inst.op1.ds<32767)) {
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flags.cf=false;flags.of=false;
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} else {
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flags.cf=true;flags.of=true;
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}
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DIMULW(inst.op1.ws,inst.op1.ws,inst.op2.ws,LoadD,SaveD);
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break;
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case O_IMULRd:
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{
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Bit64s res=(Bit64s)inst.op1.ds*(Bit64s)inst.op2.ds;
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inst.op1.ds=(Bit32s)res;
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flags.type=t_MUL;
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if ((res>-((Bit64s)(2147483647)+1)) && (res<(Bit64s)2147483647)) {
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flags.cf=false;flags.of=false;
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} else {
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flags.cf=true;flags.of=true;
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}
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break;
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}
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DIMULD(inst.op1.ds,inst.op1.ds,inst.op2.ds,LoadD,SaveD);
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break;
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case O_MULb:
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flags.type=t_MUL;
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reg_ax=reg_al*inst.op1.b;
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flags.cf=flags.of=((reg_ax & 0xff00) !=0);
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MULB(inst.op1.b,LoadD,0);
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goto nextopcode;
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case O_MULw:
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{
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Bit32u tempu=(Bit32u)reg_ax*(Bit32u)inst.op1.w;
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reg_ax=(Bit16u)(tempu);
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reg_dx=(Bit16u)(tempu >> 16);
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flags.type=t_MUL;
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flags.cf=flags.of=(reg_dx !=0);
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goto nextopcode;
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}
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MULW(inst.op1.w,LoadD,0);
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goto nextopcode;
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case O_MULd:
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{
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Bit64u tempu=(Bit64u)reg_eax*(Bit64u)inst.op1.d;
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reg_eax=(Bit32u)(tempu);
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reg_edx=(Bit32u)(tempu >> 32);
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flags.type=t_MUL;
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flags.cf=flags.of=(reg_edx !=0);
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goto nextopcode;
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}
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MULD(inst.op1.d,LoadD,0);
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goto nextopcode;
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case O_IMULb:
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flags.type=t_MUL;
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reg_ax=((Bit8s)reg_al)*inst.op1.bs;
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flags.cf=flags.of=!((reg_ax & 0xff80)==0xff80 || (reg_ax & 0xff80)==0x0000);
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IMULB(inst.op1.b,LoadD,0);
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goto nextopcode;
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case O_IMULw:
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{
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Bit32s temps=(Bit16s)reg_ax*inst.op1.ws;
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reg_ax=(Bit16s)(temps);
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reg_dx=(Bit16s)(temps >> 16);
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flags.type=t_MUL;
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flags.cf=flags.of=!((temps & 0xffffff80)==0xffffff80 || (temps & 0xffffff80)==0x0000);
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goto nextopcode;
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}
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IMULW(inst.op1.w,LoadD,0);
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goto nextopcode;
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case O_IMULd:
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{
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Bit64s temps=(Bit64s)((Bit32s)reg_eax)*(Bit64s)inst.op1.ds;
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reg_eax=(Bit32u)(temps);
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reg_edx=(Bit32u)(temps >> 32);
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flags.type=t_MUL;
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if ( (reg_edx==0xffffffff) && (reg_eax & 0x80000000) ) {
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flags.cf=flags.of=false;
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} else if ( (reg_edx==0x00000000) && (reg_eax<0x80000000) ) {
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flags.cf=flags.of=false;
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} else {
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flags.cf=flags.of=true;
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}
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goto nextopcode;
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}
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IMULD(inst.op1.d,LoadD,0);
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goto nextopcode;
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case O_DIVb:
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{
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if (!inst.op1.b) goto doint;
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Bitu val=reg_ax;Bitu quo=val/inst.op1.b;
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reg_ah=(Bit8u)(val % inst.op1.b);
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reg_al=(Bit8u)quo;
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if (quo!=reg_al) { inst.op1.b=0;goto doint;}
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goto nextopcode;
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}
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||||
DIVB(inst.op1.b,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_DIVw:
|
||||
{
|
||||
if (!inst.op1.w) goto doint;
|
||||
Bitu val=(reg_dx<<16)|reg_ax;Bitu quo=val/inst.op1.w;
|
||||
reg_dx=(Bit16u)(val % inst.op1.w);
|
||||
reg_ax=(Bit16u)quo;
|
||||
if (quo!=reg_ax) { inst.op1.b=0;goto doint;}
|
||||
goto nextopcode;
|
||||
}
|
||||
DIVW(inst.op1.w,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_DIVd:
|
||||
{
|
||||
if (!inst.op1.d) goto doint;
|
||||
Bit64u val=(((Bit64u)reg_edx)<<32)|reg_eax;
|
||||
Bit64u quo=val/inst.op1.d;
|
||||
reg_edx=(Bit32u)(val % inst.op1.d);
|
||||
reg_eax=(Bit32u)quo;
|
||||
if (quo!=(Bit64u)reg_eax) { inst.op1.b=0;goto doint;}
|
||||
goto nextopcode;
|
||||
}
|
||||
DIVD(inst.op1.d,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_IDIVb:
|
||||
{
|
||||
if (!inst.op1.b) goto doint;
|
||||
Bits val=(Bit16s)reg_ax;Bits quo=val/inst.op1.bs;
|
||||
reg_ah=(Bit8s)(val % inst.op1.bs);
|
||||
reg_al=(Bit8s)quo;
|
||||
if (quo!=(Bit8s)reg_al) { inst.op1.b=0;goto doint;}
|
||||
goto nextopcode;
|
||||
}
|
||||
IDIVB(inst.op1.b,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_IDIVw:
|
||||
{
|
||||
if (!inst.op1.w) goto doint;
|
||||
Bits val=(Bit32s)((reg_dx<<16)|reg_ax);Bits quo=val/inst.op1.ws;
|
||||
reg_dx=(Bit16u)(val % inst.op1.ws);
|
||||
reg_ax=(Bit16s)quo;
|
||||
if (quo!=(Bit16s)reg_ax) { inst.op1.b=0;goto doint;}
|
||||
goto nextopcode;
|
||||
}
|
||||
IDIVW(inst.op1.w,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_IDIVd:
|
||||
{
|
||||
if (!inst.op1.d) goto doint;
|
||||
Bit64s val=(((Bit64u)reg_edx)<<32)|reg_eax;
|
||||
Bit64s quo=val/inst.op1.ds;
|
||||
reg_edx=(Bit32s)(val % inst.op1.ds);
|
||||
reg_eax=(Bit32s)(quo);
|
||||
if (quo!=(Bit64s)((Bit32s)reg_eax)) { inst.op1.b=0;goto doint;}
|
||||
goto nextopcode;
|
||||
}
|
||||
IDIVD(inst.op1.d,LoadD,0);
|
||||
goto nextopcode;
|
||||
case O_AAM:
|
||||
reg_ah=reg_al / inst.op1.b;
|
||||
reg_al=reg_al % inst.op1.b;
|
||||
flags.type=t_UNKNOWN;
|
||||
flags.sf=(reg_ah & 0x80) > 0;
|
||||
flags.zf=(reg_ax == 0);
|
||||
//TODO PF
|
||||
flags.pf=0;
|
||||
AAM(inst.op1.b);
|
||||
goto nextopcode;
|
||||
case O_AAD:
|
||||
reg_al=reg_ah*inst.op1.b+reg_al;
|
||||
reg_ah=0;
|
||||
flags.cf=(reg_al>=0x80);
|
||||
flags.zf=(reg_al==0);
|
||||
//TODO PF
|
||||
flags.type=t_UNKNOWN;
|
||||
AAD(inst.op1.b);
|
||||
goto nextopcode;
|
||||
|
||||
case O_C_O: inst.cond=get_OF(); break;
|
||||
|
|
@ -363,19 +265,37 @@ switch (inst.code.op) {
|
|||
case O_SEGGS:
|
||||
inst.code.extra=gs;
|
||||
break;
|
||||
|
||||
|
||||
case O_SEGSS:
|
||||
inst.code.extra=ss;
|
||||
break;
|
||||
|
||||
case O_LOOP:
|
||||
if (--reg_cx) break;
|
||||
if (inst.prefix & PREFIX_ADDR) {
|
||||
if (--reg_ecx) break;
|
||||
} else {
|
||||
if (--reg_cx) break;
|
||||
}
|
||||
goto nextopcode;
|
||||
case O_LOOPZ:
|
||||
if (--reg_cx && get_ZF()) break;
|
||||
if (inst.prefix & PREFIX_ADDR) {
|
||||
if (--reg_ecx && get_ZF()) break;
|
||||
} else {
|
||||
if (--reg_cx && get_ZF()) break;
|
||||
}
|
||||
goto nextopcode;
|
||||
case O_LOOPNZ:
|
||||
if (--reg_cx && !get_ZF()) break;
|
||||
if (inst.prefix & PREFIX_ADDR) {
|
||||
if (--reg_ecx && !get_ZF()) break;
|
||||
} else {
|
||||
if (--reg_cx && !get_ZF()) break;
|
||||
}
|
||||
goto nextopcode;
|
||||
case O_JCXZ:
|
||||
if (reg_cx) goto nextopcode;
|
||||
if (inst.prefix & PREFIX_ADDR) {
|
||||
if (reg_ecx) goto nextopcode;
|
||||
} else {
|
||||
if (reg_cx) goto nextopcode;
|
||||
}
|
||||
break;
|
||||
case O_XCHG_AX:
|
||||
{
|
||||
|
|
@ -391,16 +311,28 @@ switch (inst.code.op) {
|
|||
inst.op1.d=temp;
|
||||
break;
|
||||
}
|
||||
case O_CALL_N:
|
||||
case O_CALLNw:
|
||||
SaveIP();
|
||||
Push_16(reg_ip);
|
||||
break;
|
||||
case O_CALL_F:
|
||||
Push_16(SegValue(cs));
|
||||
case O_CALLNd:
|
||||
SaveIP();
|
||||
Push_16(reg_ip);
|
||||
Push_32(reg_eip);
|
||||
break;
|
||||
doint:
|
||||
case O_CALLFw:
|
||||
SaveIP();
|
||||
CPU_CALL(false,inst.op2.d,inst.op1.d);
|
||||
LoadIP();
|
||||
goto nextopcode;
|
||||
case O_CALLFd:
|
||||
SaveIP();
|
||||
CPU_CALL(true,inst.op2.d,inst.op1.d);
|
||||
LoadIP();
|
||||
goto nextopcode;
|
||||
case O_JMPFw:
|
||||
CPU_JMP(false,inst.op2.d,inst.op1.d);
|
||||
LoadIP();
|
||||
goto nextopcode;
|
||||
case O_INT:
|
||||
SaveIP();
|
||||
#if C_DEBUG
|
||||
|
|
@ -448,6 +380,95 @@ doint:
|
|||
} else {
|
||||
E_Exit("Too high CallBack Number %d called",inst.op1.d);
|
||||
}
|
||||
case O_GRP6w:
|
||||
case O_GRP6d:
|
||||
switch (inst.rm_index) {
|
||||
case 0x02: /* LLDT */
|
||||
CPU_LLDT(inst.op1.d);
|
||||
goto nextopcode; /* Else value will saved */
|
||||
default:
|
||||
LOG(LOG_ERROR|LOG_CPU,"Group 6 Illegal subfunction %X",inst.rm_index);
|
||||
}
|
||||
break;
|
||||
case O_GRP7w:
|
||||
case O_GRP7d:
|
||||
switch (inst.rm_index) {
|
||||
case 0: /* SGDT */
|
||||
{
|
||||
Bitu limit,base;
|
||||
CPU_SGDT(limit,base);
|
||||
SaveMw(inst.rm_eaa,limit);
|
||||
SaveMd(inst.rm_eaa+2,base);
|
||||
break;
|
||||
}
|
||||
case 1: /* SIDT */
|
||||
{
|
||||
Bitu limit,base;
|
||||
CPU_SIDT(limit,base);
|
||||
SaveMw(inst.rm_eaa,limit);
|
||||
SaveMd(inst.rm_eaa+2,base);
|
||||
break;
|
||||
}
|
||||
case 2: /* LGDT */
|
||||
CPU_LGDT(LoadMw(inst.rm_eaa),LoadMd(inst.rm_eaa+2)&((inst.code.op == O_GRP7w) ? 0xFFFFFF : 0xFFFFFFFF));
|
||||
break;
|
||||
case 3: /* LIDT */
|
||||
CPU_LIDT(LoadMw(inst.rm_eaa),LoadMd(inst.rm_eaa+2)&((inst.code.op == O_GRP7w) ? 0xFFFFFF : 0xFFFFFFFF));
|
||||
break;
|
||||
case 4: /* SMSW */
|
||||
{
|
||||
Bitu word;CPU_SMSW(word);
|
||||
SaveMw(inst.rm_eaa,word);
|
||||
break;
|
||||
}
|
||||
case 6: /* LMSW */
|
||||
{
|
||||
Bitu word=LoadMw(inst.rm_eaa);
|
||||
CPU_LMSW(word);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
LOG(LOG_ERROR|LOG_CPU,"Group 7 Illegal subfunction %X",inst.rm_index);
|
||||
}
|
||||
break;
|
||||
case O_M_Cd_Rd:
|
||||
CPU_SET_CRX(inst.rm_index,inst.op1.d);
|
||||
break;
|
||||
case O_M_Rd_Cd:
|
||||
inst.op1.d=CPU_GET_CRX(inst.rm_index);
|
||||
break;
|
||||
case O_LAR:
|
||||
{
|
||||
Bitu ar;CPU_LAR(inst.op1.d,ar);
|
||||
inst.op2.d=ar;
|
||||
}
|
||||
break;
|
||||
case O_BTd:
|
||||
case O_BTSd:
|
||||
case O_BTCd:
|
||||
case O_BTRd:
|
||||
{
|
||||
Bitu val;PhysPt read;
|
||||
Bitu mask=1 << (inst.op1.d & 31);
|
||||
FILLFLAGS;
|
||||
if (inst.rm<0xc0) {
|
||||
read=inst.rm_eaa+4*(inst.op1.d / 32);
|
||||
val=mem_readd(read);
|
||||
} else {
|
||||
val=reg_32(inst.rm_eai);
|
||||
}
|
||||
SETFLAGBIT(CF,(val&mask)>0);
|
||||
if (inst.code.op==O_BTSd) val|=mask;
|
||||
if (inst.code.op==O_BTRd) val&=~mask;
|
||||
if (inst.code.op==O_BTCd) val^=mask;
|
||||
if (inst.code.op==O_BTd) break;
|
||||
if (inst.rm<0xc0) {
|
||||
mem_writed(read,val);
|
||||
} else {
|
||||
reg_32(inst.rm_eai)=val;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -80,15 +80,15 @@ static OpCode OpCodeTable[1024]={
|
|||
|
||||
|
||||
/* 0x70 - 0x77 */
|
||||
{L_Ibx ,O_C_O ,S_C_ADDIP,0 },{L_Ibx ,O_C_NO ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_B ,S_C_ADDIP,0 },{L_Ibx ,O_C_NB ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_Z ,S_C_ADDIP,0 },{L_Ibx ,O_C_NZ ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_BE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NBE ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_O ,S_C_AIPw,0 },{L_Ibx ,O_C_NO ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_B ,S_C_AIPw,0 },{L_Ibx ,O_C_NB ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_Z ,S_C_AIPw,0 },{L_Ibx ,O_C_NZ ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_BE ,S_C_AIPw,0 },{L_Ibx ,O_C_NBE ,S_C_AIPw,0 },
|
||||
/* 0x78 - 0x7f */
|
||||
{L_Ibx ,O_C_S ,S_C_ADDIP,0 },{L_Ibx ,O_C_NS ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_P ,S_C_ADDIP,0 },{L_Ibx ,O_C_NP ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_L ,S_C_ADDIP,0 },{L_Ibx ,O_C_NL ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_LE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NLE ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_S ,S_C_AIPw,0 },{L_Ibx ,O_C_NS ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_P ,S_C_AIPw,0 },{L_Ibx ,O_C_NP ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_L ,S_C_AIPw,0 },{L_Ibx ,O_C_NL ,S_C_AIPw,0 },
|
||||
{L_Ibx ,O_C_LE ,S_C_AIPw,0 },{L_Ibx ,O_C_NLE ,S_C_AIPw,0 },
|
||||
|
||||
|
||||
/* 0x80 - 0x87 */
|
||||
|
|
@ -109,7 +109,7 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_REGw ,O_XCHG_AX ,S_REGw ,REGI_SI},{L_REGw ,O_XCHG_AX ,S_REGw ,REGI_DI},
|
||||
/* 0x98 - 0x9f */
|
||||
{D_CBW ,0 ,0 ,0 },{D_CWD ,0 ,0 ,0 },
|
||||
{L_Ifw ,O_CALL_F ,S_CSIP ,0 },{L_ERROR ,0 ,0 ,0 },
|
||||
{L_Ifw ,O_CALLFw ,0 ,0 },{L_ERROR ,0 ,0 ,0 },
|
||||
{L_FLG ,0 ,S_PUSHw,0 },{L_POPw ,0 ,S_FLGw ,0 },
|
||||
{L_REGb ,0 ,S_FLGb ,REGI_AH},{L_FLG ,0 ,S_REGb ,REGI_AH},
|
||||
|
||||
|
|
@ -142,9 +142,9 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0 ,S_Eb ,M_Ib },{L_MODRM ,0 ,S_Ew ,M_Iw },
|
||||
/* 0xc8 - 0xcf */
|
||||
{D_ENTERw ,0 ,0 ,0 },{D_LEAVEw ,0 ,0 ,0 },
|
||||
{L_POPfw ,0 ,S_CSIPIw,0 },{L_POPfw ,0 ,S_CSIP ,0 },
|
||||
{D_RETFwIw ,0 ,0 ,0 },{D_RETFw ,0 ,0 ,0 },
|
||||
{L_VAL ,O_INT ,0 ,3 },{L_Ib ,O_INT ,0 ,0 },
|
||||
{L_INTO ,O_INT ,0 ,0 },{L_IRETw ,0 ,S_CSIP ,0 },
|
||||
{L_INTO ,O_INT ,0 ,0 },{D_IRETw ,0 ,0 ,0 },
|
||||
|
||||
/* 0xd0 - 0xd7 */
|
||||
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,6 ,0 ,M_GRP_1 },
|
||||
|
|
@ -159,13 +159,13 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 },
|
||||
|
||||
/* 0xe0 - 0xe7 */
|
||||
{L_Ibx ,O_LOOPNZ ,S_ADDIP,0 },{L_Ibx ,O_LOOPZ ,S_ADDIP,0 },
|
||||
{L_Ibx ,O_LOOP ,S_ADDIP,0 },{L_Ibx ,O_JCXZ ,S_ADDIP,0 },
|
||||
{L_Ibx ,O_LOOPNZ ,S_AIPw ,0 },{L_Ibx ,O_LOOPZ ,S_AIPw ,0 },
|
||||
{L_Ibx ,O_LOOP ,S_AIPw ,0 },{L_Ibx ,O_JCXZ ,S_AIPw ,0 },
|
||||
{L_Ib ,O_INb ,0 ,0 },{L_Ib ,O_INw ,0 ,0 },
|
||||
{L_Ib ,O_OUTb ,0 ,0 },{L_Ib ,O_OUTw ,0 ,0 },
|
||||
/* 0xe8 - 0xef */
|
||||
{L_Iw ,O_CALL_N ,S_ADDIP,0 },{L_Iwx ,0 ,S_ADDIP,0 },
|
||||
{L_Ifw ,0 ,S_CSIP ,0 },{L_Ibx ,0 ,S_ADDIP,0 },
|
||||
{L_Iw ,O_CALLNw ,S_AIPw ,0 },{L_Iwx ,0 ,S_AIPw ,0 },
|
||||
{L_Ifw ,O_JMPFw ,0 ,0 },{L_Ibx ,0 ,S_AIPw ,0 },
|
||||
{L_REGw ,O_INb ,0 ,REGI_DX},{L_REGw ,O_INw ,0 ,REGI_DX},
|
||||
{L_REGw ,O_OUTb ,0 ,REGI_DX},{L_REGw ,O_OUTw ,0 ,REGI_DX},
|
||||
|
||||
|
|
@ -181,7 +181,7 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0xb ,0 ,M_GRP },{L_MODRM ,0xc ,0 ,M_GRP },
|
||||
|
||||
/* 0x100 - 0x107 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_GRP6w ,0 ,0 },{L_MODRM ,O_GRP7w ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
|
@ -203,8 +203,8 @@ static OpCode OpCodeTable[1024]={
|
|||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x120 - 0x127 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_M_Rd_Cd ,S_Ed ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_M_Cd_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
|
|
@ -271,15 +271,15 @@ static OpCode OpCodeTable[1024]={
|
|||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x180 - 0x187 */
|
||||
{L_Iwx ,O_C_O ,S_C_ADDIP,0 },{L_Iwx ,O_C_NO ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_B ,S_C_ADDIP,0 },{L_Iwx ,O_C_NB ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_Z ,S_C_ADDIP,0 },{L_Iwx ,O_C_NZ ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_BE ,S_C_ADDIP,0 },{L_Iwx ,O_C_NBE ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_O ,S_C_AIPw,0 },{L_Iwx ,O_C_NO ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_B ,S_C_AIPw,0 },{L_Iwx ,O_C_NB ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_Z ,S_C_AIPw,0 },{L_Iwx ,O_C_NZ ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_BE ,S_C_AIPw,0 },{L_Iwx ,O_C_NBE ,S_C_AIPw,0 },
|
||||
/* 0x188 - 0x18f */
|
||||
{L_Iwx ,O_C_S ,S_C_ADDIP,0 },{L_Iwx ,O_C_NS ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_P ,S_C_ADDIP,0 },{L_Iwx ,O_C_NP ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_L ,S_C_ADDIP,0 },{L_Iwx ,O_C_NL ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_LE ,S_C_ADDIP,0 },{L_Iwx ,O_C_NLE ,S_C_ADDIP,0 },
|
||||
{L_Iwx ,O_C_S ,S_C_AIPw,0 },{L_Iwx ,O_C_NS ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_P ,S_C_AIPw,0 },{L_Iwx ,O_C_NP ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_L ,S_C_AIPw,0 },{L_Iwx ,O_C_NL ,S_C_AIPw,0 },
|
||||
{L_Iwx ,O_C_LE ,S_C_AIPw,0 },{L_Iwx ,O_C_NLE ,S_C_AIPw,0 },
|
||||
|
||||
/* 0x190 - 0x197 */
|
||||
{L_MODRM ,O_C_O ,S_C_Eb,0 },{L_MODRM ,O_C_NO ,S_C_Eb,0 },
|
||||
|
|
@ -294,23 +294,23 @@ static OpCode OpCodeTable[1024]={
|
|||
|
||||
/* 0x1a0 - 0x1a7 */
|
||||
{L_SEG ,0 ,S_PUSHw ,fs },{L_POPw ,0 ,S_SEGI ,fs },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_BTw ,0 ,0 },
|
||||
{L_MODRM ,O_DSHLw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHLw ,S_Ew ,M_EwGwCL },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x1a8 - 0x1af */
|
||||
{L_SEG ,0 ,S_PUSHw ,gs },{L_POPw ,0 ,S_SEGI ,gs },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_BTSw ,0 ,0 },
|
||||
{L_MODRM ,O_DSHRw ,S_Ew,M_EwGwIb },{L_MODRM ,O_DSHRw ,S_Ew ,M_EwGwCL },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRw ,S_Gw ,M_EwxGwx },
|
||||
|
||||
/* 0x1b0 - 0x1b7 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_SEGSS ,S_SEGGw,M_Efw },{L_MODRM ,O_BTRw ,0 ,0 },
|
||||
{L_MODRM ,O_SEGFS ,S_SEGGw,M_Efw },{L_MODRM ,O_SEGGS ,S_SEGGw,M_Efw },
|
||||
{L_MODRM ,0 ,S_Gw ,M_Eb },{L_MODRM ,0 ,S_Gw ,M_Ew },
|
||||
/* 0x1b8 - 0x1bf */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,0xe ,0 ,M_GRP },{L_MODRM ,O_BTCw ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,0 ,S_Gw ,M_Ebx },{L_MODRM ,0 ,S_Gw ,M_Ewx },
|
||||
|
||||
|
|
@ -429,8 +429,7 @@ static OpCode OpCodeTable[1024]={
|
|||
{D_PUSHAd ,0 ,0 ,0 },{D_POPAd ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_BOUNDd ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_PRESEG ,0 ,0 ,fs },{L_PRESEG ,0 ,0 ,gs },
|
||||
//TODO check ox66 0x66 prefix
|
||||
{0 ,0 ,0 ,0 },{L_PREADD ,0 ,0 ,0 },
|
||||
{L_PREOP ,0 ,0 ,0 },{L_PREADD ,0 ,0 ,0 },
|
||||
/* 0x268 - 0x26f */
|
||||
{L_Id ,0 ,S_PUSHd,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdId},
|
||||
{L_Ibx ,0 ,S_PUSHd,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdIbx},
|
||||
|
|
@ -438,15 +437,15 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_STRING ,R_OUTSB ,0 ,0 },{L_STRING ,R_OUTSD ,0 ,0 },
|
||||
|
||||
/* 0x270 - 0x277 */
|
||||
{L_Ibx ,O_C_O ,S_C_ADDIP,0 },{L_Ibx ,O_C_NO ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_B ,S_C_ADDIP,0 },{L_Ibx ,O_C_NB ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_Z ,S_C_ADDIP,0 },{L_Ibx ,O_C_NZ ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_BE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NBE ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_O ,S_C_AIPd,0 },{L_Ibx ,O_C_NO ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_B ,S_C_AIPd,0 },{L_Ibx ,O_C_NB ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_Z ,S_C_AIPd,0 },{L_Ibx ,O_C_NZ ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_BE ,S_C_AIPd,0 },{L_Ibx ,O_C_NBE ,S_C_AIPd,0 },
|
||||
/* 0x278 - 0x27f */
|
||||
{L_Ibx ,O_C_S ,S_C_ADDIP,0 },{L_Ibx ,O_C_NS ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_P ,S_C_ADDIP,0 },{L_Ibx ,O_C_NP ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_L ,S_C_ADDIP,0 },{L_Ibx ,O_C_NL ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_LE ,S_C_ADDIP,0 },{L_Ibx ,O_C_NLE ,S_C_ADDIP,0 },
|
||||
{L_Ibx ,O_C_S ,S_C_AIPd,0 },{L_Ibx ,O_C_NS ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_P ,S_C_AIPd,0 },{L_Ibx ,O_C_NP ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_L ,S_C_AIPd,0 },{L_Ibx ,O_C_NL ,S_C_AIPd,0 },
|
||||
{L_Ibx ,O_C_LE ,S_C_AIPd,0 },{L_Ibx ,O_C_NLE ,S_C_AIPd,0 },
|
||||
|
||||
/* 0x280 - 0x287 */
|
||||
{L_MODRM ,0 ,0 ,M_GRP },{L_MODRM ,2 ,0 ,M_GRP },
|
||||
|
|
@ -467,7 +466,7 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_SI},{L_REGd ,O_XCHG_EAX ,S_REGd ,REGI_DI},
|
||||
/* 0x298 - 0x29f */
|
||||
{D_CBW ,0 ,0 ,0 },{D_CDQ ,0 ,0 ,0 },
|
||||
{L_Ifd ,O_CALL_F ,S_CSIP ,0 },{L_ERROR ,0 ,0 ,0 },
|
||||
{L_Ifd ,O_CALLFd ,0 ,0 },{L_ERROR ,0 ,0 ,0 },
|
||||
{L_FLG ,0 ,S_PUSHd,0 },{L_POPd ,0 ,S_FLGd ,0 },
|
||||
{L_REGb ,0 ,S_FLGb ,REGI_AH},{L_FLG ,0 ,S_REGb ,REGI_AH},
|
||||
|
||||
|
|
@ -500,9 +499,9 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0 ,S_Eb ,M_Ib },{L_MODRM ,0 ,S_Ed ,M_Id },
|
||||
/* 0x2c8 - 0x2cf */
|
||||
{D_ENTERd ,0 ,0 ,0 },{D_LEAVEd ,0 ,0 ,0 },
|
||||
{L_POPfd ,0 ,S_CSIPIw,0 },{L_POPfd ,0 ,S_CSIP ,0 },
|
||||
{D_RETFdIw ,0 ,0 ,0 },{D_RETFd ,0 ,0 ,0 },
|
||||
{L_VAL ,O_INT ,0 ,3 },{L_Ib ,O_INT ,0 ,0 },
|
||||
{L_INTO ,O_INT ,0 ,0 },{L_IRETd ,0 ,S_CSIP ,0 },
|
||||
{L_INTO ,O_INT ,0 ,0 },{D_IRETd ,0 ,0 ,0 },
|
||||
|
||||
/* 0x2d0 - 0x2d7 */
|
||||
{L_MODRM ,5 ,0 ,M_GRP_1 },{L_MODRM ,7 ,0 ,M_GRP_1 },
|
||||
|
|
@ -516,13 +515,13 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0 ,0 ,0 },{L_MODRM ,0 ,0 ,0 },
|
||||
|
||||
/* 0x2e0 - 0x2e7 */
|
||||
{L_Ibx ,O_LOOPNZ ,S_ADDIP,0 },{L_Ibx ,O_LOOPZ ,S_ADDIP,0 },
|
||||
{L_Ibx ,O_LOOP ,S_ADDIP,0 },{L_Ibx ,O_JCXZ ,S_ADDIP,0 },
|
||||
{L_Ibx ,O_LOOPNZ ,S_AIPd ,0 },{L_Ibx ,O_LOOPZ ,S_AIPd ,0 },
|
||||
{L_Ibx ,O_LOOP ,S_AIPd ,0 },{L_Ibx ,O_JCXZ ,S_AIPd ,0 },
|
||||
{L_Ib ,O_INb ,0 ,0 },{L_Ib ,O_INd ,0 ,0 },
|
||||
{L_Ib ,O_OUTb ,0 ,0 },{L_Ib ,O_OUTd ,0 ,0 },
|
||||
/* 0x2e8 - 0x2ef */
|
||||
{L_Id ,O_CALL_N ,S_ADDIP,0 },{L_Idx ,0 ,S_ADDIP,0 },
|
||||
{L_Ifd ,0 ,S_CSIP ,0 },{L_Ibx ,0 ,S_ADDIP,0 },
|
||||
{L_Id ,O_CALLNd ,S_AIPd ,0 },{L_Idx ,0 ,S_AIPd ,0 },
|
||||
{L_Ifd ,O_JMPFd ,0 ,0 },{L_Ibx ,0 ,S_AIPd ,0 },
|
||||
{L_REGw ,O_INb ,0 ,REGI_DX},{L_REGw ,O_INd ,0 ,REGI_DX},
|
||||
{L_REGw ,O_OUTb ,0 ,REGI_DX},{L_REGw ,O_OUTd ,0 ,REGI_DX},
|
||||
|
||||
|
|
@ -538,179 +537,179 @@ static OpCode OpCodeTable[1024]={
|
|||
{L_MODRM ,0xb ,0 ,M_GRP },{L_MODRM ,0xd ,0 ,M_GRP },
|
||||
|
||||
|
||||
/* 0x200 - 0x207 */
|
||||
/* 0x300 - 0x307 */
|
||||
{L_MODRM ,O_GRP6d ,S_Ew ,M_Ew },{L_MODRM ,O_GRP7d ,0 ,0 },
|
||||
{L_MODRM ,O_LAR ,S_Gw ,M_Ew },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x208 - 0x20f */
|
||||
/* 0x308 - 0x30f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x210 - 0x217 */
|
||||
/* 0x310 - 0x317 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x218 - 0x21f */
|
||||
/* 0x318 - 0x31f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x220 - 0x227 */
|
||||
/* 0x320 - 0x327 */
|
||||
{L_MODRM ,O_M_Rd_Cd ,S_Ed ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,O_M_Cd_Rd ,0 ,M_Ed },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x328 - 0x32f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x228 - 0x22f */
|
||||
/* 0x330 - 0x337 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x338 - 0x33f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x230 - 0x237 */
|
||||
/* 0x340 - 0x347 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x238 - 0x23f */
|
||||
/* 0x348 - 0x34f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x240 - 0x247 */
|
||||
/* 0x350 - 0x357 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x248 - 0x24f */
|
||||
/* 0x358 - 0x35f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x250 - 0x257 */
|
||||
/* 0x360 - 0x367 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x258 - 0x25f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x260 - 0x267 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x268 - 0x26f */
|
||||
/* 0x368 - 0x36f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
|
||||
/* 0x270 - 0x277 */
|
||||
/* 0x370 - 0x377 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x278 - 0x27f */
|
||||
/* 0x378 - 0x37f */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x280 - 0x287 */
|
||||
{L_Idx ,O_C_O ,S_C_ADDIP,0 },{L_Idx ,O_C_NO ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_B ,S_C_ADDIP,0 },{L_Idx ,O_C_NB ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_Z ,S_C_ADDIP,0 },{L_Idx ,O_C_NZ ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_BE ,S_C_ADDIP,0 },{L_Idx ,O_C_NBE ,S_C_ADDIP,0 },
|
||||
/* 0x288 - 0x28f */
|
||||
{L_Idx ,O_C_S ,S_C_ADDIP,0 },{L_Idx ,O_C_NS ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_P ,S_C_ADDIP,0 },{L_Idx ,O_C_NP ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_L ,S_C_ADDIP,0 },{L_Idx ,O_C_NL ,S_C_ADDIP,0 },
|
||||
{L_Idx ,O_C_LE ,S_C_ADDIP,0 },{L_Idx ,O_C_NLE ,S_C_ADDIP,0 },
|
||||
/* 0x380 - 0x387 */
|
||||
{L_Idx ,O_C_O ,S_C_AIPd,0 },{L_Idx ,O_C_NO ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_B ,S_C_AIPd,0 },{L_Idx ,O_C_NB ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_Z ,S_C_AIPd,0 },{L_Idx ,O_C_NZ ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_BE ,S_C_AIPd,0 },{L_Idx ,O_C_NBE ,S_C_AIPd,0 },
|
||||
/* 0x388 - 0x38f */
|
||||
{L_Idx ,O_C_S ,S_C_AIPd,0 },{L_Idx ,O_C_NS ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_P ,S_C_AIPd,0 },{L_Idx ,O_C_NP ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_L ,S_C_AIPd,0 },{L_Idx ,O_C_NL ,S_C_AIPd,0 },
|
||||
{L_Idx ,O_C_LE ,S_C_AIPd,0 },{L_Idx ,O_C_NLE ,S_C_AIPd,0 },
|
||||
|
||||
/* 0x290 - 0x297 */
|
||||
/* 0x390 - 0x397 */
|
||||
{L_MODRM ,O_C_O ,S_C_Eb,0 },{L_MODRM ,O_C_NO ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_B ,S_C_Eb,0 },{L_MODRM ,O_C_NB ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_Z ,S_C_Eb,0 },{L_MODRM ,O_C_NZ ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_BE ,S_C_Eb,0 },{L_MODRM ,O_C_NBE ,S_C_Eb,0 },
|
||||
/* 0x298 - 0x29f */
|
||||
/* 0x398 - 0x39f */
|
||||
{L_MODRM ,O_C_S ,S_C_Eb,0 },{L_MODRM ,O_C_NS ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_P ,S_C_Eb,0 },{L_MODRM ,O_C_NP ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_L ,S_C_Eb,0 },{L_MODRM ,O_C_NL ,S_C_Eb,0 },
|
||||
{L_MODRM ,O_C_LE ,S_C_Eb,0 },{L_MODRM ,O_C_NLE ,S_C_Eb,0 },
|
||||
|
||||
/* 0x2a0 - 0x2a7 */
|
||||
/* 0x3a0 - 0x3a7 */
|
||||
{L_SEG ,0 ,S_PUSHd ,fs },{L_POPd ,0 ,S_SEGI ,fs },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_BTd ,0 ,0 },
|
||||
{L_MODRM ,O_DSHLd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHLd ,S_Ed ,M_EdGdCL },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x2a8 - 0x2af */
|
||||
/* 0x3a8 - 0x3af */
|
||||
{L_SEG ,0 ,S_PUSHd ,gs },{L_POPd ,0 ,S_SEGI ,gs },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_BTSd ,0 ,0 },
|
||||
{L_MODRM ,O_DSHRd ,S_Ed,M_EdGdIb },{L_MODRM ,O_DSHRd ,S_Ed ,M_EdGdCL },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_IMULRd ,S_Gd ,M_EdxGdx },
|
||||
|
||||
/* 0x2b0 - 0x2b7 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x3b0 - 0x3b7 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{L_MODRM ,O_BTRd ,0 ,0 },
|
||||
{L_MODRM ,O_SEGFS ,S_SEGGd,M_Efd },{L_MODRM ,O_SEGGS ,S_SEGGd,M_Efd },
|
||||
{L_MODRM ,0 ,S_Gd ,M_Eb },{L_MODRM ,0 ,S_Gd ,M_Ew },
|
||||
/* 0x2b8 - 0x2bf */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x3b8 - 0x3bf */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,0xf ,0 ,M_GRP },{L_MODRM ,O_BTCd ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{L_MODRM ,0 ,S_Gd ,M_Ebx },{L_MODRM ,0 ,S_Gd ,M_Ewx },
|
||||
|
||||
/* 0x2c0 - 0x2cc */
|
||||
/* 0x3c0 - 0x3cc */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x2c8 - 0x2cf */
|
||||
/* 0x3c8 - 0x3cf */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x2d0 - 0x2d7 */
|
||||
/* 0x3d0 - 0x3d7 */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x2d8 - 0x2df */
|
||||
/* 0x3d8 - 0x3df */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x2e0 - 0x2ee */
|
||||
/* 0x3e0 - 0x3ee */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x2e8 - 0x2ef */
|
||||
/* 0x3e8 - 0x3ef */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
||||
/* 0x2f0 - 0x2fc */
|
||||
/* 0x3f0 - 0x3fc */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
/* 0x2f8 - 0x2ff */
|
||||
/* 0x3f8 - 0x3ff */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
|
|
@ -785,16 +784,26 @@ static OpCode Groups[16][8]={
|
|||
{0 ,0 ,0 ,0 },{0 ,O_CBACK ,0 ,M_Iw },
|
||||
},{ /* 0x0c Group 5 Ew */
|
||||
{0 ,t_INCw ,S_Ew ,M_Ew },{0 ,t_DECw ,S_Ew ,M_Ew },
|
||||
{0 ,O_CALL_N ,S_IP ,M_Ew },{0 ,O_CALL_F ,S_CSIP ,M_Efw },
|
||||
{0 ,0 ,S_IP ,M_Ew },{0 ,0 ,S_CSIP ,M_Efw },
|
||||
{0 ,O_CALLNw ,S_IP ,M_Ew },{0 ,O_CALLFw ,0 ,M_Efw },
|
||||
{0 ,0 ,S_IP ,M_Ew },{0 ,O_JMPFw ,0 ,M_Efw },
|
||||
{0 ,0 ,S_PUSHw,M_Ew },{0 ,0 ,0 ,0 },
|
||||
},{ /* 0x0d Group 5 Ed */
|
||||
{0 ,t_INCd ,S_Ed ,M_Ed },{0 ,t_DECd ,S_Ed ,M_Ed },
|
||||
{0 ,O_CALL_N ,S_IP ,M_Ed },{0 ,O_CALL_F ,S_CSIP ,M_Efd },
|
||||
{0 ,0 ,S_IP ,M_Ed },{0 ,0 ,S_CSIP ,M_Efd },
|
||||
{0 ,O_CALLNd ,S_IP ,M_Ed },{0 ,O_CALLFd ,0 ,M_Efd },
|
||||
{0 ,0 ,S_IP ,M_Ed },{0 ,O_JMPFd ,0 ,M_Efd },
|
||||
{0 ,0 ,S_PUSHd,M_Ed },{0 ,0 ,0 ,0 },
|
||||
|
||||
|
||||
},{ /* 0x0e Group 8 Ew */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,O_BTw ,0 ,M_Ib },{0 ,O_BTSw ,0 ,M_Ib },
|
||||
{0 ,O_BTRw ,0 ,M_Ib },{0 ,O_BTCw ,0 ,M_Ib },
|
||||
},{ /* 0x0f Group 8 Ed */
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,0 ,0 ,0 },{0 ,0 ,0 ,0 },
|
||||
{0 ,O_BTd ,0 ,M_Ib },{0 ,O_BTSd ,0 ,M_Ib },
|
||||
{0 ,O_BTRd ,0 ,M_Ib },{0 ,O_BTCd ,0 ,M_Ib },
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -52,14 +52,14 @@ switch (inst.code.save) {
|
|||
reg_32(inst.code.extra)=inst.op1.d;
|
||||
break;
|
||||
case S_SEGI:
|
||||
SegSet16(inst.code.extra,inst.op1.w);
|
||||
CPU_SetSegGeneral((SegNames)inst.code.extra,inst.op1.w);
|
||||
break;
|
||||
case S_SEGm:
|
||||
SegSet16(inst.rm_index,inst.op1.w);
|
||||
CPU_SetSegGeneral((SegNames)inst.rm_index,inst.op1.w);
|
||||
break;
|
||||
case S_SEGGw:
|
||||
reg_16(inst.rm_index)=inst.op1.w;
|
||||
SegSet16(inst.code.extra,inst.op2.w);
|
||||
CPU_SetSegGeneral((SegNames)inst.code.extra,inst.op2.w);
|
||||
break;
|
||||
case S_PUSHw:
|
||||
Push_16(inst.op1.w);
|
||||
|
|
@ -68,19 +68,19 @@ switch (inst.code.save) {
|
|||
Push_32(inst.op1.d);
|
||||
break;
|
||||
|
||||
case S_C_ADDIP:
|
||||
case S_C_AIPw:
|
||||
if (!inst.cond) goto nextopcode;
|
||||
case S_ADDIP:
|
||||
case S_AIPw:
|
||||
SaveIP();
|
||||
reg_eip+=inst.op1.d;
|
||||
reg_eip&=0xffff;
|
||||
LoadIP();
|
||||
break;
|
||||
case S_CSIPIw:
|
||||
reg_esp+=Fetchw();
|
||||
case S_CSIP:
|
||||
reg_eip=inst.op1.d;
|
||||
SegSet16(cs,inst.op2.w);
|
||||
case S_C_AIPd:
|
||||
if (!inst.cond) goto nextopcode;
|
||||
case S_AIPd:
|
||||
SaveIP();
|
||||
reg_eip+=inst.op1.d;
|
||||
LoadIP();
|
||||
break;
|
||||
case S_IPIw:
|
||||
|
|
@ -91,15 +91,13 @@ switch (inst.code.save) {
|
|||
LoadIP();
|
||||
break;
|
||||
case S_FLGb:
|
||||
flags.of =get_OF();
|
||||
flags.type=t_UNKNOWN;
|
||||
flags.cf =(inst.op1.d & 0x001)>0;flags.pf =(inst.op1.d & 0x004)>0;
|
||||
flags.af =(inst.op1.d & 0x010)>0;flags.zf =(inst.op1.d & 0x040)>0;
|
||||
flags.sf =(inst.op1.d & 0x080)>0;
|
||||
SETFLAGSb(inst.op1.d);
|
||||
break;
|
||||
case S_FLGw:
|
||||
case S_FLGd: //TODO Check full 32bit flags one day
|
||||
Save_Flagsw(inst.op1.w);
|
||||
SETFLAGSw(inst.op1.d);
|
||||
break;
|
||||
case S_FLGd:
|
||||
SETFLAGSd(inst.op1.d);
|
||||
break;
|
||||
case 0:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -10,8 +10,9 @@
|
|||
else si_base=SegBase(ds);
|
||||
di_base=SegBase(es);
|
||||
if (inst.prefix & PREFIX_ADDR) {
|
||||
add_mask=0;
|
||||
si_index=reg_esi;di_index=reg_edi;
|
||||
add_mask=0xFFFFFFFF;
|
||||
si_index=reg_esi;
|
||||
di_index=reg_edi;
|
||||
count=reg_ecx;
|
||||
} else {
|
||||
add_mask=0xFFFF;
|
||||
|
|
@ -23,7 +24,7 @@
|
|||
count=1;
|
||||
}
|
||||
|
||||
add_index=flags.df ? -1 : 1;
|
||||
add_index=GETFLAG(DF) ? -1 : 1;
|
||||
if (count) switch (inst.code.op) {
|
||||
case R_OUTSB:
|
||||
for (;count>0;count--) {
|
||||
|
|
|
|||
|
|
@ -25,8 +25,8 @@ enum {
|
|||
L_PREOP,L_PREADD,L_PREREP,L_PREREPNE,
|
||||
L_STRING,
|
||||
|
||||
L_IRETw,L_IRETd,
|
||||
/* Direct ones */
|
||||
D_IRETw,D_IRETd,
|
||||
D_PUSHAw,D_PUSHAd,
|
||||
D_POPAw,D_POPAd,
|
||||
D_DAA,D_DAS,
|
||||
|
|
@ -39,6 +39,9 @@ enum {
|
|||
D_ENTERw,D_ENTERd,
|
||||
D_LEAVEw,D_LEAVEd,
|
||||
L_ERROR,
|
||||
|
||||
D_RETFw,D_RETFd,
|
||||
D_RETFwIw,D_RETFdIw,
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -48,12 +51,15 @@ enum {
|
|||
O_XCHG_AX,O_XCHG_EAX,
|
||||
O_IMULRw,O_IMULRd,
|
||||
O_BOUNDw,O_BOUNDd,
|
||||
O_CALL_N,O_CALL_F,
|
||||
O_CALLNw,O_CALLNd,
|
||||
O_CALLFw,O_CALLFd,
|
||||
O_JMPFw,O_JMPFd,
|
||||
|
||||
O_OPAL,O_ALOP,
|
||||
O_OPAX,O_AXOP,
|
||||
O_OPEAX,O_EAXOP,
|
||||
O_INT,
|
||||
O_SEGDS,O_SEGES,O_SEGFS,O_SEGGS,
|
||||
O_SEGDS,O_SEGES,O_SEGFS,O_SEGGS,O_SEGSS,
|
||||
O_LOOP,O_LOOPZ,O_LOOPNZ,O_JCXZ,
|
||||
O_INb,O_INw,O_INd,
|
||||
O_OUTb,O_OUTw,O_OUTd,
|
||||
|
|
@ -70,6 +76,18 @@ enum {
|
|||
O_DSHRw,O_DSHRd,
|
||||
O_C_O ,O_C_NO ,O_C_B ,O_C_NB ,O_C_Z ,O_C_NZ ,O_C_BE ,O_C_NBE,
|
||||
O_C_S ,O_C_NS ,O_C_P ,O_C_NP ,O_C_L ,O_C_NL ,O_C_LE ,O_C_NLE,
|
||||
|
||||
O_GRP6w,O_GRP6d,
|
||||
O_GRP7w,O_GRP7d,
|
||||
O_M_Cd_Rd,O_M_Rd_Cd,
|
||||
O_LAR,
|
||||
|
||||
O_BTw,O_BTSw,O_BTRw,O_BTCw,
|
||||
O_BTd,O_BTSd,O_BTRd,O_BTCd,
|
||||
O_BSFw,O_BSRw,
|
||||
|
||||
|
||||
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
@ -87,12 +105,11 @@ enum {
|
|||
S_SEGGw,S_SEGGd,
|
||||
|
||||
|
||||
S_ADDIP,S_C_ADDIP,
|
||||
S_AIPw,S_C_AIPw,
|
||||
S_AIPd,S_C_AIPd,
|
||||
|
||||
S_FLGb,S_FLGw,S_FLGd,
|
||||
S_IP,S_IPIw,
|
||||
S_CSIP,S_CSIPIw,
|
||||
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
@ -134,7 +151,7 @@ struct OpCode {
|
|||
static struct {
|
||||
Bitu entry;
|
||||
Bitu entry_default;
|
||||
Bit8u rm;
|
||||
Bitu rm;
|
||||
EAPoint rm_eaa;
|
||||
Bitu rm_off;
|
||||
Bitu rm_eai;
|
||||
|
|
@ -150,7 +167,7 @@ static struct {
|
|||
struct {
|
||||
EAPoint base;
|
||||
} seg;
|
||||
bool cond;
|
||||
Bitu cond;
|
||||
bool repz;
|
||||
Bitu prefix;
|
||||
} inst;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue