simplify memory checking handlers a bit
Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3004
This commit is contained in:
parent
d0b4e12779
commit
c6df37a834
4 changed files with 27 additions and 70 deletions
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@ -16,7 +16,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* $Id: paging.h,v 1.26 2007-09-29 13:23:59 c2woody Exp $ */
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/* $Id: paging.h,v 1.27 2007-09-30 14:10:04 c2woody Exp $ */
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#ifndef DOSBOX_PAGING_H
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#define DOSBOX_PAGING_H
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@ -57,9 +57,9 @@ public:
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virtual void writed(PhysPt addr,Bitu val);
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virtual HostPt GetHostReadPt(Bitu phys_page);
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virtual HostPt GetHostWritePt(Bitu phys_page);
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virtual bool readb_checked(PhysPt addr, Bitu * val);
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virtual bool readw_checked(PhysPt addr, Bitu * val);
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virtual bool readd_checked(PhysPt addr, Bitu * val);
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virtual bool readb_checked(PhysPt addr,Bit8u * val);
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virtual bool readw_checked(PhysPt addr,Bit16u * val);
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virtual bool readd_checked(PhysPt addr,Bit32u * val);
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virtual bool writeb_checked(PhysPt addr,Bitu val);
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virtual bool writew_checked(PhysPt addr,Bitu val);
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virtual bool writed_checked(PhysPt addr,Bitu val);
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@ -231,13 +231,7 @@ INLINE bool mem_readb_checked(PhysPt address, Bit8u * val) {
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if (paging.tlb.read[index]) {
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*val=host_readb(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readb_checked(address, &uval);
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*val=(Bit8u)uval;
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return retval;
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}
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} else return paging.tlb.handler[index]->readb_checked(address, val);
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}
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INLINE bool mem_readw_checked(PhysPt address, Bit16u * val) {
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@ -246,13 +240,7 @@ INLINE bool mem_readw_checked(PhysPt address, Bit16u * val) {
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if (paging.tlb.read[index]) {
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*val=host_readw(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readw_checked(address, &uval);
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*val=(Bit16u)uval;
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return retval;
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}
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} else return paging.tlb.handler[index]->readw_checked(address, val);
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} else return mem_unalignedreadw_checked(address, val);
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}
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@ -262,13 +250,7 @@ INLINE bool mem_readd_checked(PhysPt address, Bit32u * val) {
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if (paging.tlb.read[index]) {
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*val=host_readd(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readd_checked(address, &uval);
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*val=(Bit32u)uval;
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return retval;
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}
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} else return paging.tlb.handler[index]->readd_checked(address, val);
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} else return mem_unalignedreadd_checked(address, val);
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}
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@ -461,13 +461,8 @@ static void dyn_read_intro(DynReg * addr,bool release_addr=true) {
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cache_addw(0xc18b); // mov eax,ecx
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}
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bool mem_readb_checked_x86x(PhysPt address) {
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Bitu index=(address>>12);
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readb_checked(address, &uval);
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core_dyn.readdata=(Bit8u)uval;
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return retval;
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bool mem_readb_checked_dcx86(PhysPt address) {
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return paging.tlb.handler[address>>12]->readb_checked(address, (Bit8u*)(&core_dyn.readdata));
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}
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static void dyn_read_byte(DynReg * addr,DynReg * dst,Bitu high) {
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@ -489,7 +484,7 @@ static void dyn_read_byte(DynReg * addr,DynReg * dst,Bitu high) {
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gen_fill_branch(je_loc);
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cache_addb(0x51); // push ecx
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cache_addb(0xe8);
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cache_addd(((Bit32u)&mem_readb_checked_x86x) - (Bit32u)cache.pos-4);
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cache_addd(((Bit32u)&mem_readb_checked_dcx86) - (Bit32u)cache.pos-4);
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cache_addw(0xc483); // add esp,4
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cache_addb(0x04);
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cache_addw(0x012c); // sub al,1
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@ -527,7 +522,7 @@ static void dyn_read_byte_release(DynReg * addr,DynReg * dst,Bitu high) {
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gen_fill_branch(je_loc);
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cache_addb(0x51); // push ecx
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cache_addb(0xe8);
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cache_addd(((Bit32u)&mem_readb_checked_x86x) - (Bit32u)cache.pos-4);
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cache_addd(((Bit32u)&mem_readb_checked_dcx86) - (Bit32u)cache.pos-4);
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cache_addw(0xc483); // add esp,4
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cache_addb(0x04);
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cache_addw(0x012c); // sub al,1
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@ -546,18 +541,14 @@ static void dyn_read_byte_release(DynReg * addr,DynReg * dst,Bitu high) {
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dst->flags|=DYNFLG_CHANGED;
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}
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bool mem_readd_checked_x86x(PhysPt address) {
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bool mem_readd_checked_dcx86(PhysPt address) {
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if ((address & 0xfff)<0xffd) {
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Bitu index=(address>>12);
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if (paging.tlb.read[index]) {
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core_dyn.readdata=host_readd(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readd_checked(address, &uval);
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core_dyn.readdata=(Bit32u)uval;
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return retval;
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return paging.tlb.handler[index]->readd_checked(address, &core_dyn.readdata);
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}
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} else return mem_unalignedreadd_checked(address, &core_dyn.readdata);
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}
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@ -589,7 +580,7 @@ static void dyn_read_word(DynReg * addr,DynReg * dst,bool dword) {
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gen_fill_branch(je_loc);
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cache_addb(0x51); // push ecx
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cache_addb(0xe8);
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cache_addd(((Bit32u)&mem_readd_checked_x86x) - (Bit32u)cache.pos-4);
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cache_addd(((Bit32u)&mem_readd_checked_dcx86) - (Bit32u)cache.pos-4);
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cache_addw(0xc483); // add esp,4
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cache_addb(0x04);
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cache_addw(0x012c); // sub al,1
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@ -635,7 +626,7 @@ static void dyn_read_word_release(DynReg * addr,DynReg * dst,bool dword) {
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gen_fill_branch(je_loc);
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cache_addb(0x51); // push ecx
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cache_addb(0xe8);
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cache_addd(((Bit32u)&mem_readd_checked_x86x) - (Bit32u)cache.pos-4);
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cache_addd(((Bit32u)&mem_readd_checked_dcx86) - (Bit32u)cache.pos-4);
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cache_addw(0xc483); // add esp,4
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cache_addb(0x04);
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cache_addw(0x012c); // sub al,1
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@ -570,11 +570,7 @@ bool DRC_CALL_CONV mem_readb_checked_drc(PhysPt address) {
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*((Bit8u*)(&core_dynrec.readdata))=host_readb(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readb_checked(address, &uval);
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*((Bit8u*)(&core_dynrec.readdata))=(Bit8u)uval;
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return retval;
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return paging.tlb.handler[index]->readb_checked(address, (Bit8u*)(&core_dynrec.readdata));
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}
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}
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@ -594,13 +590,7 @@ bool DRC_CALL_CONV mem_readw_checked_drc(PhysPt address) {
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if (paging.tlb.read[index]) {
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*((Bit16u*)(&core_dynrec.readdata))=host_readw(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readw_checked(address, &uval);
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*((Bit16u*)(&core_dynrec.readdata))=(Bit16u)uval;
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return retval;
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}
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} else return paging.tlb.handler[index]->readw_checked(address, (Bit16u*)(&core_dynrec.readdata));
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} else return mem_unalignedreadw_checked(address, ((Bit16u*)(&core_dynrec.readdata)));
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}
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@ -611,13 +601,7 @@ bool DRC_CALL_CONV mem_readd_checked_drc(PhysPt address) {
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if (paging.tlb.read[index]) {
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*((Bit32u*)(&core_dynrec.readdata))=host_readd(paging.tlb.read[index]+address);
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return false;
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} else {
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Bitu uval;
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bool retval;
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retval=paging.tlb.handler[index]->readd_checked(address, &uval);
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*((Bit32u*)(&core_dynrec.readdata))=(Bit32u)uval;
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return retval;
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}
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} else return paging.tlb.handler[index]->readd_checked(address, (Bit32u*)(&core_dynrec.readdata));
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} else return mem_unalignedreadd_checked(address, ((Bit32u*)(&core_dynrec.readdata)));
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}
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@ -75,14 +75,14 @@ HostPt PageHandler::GetHostWritePt(Bitu /*phys_page*/) {
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return 0;
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}
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bool PageHandler::readb_checked(PhysPt addr, Bitu * val) {
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*val=readb(addr); return false;
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bool PageHandler::readb_checked(PhysPt addr, Bit8u * val) {
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*val=(Bit8u)readb(addr); return false;
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}
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bool PageHandler::readw_checked(PhysPt addr, Bitu * val) {
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*val=readw(addr); return false;
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bool PageHandler::readw_checked(PhysPt addr, Bit16u * val) {
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*val=(Bit16u)readw(addr); return false;
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}
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bool PageHandler::readd_checked(PhysPt addr, Bitu * val) {
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*val=readd(addr); return false;
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bool PageHandler::readd_checked(PhysPt addr, Bit32u * val) {
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*val=(Bit32u)readd(addr); return false;
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}
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bool PageHandler::writeb_checked(PhysPt addr,Bitu val) {
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writeb(addr,val); return false;
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@ -185,19 +185,19 @@ public:
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InitPage(addr,true);
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mem_writed(addr,val);
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}
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bool readb_checked(PhysPt addr, Bitu * val) {
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bool readb_checked(PhysPt addr, Bit8u * val) {
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if (InitPage(addr,false,true)) {
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*val=mem_readb(addr);
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return false;
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} else return true;
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}
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bool readw_checked(PhysPt addr, Bitu * val) {
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bool readw_checked(PhysPt addr, Bit16u * val) {
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if (InitPage(addr,false,true)){
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*val=mem_readw(addr);
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return false;
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} else return true;
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}
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bool readd_checked(PhysPt addr, Bitu * val) {
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bool readd_checked(PhysPt addr, Bit32u * val) {
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if (InitPage(addr,false,true)) {
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*val=mem_readd(addr);
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return false;
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