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Flag handling (mostly undocumented behavior) for normal core: overflow flag for divide instructions, zero and sign flags for integer multiply instructions. Fixes A320 Airbus and Perfect General.

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@4098
This commit is contained in:
ripsaw8080 2018-05-03 17:11:36 +00:00
parent 630b9befb5
commit e01a04aee9
1 changed files with 12 additions and 0 deletions
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12
src/cpu/instructions.h
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@ -679,6 +679,7 @@
if (quo>0xff) EXCEPTION(0); \
reg_ah=rem; \
reg_al=quo8; \
SETFLAGBIT(OF,false); \
}
@ -693,6 +694,7 @@
if (quo!=(Bit32u)quo16) EXCEPTION(0); \
reg_dx=rem; \
reg_ax=quo16; \
SETFLAGBIT(OF,false); \
}
#define DIVD(op1,load,save) \
@ -706,6 +708,7 @@
if (quo!=(Bit64u)quo32) EXCEPTION(0); \
reg_edx=rem; \
reg_eax=quo32; \
SETFLAGBIT(OF,false); \
}
@ -719,6 +722,7 @@
if (quo!=(Bit16s)quo8s) EXCEPTION(0); \
reg_ah=rem; \
reg_al=quo8s; \
SETFLAGBIT(OF,false); \
}
@ -733,6 +737,7 @@
if (quo!=(Bit32s)quo16s) EXCEPTION(0); \
reg_dx=rem; \
reg_ax=quo16s; \
SETFLAGBIT(OF,false); \
}
#define IDIVD(op1,load,save) \
@ -746,12 +751,15 @@
if (quo!=(Bit64s)quo32s) EXCEPTION(0); \
reg_edx=rem; \
reg_eax=quo32s; \
SETFLAGBIT(OF,false); \
}
#define IMULB(op1,load,save) \
{ \
reg_ax=((Bit8s)reg_al) * ((Bit8s)(load(op1))); \
FillFlagsNoCFOF(); \
SETFLAGBIT(ZF,reg_al == 0); \
SETFLAGBIT(SF,reg_al & 0x80); \
if ((reg_ax & 0xff80)==0xff80 || \
(reg_ax & 0xff80)==0x0000) { \
SETFLAGBIT(CF,false);SETFLAGBIT(OF,false); \
@ -767,6 +775,8 @@
reg_ax=(Bit16s)(temps); \
reg_dx=(Bit16s)(temps >> 16); \
FillFlagsNoCFOF(); \
SETFLAGBIT(ZF,reg_ax == 0); \
SETFLAGBIT(SF,reg_ax & 0x8000); \
if (((temps & 0xffff8000)==0xffff8000 || \
(temps & 0xffff8000)==0x0000)) { \
SETFLAGBIT(CF,false);SETFLAGBIT(OF,false); \
@ -782,6 +792,8 @@
reg_eax=(Bit32u)(temps); \
reg_edx=(Bit32u)(temps >> 32); \
FillFlagsNoCFOF(); \
SETFLAGBIT(ZF,reg_eax == 0); \
SETFLAGBIT(SF,reg_eax & 0x80000000); \
if ((reg_edx==0xffffffff) && \
(reg_eax & 0x80000000) ) { \
SETFLAGBIT(CF,false);SETFLAGBIT(OF,false); \