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swap parameter loading to work around register clashing for x86_64 (drc dynamic fpu)

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Imported-from: https://svn.code.sf.net/p/dosbox/code-0/dosbox/trunk@3005
This commit is contained in:
Sebastian Strohhäcker 2007-10-01 20:31:16 +00:00
parent c6df37a834
commit 138adbcf39
1 changed files with 5 additions and 5 deletions
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10
src/cpu/core_dynrec/dyn_fpu.h
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@ -289,8 +289,8 @@ static void dyn_fpu_esc1(){
switch(decode.modrm.reg){
case 0x00: /* FLD float*/
gen_call_function_raw((void*)&FPU_PREP_PUSH);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
dyn_fill_ea(FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
gen_call_function_RR((void*)&FPU_FLD_F32,FC_OP1,FC_OP2);
break;
case 0x01: /* UNKNOWN */
@ -532,8 +532,8 @@ static void dyn_fpu_esc5(){
case 0x07: /*FNSTSW */
gen_mov_word_to_reg(FC_OP1,(void*)(&TOP),true);
gen_call_function_R((void*)&FPU_SET_TOP,FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&fpu.sw),true);
dyn_fill_ea(FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&fpu.sw),true);
gen_call_function_RR((void*)&mem_writew,FC_OP1,FC_OP2);
break;
default:
@ -633,8 +633,8 @@ static void dyn_fpu_esc7(){
switch(decode.modrm.reg){
case 0x00: /* FILD Bit16s */
gen_call_function_raw((void*)&FPU_PREP_PUSH);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
dyn_fill_ea(FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
gen_call_function_RR((void*)&FPU_FLD_I16,FC_OP1,FC_OP2);
break;
case 0x01:
@ -651,14 +651,14 @@ static void dyn_fpu_esc7(){
break;
case 0x04: /* FBLD packed BCD */
gen_call_function_raw((void*)&FPU_PREP_PUSH);
dyn_fill_ea(FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
dyn_fill_ea(FC_OP1);
gen_call_function_RR((void*)&FPU_FBLD,FC_OP1,FC_OP2);
break;
case 0x05: /* FILD Bit64s */
gen_call_function_raw((void*)&FPU_PREP_PUSH);
dyn_fill_ea(FC_OP1);
gen_mov_word_to_reg(FC_OP2,(void*)(&TOP),true);
dyn_fill_ea(FC_OP1);
gen_call_function_RR((void*)&FPU_FLD_I64,FC_OP1,FC_OP2);
break;
case 0x06: /* FBSTP packed BCD */